* [PATCH 0/2] DPCD Backlight Control
@ 2016-01-12 15:59 Yetunde Adebisi
2016-01-12 15:59 ` [PATCH 1/2] drm/dp: Add definition for Display Control DPCD Registers capability size Yetunde Adebisi
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Yetunde Adebisi @ 2016-01-12 15:59 UTC (permalink / raw)
To: intel-gfx; +Cc: Yetunde Adebisi
These patches add support for Backlight Control using DPCD registers on eDP
displays.
- Patch 1 adds macro for DPCD registers capability size to drm_dp_helper.h
A copy of this patch has also been sent to dri-devel list.
- Patch 2 Implements functionaly for DPCD Backlight Control
Yetunde Adebisi (2):
drm/dp: Add definition for Display Control DPCD Registers capability
size
drm/i915: Add Backlight Control using DPCD for eDP connectors (v5)
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_dp.c | 17 ++-
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 169 ++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_drv.h | 6 +
drivers/gpu/drm/i915/intel_panel.c | 4 +
include/drm/drm_dp_helper.h | 1 +
6 files changed, 192 insertions(+), 6 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c
--
1.9.3
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 1/2] drm/dp: Add definition for Display Control DPCD Registers capability size 2016-01-12 15:59 [PATCH 0/2] DPCD Backlight Control Yetunde Adebisi @ 2016-01-12 15:59 ` Yetunde Adebisi 2016-01-12 15:59 ` [PATCH 2/2] drm/i915: Add Backlight Control using DPCD for eDP connectors (v5) Yetunde Adebisi 2016-01-12 17:49 ` ✗ warning: Fi.CI.BAT Patchwork 2 siblings, 0 replies; 10+ messages in thread From: Yetunde Adebisi @ 2016-01-12 15:59 UTC (permalink / raw) To: intel-gfx; +Cc: Yetunde Adebisi, Jani Nikula, dri-devel This is used when reading Display Control capability Registers on the sink device. cc: Jani Nikula <jani.nikula@intel.com> cc: dri-devel@lists.freedesktop.org Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com> --- include/drm/drm_dp_helper.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1252108..92d9a52 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI #define DP_BRANCH_OUI_HEADER_SIZE 0xc #define DP_RECEIVER_CAP_SIZE 0xf #define EDP_PSR_RECEIVER_CAP_SIZE 2 +#define EDP_DISPLAY_CTL_CAP_SIZE 3 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); -- 1.9.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/2] drm/i915: Add Backlight Control using DPCD for eDP connectors (v5) 2016-01-12 15:59 [PATCH 0/2] DPCD Backlight Control Yetunde Adebisi 2016-01-12 15:59 ` [PATCH 1/2] drm/dp: Add definition for Display Control DPCD Registers capability size Yetunde Adebisi @ 2016-01-12 15:59 ` Yetunde Adebisi 2016-01-12 16:16 ` Daniel Stone 2016-01-12 17:49 ` ✗ warning: Fi.CI.BAT Patchwork 2 siblings, 1 reply; 10+ messages in thread From: Yetunde Adebisi @ 2016-01-12 15:59 UTC (permalink / raw) To: intel-gfx; +Cc: Yetunde Adebisi, Jani Nikula This patch adds support for eDP backlight control using DPCD registers to backlight hooks in intel_panel. It checks for backlight control over AUX channel capability and sets up function pointers to get and set the backlight brightness level if supported. v2: Moved backlight functions from intel_dp.c into a new file intel_dp_aux_backlight.c. Also moved reading of eDP display control registers to intel_dp_get_dpcd v3: Correct some formatting mistakes v4: Updated to use AUX backlight control if PWM control is not possible (Jani) v5: Moved call to initialize backlight registers to dp_aux_setup_backlight This patch depends on http://patchwork.freedesktop.org/patch/64253/ Cc: Bob Paauwe <bob.j.paauwe@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com> --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/intel_dp.c | 17 ++- drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 169 ++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 6 + drivers/gpu/drm/i915/intel_panel.c | 4 + 5 files changed, 191 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_dp_aux_backlight.c diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 0851de07..41250cc 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -77,6 +77,7 @@ i915-y += dvo_ch7017.o \ dvo_tfp410.o \ intel_crt.o \ intel_ddi.o \ + intel_dp_aux_backlight.o \ intel_dp_link_training.o \ intel_dp_mst.o \ intel_dp.o \ diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 796e3d3..b9dabad 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3186,7 +3186,7 @@ static void chv_dp_post_pll_disable(struct intel_encoder *encoder) * Sinks are *supposed* to come up within 1ms from an off state, but we're also * supposed to retry 3 times per the spec. */ -static ssize_t +ssize_t intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, void *buffer, size_t size) { @@ -3853,7 +3853,6 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_device *dev = dig_port->base.base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - uint8_t rev; if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, sizeof(intel_dp->dpcd)) < 0) @@ -3889,6 +3888,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) DRM_DEBUG_KMS("PSR2 %s on sink", dev_priv->psr.psr2_support ? "supported" : "not supported"); } + + /* Read the eDP Display control capabilities registers */ + memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd)); + if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && + (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, + intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == + sizeof(intel_dp->edp_dpcd))) + DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd), + intel_dp->edp_dpcd); } DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", @@ -3896,10 +3904,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) yesno(drm_dp_tps3_supported(intel_dp->dpcd))); /* Intermediate frequency support */ - if (is_edp(intel_dp) && - (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && - (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) && - (rev >= 0x03)) { /* eDp v1.4 or higher */ + if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */ __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; int i; diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c new file mode 100644 index 0000000..3ef28e7 --- /dev/null +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c @@ -0,0 +1,169 @@ +/* + * Copyright © 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#include "intel_drv.h" + +static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable) +{ + uint8_t reg_val = 0; + + if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, + ®_val, sizeof(reg_val)) < 0) { + DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n", + DP_EDP_DISPLAY_CONTROL_REGISTER); + return; + } + if (enable) + reg_val |= DP_EDP_BACKLIGHT_ENABLE; + else + reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE); + + if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, + reg_val) < 0) { + DRM_DEBUG_KMS("Failed to %s aux backlight\n", + enable ? "enable" : "disable"); + } +} + +/* + * Read the current backlight value from DPCD register(s) based + * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported + */ +static uint32_t intel_dp_aux_get_backlight(struct intel_connector *connector) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base); + uint8_t read_val[2] = { 0x0 }; + uint16_t level = 0; + + if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, + &read_val, sizeof(read_val)) < 0) { + DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n", + DP_EDP_BACKLIGHT_BRIGHTNESS_MSB); + return 0; + } + level = read_val[0]; + if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) + level = (read_val[0] << 8 | read_val[1]); + + return level; +} + +/* + * Sends the current backlight level over the aux channel, checking if its using + * 8-bit or 16 bit value (MSB and LSB) + */ +static void +intel_dp_aux_set_backlight(struct intel_connector *connector, u32 level) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base); + uint8_t vals[2] = { 0x0 }; + + vals[0] = level; + + /* Write the MSB and/or LSB */ + if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) { + vals[0] = (level & 0xFF00) >> 8; + vals[1] = (level & 0xFF); + } + if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, + vals, sizeof(vals)) < 0) { + DRM_DEBUG_KMS("Failed to write aux backlight level\n"); + return; + } +} + +static void intel_dp_aux_enable_backlight(struct intel_connector *connector) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base); + uint8_t dpcd_buf = 0; + + set_aux_backlight_enable(intel_dp, true); + + if ((intel_dp_dpcd_read_wake(&intel_dp->aux, + DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf, 1) == 1) && + ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) == + DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET)) + drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, + (dpcd_buf | DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD)); +} + +static void intel_dp_aux_disable_backlight(struct intel_connector *connector) +{ + set_aux_backlight_enable(enc_to_intel_dp(&connector->encoder->base), false); +} + +static int intel_dp_aux_setup_backlight(struct intel_connector *connector, + enum pipe pipe) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base); + struct intel_panel *panel = &connector->panel; + + intel_dp_aux_enable_backlight(connector); + + if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) + panel->backlight.max = 0xFFFF; + else + panel->backlight.max = 0xFF; + + panel->backlight.min = 0; + panel->backlight.level = intel_dp_aux_get_backlight(connector); + + panel->backlight.enabled = panel->backlight.level != 0; + + return 0; +} + +static bool +intel_dp_aux_display_control_capable(struct intel_connector *connector) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base); + + /* Check the eDP Display control capabilities registers to determine if + * the panel can support backlight control over the aux channel + */ + if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP && + (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) && + !(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) { + + DRM_DEBUG_KMS("AUX Backlight Control Supported!\n"); + return true; + } + return false; +} + +int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector) +{ + struct intel_panel *panel = &intel_connector->panel; + + if (!intel_dp_aux_display_control_capable(intel_connector)) + return -ENODEV; + + panel->backlight.setup = intel_dp_aux_setup_backlight; + panel->backlight.enable = intel_dp_aux_enable_backlight; + panel->backlight.disable = intel_dp_aux_disable_backlight; + panel->backlight.set = intel_dp_aux_set_backlight; + panel->backlight.get = intel_dp_aux_get_backlight; + + return 0; +} diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index bdfe403..06663cb 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -781,6 +781,7 @@ struct intel_dp { uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; + uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; /* sink rates as reported by DP_SUPPORTED_LINK_RATES */ uint8_t num_sink_rates; int sink_rates[DP_MAX_SUPPORTED_RATES]; @@ -1307,6 +1308,11 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); bool intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]); +ssize_t intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, + void *buffer, size_t size); + +/* intel_dp_aux_backlight.c */ +int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector); /* intel_dp_mst.c */ int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 21ee647..941c6fe 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -1720,6 +1720,10 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel) container_of(panel, struct intel_connector, panel); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); + if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP && + intel_dp_aux_init_backlight_funcs(connector) == 0) + return; + if (IS_BROXTON(dev_priv)) { panel->backlight.setup = bxt_setup_backlight; panel->backlight.enable = bxt_enable_backlight; -- 1.9.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] drm/i915: Add Backlight Control using DPCD for eDP connectors (v5) 2016-01-12 15:59 ` [PATCH 2/2] drm/i915: Add Backlight Control using DPCD for eDP connectors (v5) Yetunde Adebisi @ 2016-01-12 16:16 ` Daniel Stone 2016-01-12 17:18 ` Jani Nikula 0 siblings, 1 reply; 10+ messages in thread From: Daniel Stone @ 2016-01-12 16:16 UTC (permalink / raw) To: Yetunde Adebisi; +Cc: Jani Nikula, intel-gfx On 12 January 2016 at 15:59, Yetunde Adebisi <yetundex.adebisi@intel.com> wrote: > + memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd)); gcc should've warned you about this; you're memsetting too small a size. Cheers, Daniel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] drm/i915: Add Backlight Control using DPCD for eDP connectors (v5) 2016-01-12 16:16 ` Daniel Stone @ 2016-01-12 17:18 ` Jani Nikula 2016-01-12 17:27 ` Daniel Stone 0 siblings, 1 reply; 10+ messages in thread From: Jani Nikula @ 2016-01-12 17:18 UTC (permalink / raw) To: Daniel Stone, Yetunde Adebisi; +Cc: intel-gfx On Tue, 12 Jan 2016, Daniel Stone <daniel@fooishbar.org> wrote: > On 12 January 2016 at 15:59, Yetunde Adebisi <yetundex.adebisi@intel.com> wrote: >> + memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd)); > > gcc should've warned you about this; you're memsetting too small a size. Really? I think it's fine. BR, Jani. -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] drm/i915: Add Backlight Control using DPCD for eDP connectors (v5) 2016-01-12 17:18 ` Jani Nikula @ 2016-01-12 17:27 ` Daniel Stone 2016-01-12 17:30 ` Jani Nikula 0 siblings, 1 reply; 10+ messages in thread From: Daniel Stone @ 2016-01-12 17:27 UTC (permalink / raw) To: Jani Nikula; +Cc: Yetunde Adebisi, intel-gfx On 12 January 2016 at 17:18, Jani Nikula <jani.nikula@intel.com> wrote: > On Tue, 12 Jan 2016, Daniel Stone <daniel@fooishbar.org> wrote: >> On 12 January 2016 at 15:59, Yetunde Adebisi <yetundex.adebisi@intel.com> wrote: >>> + memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd)); >> >> gcc should've warned you about this; you're memsetting too small a size. > > Really? I think it's fine. foo.c:11:23: warning: argument to ‘sizeof’ in ‘memset’ call is the same expression as the destination; did you mean to dereference it? [-Wsizeof-pointer-memaccess] memset(bar, 0, sizeof(bar)); ^ Either it should be memset(&intel_dp->edp_dpcd, ...), or it should be sizeof(*intel_dp->edp_dpcd). Unless the intention is genuinely just to clear the size of one pointer and not the entire structure, in which case this is terribly misleading. Cheers, Daniel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] drm/i915: Add Backlight Control using DPCD for eDP connectors (v5) 2016-01-12 17:27 ` Daniel Stone @ 2016-01-12 17:30 ` Jani Nikula 0 siblings, 0 replies; 10+ messages in thread From: Jani Nikula @ 2016-01-12 17:30 UTC (permalink / raw) To: Daniel Stone; +Cc: Yetunde Adebisi, intel-gfx On Tue, 12 Jan 2016, Daniel Stone <daniel@fooishbar.org> wrote: > On 12 January 2016 at 17:18, Jani Nikula <jani.nikula@intel.com> wrote: >> On Tue, 12 Jan 2016, Daniel Stone <daniel@fooishbar.org> wrote: >>> On 12 January 2016 at 15:59, Yetunde Adebisi <yetundex.adebisi@intel.com> wrote: >>>> + memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd)); >>> >>> gcc should've warned you about this; you're memsetting too small a size. >> >> Really? I think it's fine. > > foo.c:11:23: warning: argument to ‘sizeof’ in ‘memset’ call is the > same expression as the destination; did you mean to dereference it? > [-Wsizeof-pointer-memaccess] > memset(bar, 0, sizeof(bar)); > ^ > > Either it should be memset(&intel_dp->edp_dpcd, ...), or it should be > sizeof(*intel_dp->edp_dpcd). Unless the intention is genuinely just to > clear the size of one pointer and not the entire structure, in which > case this is terribly misleading. It's defined as + uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; so sizeof(intel_dp->edp_dpcd) will be EDP_DISPLAY_CTL_CAP_SIZE. BR, Jani. > > Cheers, > Daniel -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* ✗ warning: Fi.CI.BAT 2016-01-12 15:59 [PATCH 0/2] DPCD Backlight Control Yetunde Adebisi 2016-01-12 15:59 ` [PATCH 1/2] drm/dp: Add definition for Display Control DPCD Registers capability size Yetunde Adebisi 2016-01-12 15:59 ` [PATCH 2/2] drm/i915: Add Backlight Control using DPCD for eDP connectors (v5) Yetunde Adebisi @ 2016-01-12 17:49 ` Patchwork 2016-01-21 15:07 ` Adebisi, YetundeX 2 siblings, 1 reply; 10+ messages in thread From: Patchwork @ 2016-01-12 17:49 UTC (permalink / raw) To: Yetunde Adebisi; +Cc: intel-gfx == Summary == Built on 9a47f23e3744929b9b222cb750994723fff0e5ee drm-intel-nightly: 2016y-01m-12d-16h-55m-40s UTC integration manifest Test gem_storedw_loop: Subgroup basic-render: pass -> DMESG-WARN (skl-i5k-2) UNSTABLE pass -> DMESG-WARN (bdw-nuci7) pass -> DMESG-WARN (bdw-ultra) Test kms_flip: Subgroup basic-flip-vs-modeset: dmesg-warn -> PASS (skl-i5k-2) pass -> DMESG-WARN (bdw-ultra) Subgroup basic-plain-flip: pass -> DMESG-WARN (bdw-ultra) Test kms_pipe_crc_basic: Subgroup nonblocking-crc-pipe-a-frame-sequence: pass -> DMESG-WARN (bdw-ultra) Subgroup nonblocking-crc-pipe-b-frame-sequence: pass -> DMESG-WARN (bdw-ultra) Subgroup read-crc-pipe-a: pass -> DMESG-WARN (bdw-ultra) Subgroup read-crc-pipe-a-frame-sequence: pass -> DMESG-WARN (bdw-ultra) Subgroup read-crc-pipe-b: pass -> DMESG-WARN (bdw-ultra) Subgroup read-crc-pipe-b-frame-sequence: pass -> DMESG-WARN (bdw-ultra) Subgroup read-crc-pipe-c: pass -> DMESG-WARN (bdw-ultra) Test pm_rpm: Subgroup basic-pci-d3-state: pass -> DMESG-WARN (bdw-ultra) Subgroup basic-rte: pass -> DMESG-WARN (bdw-ultra) bdw-nuci7 total:138 pass:128 dwarn:1 dfail:0 fail:0 skip:9 bdw-ultra total:138 pass:120 dwarn:12 dfail:0 fail:0 skip:6 bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24 byt-nuc total:141 pass:123 dwarn:3 dfail:0 fail:0 skip:15 hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7 hsw-gt2 total:141 pass:137 dwarn:0 dfail:0 fail:0 skip:4 hsw-xps12 total:138 pass:133 dwarn:1 dfail:0 fail:0 skip:4 ilk-hp8440p total:141 pass:101 dwarn:3 dfail:0 fail:0 skip:37 ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6 skl-i5k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8 skl-i7k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8 snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14 snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13 Results at /archive/results/CI_IGT_test/Patchwork_1154/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: ✗ warning: Fi.CI.BAT 2016-01-12 17:49 ` ✗ warning: Fi.CI.BAT Patchwork @ 2016-01-21 15:07 ` Adebisi, YetundeX 2016-01-22 14:35 ` Jani Nikula 0 siblings, 1 reply; 10+ messages in thread From: Adebisi, YetundeX @ 2016-01-21 15:07 UTC (permalink / raw) To: intel-gfx@lists.freedesktop.org; +Cc: Nikula, Jani Hi, I got this message in reply to this patch (https://patchwork.freedesktop.org/patch/60736/). It looks like most of the warnings are related to 'PWM1 enabled' warnings that happen when the hardware is going into some power management state and BLM_PWM_ENABLE and/or BLM_PCH_PWM_ENABLE are enabled on the bdw-ultra platform. What is the best way to fix this? If my patch is used then the function that disables BLM_PWM_ENABLE and/or BLM_PCH_PWM_ENABLE (lpt_disable_backlight) will not be called. Should I disable this DPCD backlight control featured for BDW or specifically disable these bits in my intel_dp_aux_enable_backlight function? Thank you. Yetunde Dmesg warn output [ 357.655508] ------------[ cut here ]------------ [ 357.655536] WARNING: CPU: 1 PID: 43 at drivers/gpu/drm/i915/intel_display.c:9518 hsw_enable_pc8+0x609/0x730 [i915]() [ 357.655537] CPU PWM1 enabled [ 357.655539] Modules linked in: i915 ax88179_178a i2c_hid x86_pkg_temp_thermal intel_powerclamp coretemp crct10dif_pclmul crc32_pclmul cdc_ncm usbnet mii mei_me mei lpc_ich i2c_designware_platform i2c_designware_core e1000e sdhci_pci ptp pps_core sdhci_acpi sdhci mmc_core [last unloaded: i915] [ 357.655559] CPU: 1 PID: 43 Comm: kworker/1:1 Tainted: G U W 4.4.0-gfxbench+ #1 [ 357.655560] Hardware name: Intel Corporation Broadwell Client platform/Wilson Beach SDS, BIOS BDW-E2R1.86C.0095.R09.1410300006 10/30/2014 [ 357.655565] Workqueue: pm pm_runtime_work [ 357.655567] ffffffffa03e7ce8 ffff8800ab8e3b68 ffffffff813df90c ffff8800ab8e3bb0 [ 357.655570] ffff8800ab8e3ba0 ffffffff810746e1 ffff8802308c0000 ffff880240341898 [ 357.655573] ffff8802403418a8 ffff880240341148 ffff880243bd3470 ffff8800ab8e3c00 [ 357.655576] Call Trace: [ 357.655580] [<ffffffff813df90c>] dump_stack+0x4e/0x82 [ 357.655583] [<ffffffff810746e1>] warn_slowpath_common+0x81/0xc0 [ 357.655585] [<ffffffff81074767>] warn_slowpath_fmt+0x47/0x50 [ 357.655603] [<ffffffffa0378329>] hsw_enable_pc8+0x609/0x730 [i915] [ 357.655610] [<ffffffffa02f4eba>] intel_suspend_complete+0xca/0x6c0 [i915] [ 357.655617] [<ffffffffa02f578b>] intel_runtime_suspend+0xdb/0x2d0 [i915] [ 357.655620] [<ffffffff81425496>] pci_pm_runtime_suspend+0x56/0x190 [ 357.655623] [<ffffffff81425440>] ? pci_pm_runtime_resume+0xa0/0xa0 [ 357.655626] [<ffffffff8152417d>] __rpm_callback+0x2d/0x70 [ 357.655628] [<ffffffff81425440>] ? pci_pm_runtime_resume+0xa0/0xa0 [ 357.655631] [<ffffffff815241df>] rpm_callback+0x1f/0x80 [ 357.655633] [<ffffffff81425440>] ? pci_pm_runtime_resume+0xa0/0xa0 [ 357.655635] [<ffffffff815246c8>] rpm_suspend+0x148/0x780 [ 357.655638] [<ffffffff81526276>] pm_runtime_work+0x76/0xc0 [ 357.655641] [<ffffffff8108f415>] process_one_work+0x1e5/0x620 [ 357.655642] [<ffffffff8108f379>] ? process_one_work+0x149/0x620 [ 357.655645] [<ffffffff8108f899>] worker_thread+0x49/0x450 [ 357.655646] [<ffffffff8108f850>] ? process_one_work+0x620/0x620 [ 357.655648] [<ffffffff8108f850>] ? process_one_work+0x620/0x620 [ 357.655651] [<ffffffff81095eca>] kthread+0xea/0x100 [ 357.655653] [<ffffffff81799e17>] ? _raw_spin_unlock_irq+0x27/0x50 [ 357.655656] [<ffffffff81095de0>] ? kthread_create_on_node+0x1f0/0x1f0 [ 357.655658] [<ffffffff8179aabf>] ret_from_fork+0x3f/0x70 [ 357.655661] [<ffffffff81095de0>] ? kthread_create_on_node+0x1f0/0x1f0 [ 357.655662] ---[ end trace d4f8f254173751a9 ]--- [ 357.655665] ------------[ cut here ]------------ [ 357.655682] WARNING: CPU: 1 PID: 43 at drivers/gpu/drm/i915/intel_display.c:9523 hsw_enable_pc8+0x701/0x730 [i915]() [ 357.655683] PCH PWM1 enabled [ 357.655684] Modules linked in: i915 ax88179_178a i2c_hid x86_pkg_temp_thermal intel_powerclamp coretemp crct10dif_pclmul crc32_pclmul cdc_ncm usbnet mii mei_me mei lpc_ich i2c_designware_platform i2c_designware_core e1000e sdhci_pci ptp pps_core sdhci_acpi sdhci mmc_core [last unloaded: i915] [ 357.655699] CPU: 1 PID: 43 Comm: kworker/1:1 Tainted: G U W 4.4.0-gfxbench+ #1 [ 357.655701] Hardware name: Intel Corporation Broadwell Client platform/Wilson Beach SDS, BIOS BDW-E2R1.86C.0095.R09.1410300006 10/30/2014 [ 357.655704] Workqueue: pm pm_runtime_work [ 357.655705] ffffffffa03e7ce8 ffff8800ab8e3b68 ffffffff813df90c ffff8800ab8e3bb0 [ 357.655708] ffff8800ab8e3ba0 ffffffff810746e1 ffff8802308c0000 ffff880240341898 [ 357.655711] ffff8802403418a8 ffff880240341148 ffff880243bd3470 ffff8800ab8e3c00 [ 357.655714] Call Trace: [ 357.655716] [<ffffffff813df90c>] dump_stack+0x4e/0x82 [ 357.655718] [<ffffffff810746e1>] warn_slowpath_common+0x81/0xc0 [ 357.655720] [<ffffffff81074767>] warn_slowpath_fmt+0x47/0x50 [ 357.655736] [<ffffffffa0378421>] hsw_enable_pc8+0x701/0x730 [i915] [ 357.655743] [<ffffffffa02f4eba>] intel_suspend_complete+0xca/0x6c0 [i915] [ 357.655750] [<ffffffffa02f578b>] intel_runtime_suspend+0xdb/0x2d0 [i915] [ 357.655753] [<ffffffff81425496>] pci_pm_runtime_suspend+0x56/0x190 [ 357.655755] [<ffffffff81425440>] ? pci_pm_runtime_resume+0xa0/0xa0 [ 357.655758] [<ffffffff8152417d>] __rpm_callback+0x2d/0x70 [ 357.655760] [<ffffffff81425440>] ? pci_pm_runtime_resume+0xa0/0xa0 [ 357.655763] [<ffffffff815241df>] rpm_callback+0x1f/0x80 [ 357.655765] [<ffffffff81425440>] ? pci_pm_runtime_resume+0xa0/0xa0 [ 357.655767] [<ffffffff815246c8>] rpm_suspend+0x148/0x780 [ 357.655770] [<ffffffff81526276>] pm_runtime_work+0x76/0xc0 [ 357.655772] [<ffffffff8108f415>] process_one_work+0x1e5/0x620 [ 357.655773] [<ffffffff8108f379>] ? process_one_work+0x149/0x620 [ 357.655775] [<ffffffff8108f899>] worker_thread+0x49/0x450 [ 357.655777] [<ffffffff8108f850>] ? process_one_work+0x620/0x620 [ 357.655779] [<ffffffff8108f850>] ? process_one_work+0x620/0x620 [ 357.655781] [<ffffffff81095eca>] kthread+0xea/0x100 [ 357.655783] [<ffffffff81799e17>] ? _raw_spin_unlock_irq+0x27/0x50 [ 357.655786] [<ffffffff81095de0>] ? kthread_create_on_node+0x1f0/0x1f0 [ 357.655788] [<ffffffff8179aabf>] ret_from_fork+0x3f/0x70 [ 357.655790] [<ffffffff81095de0>] ? kthread_create_on_node+0x1f0/0x1f0 [ 357.655791] ---[ end trace d4f8f254173751aa ]--- > -----Original Message----- > From: Patchwork [mailto:patchwork@annarchy.freedesktop.org] > Sent: Tuesday, January 12, 2016 5:50 PM > To: Adebisi, YetundeX > Cc: intel-gfx@lists.freedesktop.org > Subject: ✗ warning: Fi.CI.BAT > > == Summary == > > Built on 9a47f23e3744929b9b222cb750994723fff0e5ee drm-intel-nightly: > 2016y-01m-12d-16h-55m-40s UTC integration manifest > > Test gem_storedw_loop: > Subgroup basic-render: > pass -> DMESG-WARN (skl-i5k-2) UNSTABLE > pass -> DMESG-WARN (bdw-nuci7) > pass -> DMESG-WARN (bdw-ultra) > Test kms_flip: > Subgroup basic-flip-vs-modeset: > dmesg-warn -> PASS (skl-i5k-2) > pass -> DMESG-WARN (bdw-ultra) > Subgroup basic-plain-flip: > pass -> DMESG-WARN (bdw-ultra) > Test kms_pipe_crc_basic: > Subgroup nonblocking-crc-pipe-a-frame-sequence: > pass -> DMESG-WARN (bdw-ultra) > Subgroup nonblocking-crc-pipe-b-frame-sequence: > pass -> DMESG-WARN (bdw-ultra) > Subgroup read-crc-pipe-a: > pass -> DMESG-WARN (bdw-ultra) > Subgroup read-crc-pipe-a-frame-sequence: > pass -> DMESG-WARN (bdw-ultra) > Subgroup read-crc-pipe-b: > pass -> DMESG-WARN (bdw-ultra) > Subgroup read-crc-pipe-b-frame-sequence: > pass -> DMESG-WARN (bdw-ultra) > Subgroup read-crc-pipe-c: > pass -> DMESG-WARN (bdw-ultra) > Test pm_rpm: > Subgroup basic-pci-d3-state: > pass -> DMESG-WARN (bdw-ultra) > Subgroup basic-rte: > pass -> DMESG-WARN (bdw-ultra) > > bdw-nuci7 total:138 pass:128 dwarn:1 dfail:0 fail:0 skip:9 > bdw-ultra total:138 pass:120 dwarn:12 dfail:0 fail:0 skip:6 > bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24 > byt-nuc total:141 pass:123 dwarn:3 dfail:0 fail:0 skip:15 > hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7 > hsw-gt2 total:141 pass:137 dwarn:0 dfail:0 fail:0 skip:4 > hsw-xps12 total:138 pass:133 dwarn:1 dfail:0 fail:0 skip:4 > ilk-hp8440p total:141 pass:101 dwarn:3 dfail:0 fail:0 skip:37 > ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6 > skl-i5k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8 > skl-i7k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8 > snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14 > snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13 > > Results at /archive/results/CI_IGT_test/Patchwork_1154/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: ✗ warning: Fi.CI.BAT 2016-01-21 15:07 ` Adebisi, YetundeX @ 2016-01-22 14:35 ` Jani Nikula 0 siblings, 0 replies; 10+ messages in thread From: Jani Nikula @ 2016-01-22 14:35 UTC (permalink / raw) To: Adebisi, YetundeX, intel-gfx@lists.freedesktop.org On Thu, 21 Jan 2016, "Adebisi, YetundeX" <yetundex.adebisi@intel.com> wrote: > Hi, > > I got this message in reply to this patch (https://patchwork.freedesktop.org/patch/60736/). > > It looks like most of the warnings are related to 'PWM1 enabled' > warnings that happen when the hardware is going into some power > management state and BLM_PWM_ENABLE and/or BLM_PCH_PWM_ENABLE are > enabled on the bdw-ultra platform. This sounds plausible if the panel actually has DPCD controlled backlight; I was unable to confirm from the CI logs. The BIOS probably enables the PWMs at boot, and then we don't disable. What confuses me is that the backlight works on the machine *without* your patches. IIUC your patch should only enable DPCD backlight control if the DPCD says PWM control is not available. > What is the best way to fix this? If my patch is used then the > function that disables BLM_PWM_ENABLE and/or BLM_PCH_PWM_ENABLE > (lpt_disable_backlight) will not be called. > > Should I disable this DPCD backlight control featured for BDW or > specifically disable these bits in my intel_dp_aux_enable_backlight > function? Whether it makes sense or not, I predict the BIOSes of all machines to blindly enable the PWMs. Including when the panel really doesn't support PWM control. So we need to sanitize these registers. See the comment in lpt_disable_backlight, this is already the case for CPU PWM when only PCH PWM is used. I think the right approach would be to sanitize the state at setup time instead of disable time. The BDW in question is some development platform, I don't think you could buy it. So it's a bit special, but we have it in CI because it has some other features we like to test. Not sure how much conclusions one can really draw from it. BR, Jani. > > Thank you. > > Yetunde > > > Dmesg warn output > > [ 357.655508] ------------[ cut here ]------------ > [ 357.655536] WARNING: CPU: 1 PID: 43 at drivers/gpu/drm/i915/intel_display.c:9518 hsw_enable_pc8+0x609/0x730 [i915]() > [ 357.655537] CPU PWM1 enabled > [ 357.655539] Modules linked in: i915 ax88179_178a i2c_hid x86_pkg_temp_thermal intel_powerclamp coretemp crct10dif_pclmul crc32_pclmul cdc_ncm usbnet mii mei_me mei lpc_ich i2c_designware_platform i2c_designware_core e1000e sdhci_pci ptp pps_core sdhci_acpi sdhci mmc_core [last unloaded: i915] > [ 357.655559] CPU: 1 PID: 43 Comm: kworker/1:1 Tainted: G U W 4.4.0-gfxbench+ #1 > [ 357.655560] Hardware name: Intel Corporation Broadwell Client platform/Wilson Beach SDS, BIOS BDW-E2R1.86C.0095.R09.1410300006 10/30/2014 > [ 357.655565] Workqueue: pm pm_runtime_work > [ 357.655567] ffffffffa03e7ce8 ffff8800ab8e3b68 ffffffff813df90c ffff8800ab8e3bb0 > [ 357.655570] ffff8800ab8e3ba0 ffffffff810746e1 ffff8802308c0000 ffff880240341898 > [ 357.655573] ffff8802403418a8 ffff880240341148 ffff880243bd3470 ffff8800ab8e3c00 > [ 357.655576] Call Trace: > [ 357.655580] [<ffffffff813df90c>] dump_stack+0x4e/0x82 > [ 357.655583] [<ffffffff810746e1>] warn_slowpath_common+0x81/0xc0 > [ 357.655585] [<ffffffff81074767>] warn_slowpath_fmt+0x47/0x50 > [ 357.655603] [<ffffffffa0378329>] hsw_enable_pc8+0x609/0x730 [i915] > [ 357.655610] [<ffffffffa02f4eba>] intel_suspend_complete+0xca/0x6c0 [i915] > [ 357.655617] [<ffffffffa02f578b>] intel_runtime_suspend+0xdb/0x2d0 [i915] > [ 357.655620] [<ffffffff81425496>] pci_pm_runtime_suspend+0x56/0x190 > [ 357.655623] [<ffffffff81425440>] ? pci_pm_runtime_resume+0xa0/0xa0 > [ 357.655626] [<ffffffff8152417d>] __rpm_callback+0x2d/0x70 > [ 357.655628] [<ffffffff81425440>] ? pci_pm_runtime_resume+0xa0/0xa0 > [ 357.655631] [<ffffffff815241df>] rpm_callback+0x1f/0x80 > [ 357.655633] [<ffffffff81425440>] ? pci_pm_runtime_resume+0xa0/0xa0 > [ 357.655635] [<ffffffff815246c8>] rpm_suspend+0x148/0x780 > [ 357.655638] [<ffffffff81526276>] pm_runtime_work+0x76/0xc0 > [ 357.655641] [<ffffffff8108f415>] process_one_work+0x1e5/0x620 > [ 357.655642] [<ffffffff8108f379>] ? process_one_work+0x149/0x620 > [ 357.655645] [<ffffffff8108f899>] worker_thread+0x49/0x450 > [ 357.655646] [<ffffffff8108f850>] ? process_one_work+0x620/0x620 > [ 357.655648] [<ffffffff8108f850>] ? process_one_work+0x620/0x620 > [ 357.655651] [<ffffffff81095eca>] kthread+0xea/0x100 > [ 357.655653] [<ffffffff81799e17>] ? _raw_spin_unlock_irq+0x27/0x50 > [ 357.655656] [<ffffffff81095de0>] ? kthread_create_on_node+0x1f0/0x1f0 > [ 357.655658] [<ffffffff8179aabf>] ret_from_fork+0x3f/0x70 > [ 357.655661] [<ffffffff81095de0>] ? kthread_create_on_node+0x1f0/0x1f0 > [ 357.655662] ---[ end trace d4f8f254173751a9 ]--- > [ 357.655665] ------------[ cut here ]------------ > [ 357.655682] WARNING: CPU: 1 PID: 43 at drivers/gpu/drm/i915/intel_display.c:9523 hsw_enable_pc8+0x701/0x730 [i915]() > [ 357.655683] PCH PWM1 enabled > [ 357.655684] Modules linked in: i915 ax88179_178a i2c_hid x86_pkg_temp_thermal intel_powerclamp coretemp crct10dif_pclmul crc32_pclmul cdc_ncm usbnet mii mei_me mei lpc_ich i2c_designware_platform i2c_designware_core e1000e sdhci_pci ptp pps_core sdhci_acpi sdhci mmc_core [last unloaded: i915] > [ 357.655699] CPU: 1 PID: 43 Comm: kworker/1:1 Tainted: G U W 4.4.0-gfxbench+ #1 > [ 357.655701] Hardware name: Intel Corporation Broadwell Client platform/Wilson Beach SDS, BIOS BDW-E2R1.86C.0095.R09.1410300006 10/30/2014 > [ 357.655704] Workqueue: pm pm_runtime_work > [ 357.655705] ffffffffa03e7ce8 ffff8800ab8e3b68 ffffffff813df90c ffff8800ab8e3bb0 > [ 357.655708] ffff8800ab8e3ba0 ffffffff810746e1 ffff8802308c0000 ffff880240341898 > [ 357.655711] ffff8802403418a8 ffff880240341148 ffff880243bd3470 ffff8800ab8e3c00 > [ 357.655714] Call Trace: > [ 357.655716] [<ffffffff813df90c>] dump_stack+0x4e/0x82 > [ 357.655718] [<ffffffff810746e1>] warn_slowpath_common+0x81/0xc0 > [ 357.655720] [<ffffffff81074767>] warn_slowpath_fmt+0x47/0x50 > [ 357.655736] [<ffffffffa0378421>] hsw_enable_pc8+0x701/0x730 [i915] > [ 357.655743] [<ffffffffa02f4eba>] intel_suspend_complete+0xca/0x6c0 [i915] > [ 357.655750] [<ffffffffa02f578b>] intel_runtime_suspend+0xdb/0x2d0 [i915] > [ 357.655753] [<ffffffff81425496>] pci_pm_runtime_suspend+0x56/0x190 > [ 357.655755] [<ffffffff81425440>] ? pci_pm_runtime_resume+0xa0/0xa0 > [ 357.655758] [<ffffffff8152417d>] __rpm_callback+0x2d/0x70 > [ 357.655760] [<ffffffff81425440>] ? pci_pm_runtime_resume+0xa0/0xa0 > [ 357.655763] [<ffffffff815241df>] rpm_callback+0x1f/0x80 > [ 357.655765] [<ffffffff81425440>] ? pci_pm_runtime_resume+0xa0/0xa0 > [ 357.655767] [<ffffffff815246c8>] rpm_suspend+0x148/0x780 > [ 357.655770] [<ffffffff81526276>] pm_runtime_work+0x76/0xc0 > [ 357.655772] [<ffffffff8108f415>] process_one_work+0x1e5/0x620 > [ 357.655773] [<ffffffff8108f379>] ? process_one_work+0x149/0x620 > [ 357.655775] [<ffffffff8108f899>] worker_thread+0x49/0x450 > [ 357.655777] [<ffffffff8108f850>] ? process_one_work+0x620/0x620 > [ 357.655779] [<ffffffff8108f850>] ? process_one_work+0x620/0x620 > [ 357.655781] [<ffffffff81095eca>] kthread+0xea/0x100 > [ 357.655783] [<ffffffff81799e17>] ? _raw_spin_unlock_irq+0x27/0x50 > [ 357.655786] [<ffffffff81095de0>] ? kthread_create_on_node+0x1f0/0x1f0 > [ 357.655788] [<ffffffff8179aabf>] ret_from_fork+0x3f/0x70 > [ 357.655790] [<ffffffff81095de0>] ? kthread_create_on_node+0x1f0/0x1f0 > [ 357.655791] ---[ end trace d4f8f254173751aa ]--- > > >> -----Original Message----- >> From: Patchwork [mailto:patchwork@annarchy.freedesktop.org] >> Sent: Tuesday, January 12, 2016 5:50 PM >> To: Adebisi, YetundeX >> Cc: intel-gfx@lists.freedesktop.org >> Subject: ✗ warning: Fi.CI.BAT >> >> == Summary == >> >> Built on 9a47f23e3744929b9b222cb750994723fff0e5ee drm-intel-nightly: >> 2016y-01m-12d-16h-55m-40s UTC integration manifest >> >> Test gem_storedw_loop: >> Subgroup basic-render: >> pass -> DMESG-WARN (skl-i5k-2) UNSTABLE >> pass -> DMESG-WARN (bdw-nuci7) >> pass -> DMESG-WARN (bdw-ultra) >> Test kms_flip: >> Subgroup basic-flip-vs-modeset: >> dmesg-warn -> PASS (skl-i5k-2) >> pass -> DMESG-WARN (bdw-ultra) >> Subgroup basic-plain-flip: >> pass -> DMESG-WARN (bdw-ultra) >> Test kms_pipe_crc_basic: >> Subgroup nonblocking-crc-pipe-a-frame-sequence: >> pass -> DMESG-WARN (bdw-ultra) >> Subgroup nonblocking-crc-pipe-b-frame-sequence: >> pass -> DMESG-WARN (bdw-ultra) >> Subgroup read-crc-pipe-a: >> pass -> DMESG-WARN (bdw-ultra) >> Subgroup read-crc-pipe-a-frame-sequence: >> pass -> DMESG-WARN (bdw-ultra) >> Subgroup read-crc-pipe-b: >> pass -> DMESG-WARN (bdw-ultra) >> Subgroup read-crc-pipe-b-frame-sequence: >> pass -> DMESG-WARN (bdw-ultra) >> Subgroup read-crc-pipe-c: >> pass -> DMESG-WARN (bdw-ultra) >> Test pm_rpm: >> Subgroup basic-pci-d3-state: >> pass -> DMESG-WARN (bdw-ultra) >> Subgroup basic-rte: >> pass -> DMESG-WARN (bdw-ultra) >> >> bdw-nuci7 total:138 pass:128 dwarn:1 dfail:0 fail:0 skip:9 >> bdw-ultra total:138 pass:120 dwarn:12 dfail:0 fail:0 skip:6 >> bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24 >> byt-nuc total:141 pass:123 dwarn:3 dfail:0 fail:0 skip:15 >> hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7 >> hsw-gt2 total:141 pass:137 dwarn:0 dfail:0 fail:0 skip:4 >> hsw-xps12 total:138 pass:133 dwarn:1 dfail:0 fail:0 skip:4 >> ilk-hp8440p total:141 pass:101 dwarn:3 dfail:0 fail:0 skip:37 >> ivb-t430s total:135 pass:122 dwarn:3 dfail:4 fail:0 skip:6 >> skl-i5k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8 >> skl-i7k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8 >> snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14 >> snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13 >> >> Results at /archive/results/CI_IGT_test/Patchwork_1154/ > -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2016-01-22 14:35 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-01-12 15:59 [PATCH 0/2] DPCD Backlight Control Yetunde Adebisi 2016-01-12 15:59 ` [PATCH 1/2] drm/dp: Add definition for Display Control DPCD Registers capability size Yetunde Adebisi 2016-01-12 15:59 ` [PATCH 2/2] drm/i915: Add Backlight Control using DPCD for eDP connectors (v5) Yetunde Adebisi 2016-01-12 16:16 ` Daniel Stone 2016-01-12 17:18 ` Jani Nikula 2016-01-12 17:27 ` Daniel Stone 2016-01-12 17:30 ` Jani Nikula 2016-01-12 17:49 ` ✗ warning: Fi.CI.BAT Patchwork 2016-01-21 15:07 ` Adebisi, YetundeX 2016-01-22 14:35 ` Jani Nikula
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