From: Jani Nikula <jani.nikula@linux.intel.com>
To: Kevin Strasser <kevin.strasser@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: respect previous reg values on primary plane disable
Date: Wed, 14 Oct 2015 10:58:29 +0300 [thread overview]
Message-ID: <8761293mqi.fsf@intel.com> (raw)
In-Reply-To: <1444771481-5625-1-git-send-email-kevin.strasser@linux.intel.com>
On Wed, 14 Oct 2015, Kevin Strasser <kevin.strasser@linux.intel.com> wrote:
> On HSW the crc differs between black and disabled primary planes, causing an
> assert to fail in the kms_universal_plane test. It seems that things like gamma
> correction are causing the black primary plane case to result in a brighter
> color than the disabled primary plane case.
>
> Only toggle the enable bit instead of clearing the control register, making the
> disable path more similar to that of the sprite plane.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89331
> Testcase: igt/kms_universal_plane
> Signed-off-by: Kevin Strasser <kevin.strasser@linux.intel.com>
Cc: stable@vger.kernel.org # v3.18
Fixes: fdd508a64192 ("drm/i915: Call .update_primary_plane in intel_{enable, disable}_primary_hw_plane()")
How about i9xx_update_primary_plane, modified in the same commit above,
and skylake_update_primary_plane, added in
commit 6156a45602f990cdb140025a3ced96e6695980cf
Author: Chandra Konduru <chandra.konduru@intel.com>
Date: Mon Apr 27 13:48:39 2015 -0700
drm/i915: skylake primary plane scaling using shared scalers
BR,
Jani.
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index cddb0c6..b6164d8e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2829,7 +2829,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> int pixel_size;
>
> if (!visible || !fb) {
> - I915_WRITE(reg, 0);
> + I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
> I915_WRITE(DSPSURF(plane), 0);
> POSTING_READ(reg);
> return;
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
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next prev parent reply other threads:[~2015-10-14 7:55 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-13 21:24 [PATCH] drm/i915: respect previous reg values on primary plane disable Kevin Strasser
2015-10-13 23:02 ` Jesse Barnes
2015-10-14 7:58 ` Jani Nikula [this message]
2015-10-14 7:59 ` Jani Nikula
2015-10-14 18:44 ` Kevin Strasser
2015-10-14 19:01 ` Daniel Vetter
2015-10-14 12:07 ` Ville Syrjälä
2015-10-14 12:12 ` Chris Wilson
2015-10-14 12:22 ` Ville Syrjälä
2015-10-14 18:59 ` Kevin Strasser
2015-10-14 19:48 ` Ville Syrjälä
2015-10-14 20:33 ` Kevin Strasser
2015-10-15 8:20 ` Ville Syrjälä
2015-10-15 23:00 ` Kevin Strasser
2015-10-16 0:14 ` Ville Syrjälä
2015-10-14 13:04 ` Daniel Vetter
2015-10-14 13:09 ` Ville Syrjälä
2015-10-14 22:51 ` [PATCH v2] drm/i915/hsw: keep gamma and CSC enabled for " Kevin Strasser
2015-10-15 12:31 ` Daniel Vetter
2015-10-15 12:41 ` Ville Syrjälä
2015-10-16 22:53 ` Bob Paauwe
2015-10-19 10:15 ` Daniel Vetter
2015-10-19 17:13 ` Kevin Strasser
2015-10-20 15:48 ` Bob Paauwe
2015-10-20 16:13 ` Ville Syrjälä
2015-10-20 17:00 ` Bob Paauwe
2015-10-21 6:31 ` Daniel Vetter
2015-10-20 15:49 ` Bob Paauwe
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