From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [Intel-gfx] [PATCH] drm/i915: Flush pipecontrol post-sync writes Date: Tue, 13 Oct 2015 15:45:58 +0300 Message-ID: <87612b543d.fsf@intel.com> References: <1440169721-25861-1-git-send-email-chris@chris-wilson.co.uk> <20150826091634.GQ20434@phenom.ffwll.local> <20150826092924.GD17184@nuc-i3427.alporthouse.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <20150826092924.GD17184@nuc-i3427.alporthouse.com> Sender: stable-owner@vger.kernel.org To: Chris Wilson , Daniel Vetter Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org On Wed, 26 Aug 2015, Chris Wilson wrote: > On Wed, Aug 26, 2015 at 11:16:34AM +0200, Daniel Vetter wrote: >> On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote: >> > In order to flush the results from in-batch pipecontrol writes (used for >> > example in glQuery) before declaring the batch complete (and so declaring >> > the query results coherent), we need to set the FlushEnable bit in our >> > flushing pipecontrol. The FlushEnable bit "waits until all previous >> > writes of immediate data from post-sync circles are complete before >> > executing the next command". >> > >> > Signed-off-by: Chris Wilson >> > Cc: stable@vger.kernel.org >> >> Do we have an igt/piglit failing somewhere (igt kinda preferred) or a >> bugzilla or why is this cc: stable? > > I get GPU hangs on byt without flushing these writes (running ue4). > piglit has examples where the flush is required for correct rendering. Daniel, does this satisfy your question? We've had an r-b from Ville for a long time. BR, Jani. > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center