Re: [PATCH v4] drm/i915/chv: Implement WaDisableShadowRegForCpd

From: Jani Nikula <jani.nikula@linux.intel.com>
To: deepak.s@linux.intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v4] drm/i915/chv: Implement	WaDisableShadowRegForCpd
Date: Tue, 28 Apr 2015 17:41:47 +0300	[thread overview]
Message-ID: <87618gb9hw.fsf@intel.com> (raw)
In-Reply-To: <1429154488-5044-1-git-send-email-deepak.s@linux.intel.com>

On Thu, 16 Apr 2015, deepak.s@linux.intel.com wrote:
> From: Deepak S <deepak.s@linux.intel.com>
>
> This WA is avoid problem between shadow vs wake FIFO unload
> problem during CPD/RC6 transactions on CHV.
>
> v2: Define individual bits GTFIFOCTL (Ville)
>
> v3: move WA to uncore_early_sanitize (ville)
>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pushed to drm-intel-fixes, thanks for the patch and review.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/i915_reg.h     | 2 ++
>  drivers/gpu/drm/i915/intel_uncore.c | 8 ++++++++
>  2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9c97842..a642a58 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
>  #define  GTFIFOCTL				0x120008
>  #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
>  #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
> +#define	   GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL	(1 << 12)
> +#define	   GT_FIFO_CTL_RC6_POLICY_STALL	(1 << 11)
>  
>  #define  HSW_IDICR				0x9008
>  #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index d96d15f..d7cfd0c 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -360,6 +360,14 @@ static void __intel_uncore_early_sanitize(struct drm_device *dev,
>  		__raw_i915_write32(dev_priv, GTFIFODBG,
>  				   __raw_i915_read32(dev_priv, GTFIFODBG));
>  
> +	/* WaDisableShadowRegForCpd:chv */
> +	if (IS_CHERRYVIEW(dev)) {
> +		__raw_i915_write32(dev_priv, GTFIFOCTL,
> +				__raw_i915_read32(dev_priv, GTFIFOCTL) |
> +						GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
> +						GT_FIFO_CTL_RC6_POLICY_STALL);
> +	}
> +
>  	intel_uncore_forcewake_reset(dev, restore_forcewake);
>  }
>  
> -- 
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx