Re: [PATCH] drm/i915: DP link training optimization

[Jani Nikula <jani.nikula@linux.intel.com>]

On Wed, 11 Feb 2015, Mika Kahola <mika.kahola@intel.com> wrote:
> Reuse existing DP link training values i.e. voltage swing
> and pre-emphasis levels, if DP port that we are connected
> to hasn't changed. If we are unable to re-initialize DP
> link, the fallback is to reset the link training values,
> and restart.

Sorry, I failed to remind you to sign your work:

Signed-off-by: Mika Kahola <mika.kahola@intel.com>

see Documentation/SubmittingPatches for details.

BR,
Jani.


> 	modified:   intel_dp.c
> 	modified:   intel_drv.h
> ---
>  drivers/gpu/drm/i915/intel_dp.c  | 75 +++++++++++++++++++++++++++++++++++-----
>  drivers/gpu/drm/i915/intel_drv.h |  2 ++
>  2 files changed, 69 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 868a07b..c40d64a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3286,6 +3286,25 @@ intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
>  }
>  
>  static bool
> +intel_dp_reuse_link_train(struct intel_dp *intel_dp, uint32_t *DP,
> +			  uint8_t dp_train_pat)
> +{
> +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_device *dev = intel_dig_port->base.base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	intel_dp_set_signal_levels(intel_dp, DP);
> +
> +	I915_WRITE(intel_dp->output_reg, *DP);
> +	POSTING_READ(intel_dp->output_reg);
> +
> +	drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
> +			  intel_dp->train_set, intel_dp->lane_count);
> +
> +	return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
> +}
> +
> +static bool
>  intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
>  			   const uint8_t link_status[DP_LINK_STATUS_SIZE])
>  {
> @@ -3348,6 +3367,8 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>  	int voltage_tries, loop_tries;
>  	uint32_t DP = intel_dp->DP;
>  	uint8_t link_config[2];
> +	uint8_t link_status[DP_LINK_STATUS_SIZE];
> +	bool reuse_train_set = false;
>  
>  	if (HAS_DDI(dev))
>  		intel_ddi_prepare_link_retrain(encoder);
> @@ -3365,20 +3386,36 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>  
>  	DP |= DP_PORT_EN;
>  
> -	/* clock recovery */
> -	if (!intel_dp_reset_link_train(intel_dp, &DP,
> -				       DP_TRAINING_PATTERN_1 |
> -				       DP_LINK_SCRAMBLING_DISABLE)) {
> -		DRM_ERROR("failed to enable link training\n");
> -		return;
> +	/*
> +	 * check if DP connector has changed. Reset voltage swing and
> +	 * pre-emphasis levels if that's the case.
> +	 */
> +	if (intel_dp->connector_changed) {
> +		/* reset link training values */
> +		DRM_DEBUG_KMS("resetting link train set\n");
> +		if (!intel_dp_reset_link_train(intel_dp, &DP,
> +					       DP_TRAINING_PATTERN_1 |
> +					       DP_LINK_SCRAMBLING_DISABLE)) {
> +			DRM_ERROR("failed to enable link training\n");
> +			return;
> +		}
> +		reuse_train_set = false;
> +	}
> +	else {
> +		DRM_DEBUG_KMS("reusing current link train set\n");
> +		if (!intel_dp_reuse_link_train(intel_dp, &DP,
> +					       DP_TRAINING_PATTERN_1 |
> +					       DP_LINK_SCRAMBLING_DISABLE)) {
> +			DRM_DEBUG_KMS("unable to set known link training values\n");
> +			return;
> +		}
> +		reuse_train_set = true;
>  	}
>  
>  	voltage = 0xff;
>  	voltage_tries = 0;
>  	loop_tries = 0;
>  	for (;;) {
> -		uint8_t link_status[DP_LINK_STATUS_SIZE];
> -
>  		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
>  		if (!intel_dp_get_link_status(intel_dp, link_status)) {
>  			DRM_ERROR("failed to get link status\n");
> @@ -3389,6 +3426,20 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>  			DRM_DEBUG_KMS("clock recovery OK\n");
>  			break;
>  		}
> +		/*
> +		 * if we used previously trained voltage and pre-emphasis values
> +		 * and we don't get clock recovery, reset link training values
> +		 */
> +		if (reuse_train_set) {
> +			DRM_DEBUG_KMS("clock recovery not ok, resetting DP train set\n");
> +			if (!intel_dp_reset_link_train(intel_dp, &DP,
> +						       DP_TRAINING_PATTERN_1 |
> +						       DP_LINK_SCRAMBLING_DISABLE)) {
> +				DRM_ERROR("failed to enable link training\n");
> +				return;
> +			}
> +			reuse_train_set = false;
> +		}
>  
>  		/* Check to see if we've tried the max voltage */
>  		for (i = 0; i < intel_dp->lane_count; i++)
> @@ -4076,6 +4127,14 @@ intel_dp_detect(struct drm_connector *connector, bool force)
>  		      connector->base.id, connector->name);
>  	intel_dp_unset_edid(intel_dp);
>  
> +	if (connector->base.id != intel_dp->connector_id) {
> +		intel_dp->connector_id = connector->base.id;
> +		DRM_DEBUG_KMS("DP connector changed\n");
> +		intel_dp->connector_changed = true;
> +	}
> +	else
> +		intel_dp->connector_changed = false;
> +
>  	if (intel_dp->is_mst) {
>  		/* MST devices are disconnected from a monitor POV */
>  		if (intel_encoder->type != INTEL_OUTPUT_EDP)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 1de8e20..2877226 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -648,6 +648,8 @@ struct intel_dp {
>  				     bool has_aux_irq,
>  				     int send_bytes,
>  				     uint32_t aux_clock_divider);
> +	uint32_t connector_id;
> +	bool connector_changed;
>  };
>  
>  struct intel_digital_port {
> -- 
> 1.9.1
>
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-- 
Jani Nikula, Intel Open Source Technology Center
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