From: Jani Nikula <jani.nikula@linux.intel.com>
To: Gaurav K Singh <gaurav.k.singh@intel.com>,
intel-gfx <intel-gfx@lists.freedesktop.org>
Cc: Shobhit Kumar <shobhit.kumar@intel.com>
Subject: Re: [PATCH 6/9] drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link
Date: Mon, 01 Dec 2014 15:27:51 +0200 [thread overview]
Message-ID: <8761dvbiug.fsf@intel.com> (raw)
In-Reply-To: <1417254967-27384-7-git-send-email-gaurav.k.singh@intel.com>
On Sat, 29 Nov 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be enabled.
>
> v2: Address review comments by Jani
> - Added wait time for PLL to be locked.
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_pll.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index fa7a6ca..93d8e9a 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -243,6 +243,9 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
>
> dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
>
> + if (intel_dsi->dual_link)
> + dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
> +
> DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
> dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);
>
> @@ -269,12 +272,12 @@ void vlv_enable_dsi_pll(struct intel_encoder *encoder)
> tmp |= DSI_PLL_VCO_EN;
> vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
>
> - mutex_unlock(&dev_priv->dpio_lock);
> -
> - if (wait_for(I915_READ(PIPECONF(PIPE_A)) & PIPECONF_DSI_PLL_LOCKED, 20)) {
> + if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
> + DSI_PLL_LOCK, 20)) {
> DRM_ERROR("DSI PLL lock failed\n");
> return;
> }
> + mutex_unlock(&dev_priv->dpio_lock);
This hunk seems to be an unrelated change, I think it should be a
separate patch.
BR,
Jani.
>
> DRM_DEBUG_KMS("DSI PLL locked\n");
> }
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2014-12-01 13:28 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-29 9:55 [PATCH 0/9] BYT DSI Dual Link Support Gaurav K Singh
2014-11-29 9:55 ` [PATCH 1/9] drm/i915: New functions added for enabling & disabling MIPI Port Ctrl reg Gaurav K Singh
2014-11-29 9:56 ` [PATCH 2/9] drm/i915: Added port as parameter to the functions which does read/write of DSI Controller Gaurav K Singh
2014-12-01 13:40 ` Jani Nikula
2014-11-29 9:56 ` [PATCH 3/9] drm/i915: Add support for port enable/disable for dual link configuration Gaurav K Singh
2014-12-01 13:23 ` Jani Nikula
2014-12-01 14:11 ` Jani Nikula
2014-12-01 18:05 ` Singh, Gaurav K
2014-12-01 19:21 ` Jani Nikula
2014-11-29 9:56 ` [PATCH 4/9] drm/i915: Pixel Clock changes for DSI dual link Gaurav K Singh
2014-11-29 9:56 ` [PATCH 5/9] drm/i915: Dual link needs Shutdown and Turn on packet for both ports Gaurav K Singh
2014-11-29 9:56 ` [PATCH 6/9] drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link Gaurav K Singh
2014-12-01 13:27 ` Jani Nikula [this message]
2014-12-01 17:37 ` Singh, Gaurav K
2014-11-29 9:56 ` [PATCH 7/9] drm/i915: MIPI Timings related changes for " Gaurav K Singh
2014-11-29 9:56 ` [PATCH 8/9] drm/i915: Update the DSI disable path to support dual link panel disabling Gaurav K Singh
2014-11-29 9:56 ` [PATCH 9/9] drm/i915: Update the DSI enable path to support dual link panel enabling Gaurav K Singh
2014-12-03 17:34 ` shuang.he
2014-12-01 13:47 ` [PATCH 0/9] BYT DSI Dual Link Support Jani Nikula
2014-12-04 5:37 ` Singh, Gaurav K
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