Re: [PATCH] drm/i915: vlv: reserve GT power context early

[Jani Nikula <jani.nikula@linux.intel.com>]

On Tue, 11 Feb 2014, Imre Deak <imre.deak@intel.com> wrote:
> We reserve the space for the power context in stolen memory at a fixed
> address from a delayed work. This races with the subsequent driver
> init/resume code which could allocate something at that address, so the
> reservation for the power context fails. Reserve the space up-front, so
> this can't happen. This also adds a missing struct_mutex lock around the
> stolen allocation, which wasn't taken in the delayed work path.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Pushed to -fixes with Jesse's IRC R-b. Thanks for the patch and review.

BR,
Jani.


> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 87999d3..fd4c983 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3554,6 +3554,8 @@ static void valleyview_setup_pctx(struct drm_device *dev)
>  	u32 pcbr;
>  	int pctx_size = 24*1024;
>  
> +	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
> +
>  	pcbr = I915_READ(VLV_PCBR);
>  	if (pcbr) {
>  		/* BIOS set it up already, grab the pre-alloc'd space */
> @@ -3603,8 +3605,6 @@ static void valleyview_enable_rps(struct drm_device *dev)
>  		I915_WRITE(GTFIFODBG, gtfifodbg);
>  	}
>  
> -	valleyview_setup_pctx(dev);
> -
>  	/* If VLV, Forcewake all wells, else re-direct to regular path */
>  	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
>  
> @@ -4471,6 +4471,8 @@ void intel_enable_gt_powersave(struct drm_device *dev)
>  		ironlake_enable_rc6(dev);
>  		intel_init_emon(dev);
>  	} else if (IS_GEN6(dev) || IS_GEN7(dev)) {
> +		if (IS_VALLEYVIEW(dev))
> +			valleyview_setup_pctx(dev);
>  		/*
>  		 * PCU communication is slow and this doesn't need to be
>  		 * done at any specific time, so do this out of our fast path
> -- 
> 1.8.4
>
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-- 
Jani Nikula, Intel Open Source Technology Center