* [PATCH 01/16] drm/i915: Nuke _MMIO_PLANE_GAMC()
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
@ 2024-05-10 15:23 ` Ville Syrjala
2024-05-13 9:50 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 02/16] drm/i915: Extract skl_universal_plane_regs.h Ville Syrjala
` (20 subsequent siblings)
21 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2024-05-10 15:23 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
_MMIO_PLANE_GAMC() is some leftover macro that is never used.
Get rid of it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 256d73c25701..0f4a2d542d81 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5151,8 +5151,6 @@ enum skl_power_gate {
#define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
#define WM_DBG_DISALLOW_SPRITE (1 << 2)
-#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
-
/* Plane CSC Registers */
#define _PLANE_CSC_RY_GY_1_A 0x70210
#define _PLANE_CSC_RY_GY_2_A 0x70310
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 01/16] drm/i915: Nuke _MMIO_PLANE_GAMC()
2024-05-10 15:23 ` [PATCH 01/16] drm/i915: Nuke _MMIO_PLANE_GAMC() Ville Syrjala
@ 2024-05-13 9:50 ` Jani Nikula
0 siblings, 0 replies; 48+ messages in thread
From: Jani Nikula @ 2024-05-13 9:50 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> _MMIO_PLANE_GAMC() is some leftover macro that is never used.
> Get rid of it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 256d73c25701..0f4a2d542d81 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5151,8 +5151,6 @@ enum skl_power_gate {
> #define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
> #define WM_DBG_DISALLOW_SPRITE (1 << 2)
>
> -#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
> -
> /* Plane CSC Registers */
> #define _PLANE_CSC_RY_GY_1_A 0x70210
> #define _PLANE_CSC_RY_GY_2_A 0x70310
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 02/16] drm/i915: Extract skl_universal_plane_regs.h
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
2024-05-10 15:23 ` [PATCH 01/16] drm/i915: Nuke _MMIO_PLANE_GAMC() Ville Syrjala
@ 2024-05-10 15:23 ` Ville Syrjala
2024-05-13 10:07 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 03/16] drm/i915: Extract intel_cursor_regs.h Ville Syrjala
` (19 subsequent siblings)
21 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2024-05-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Zhenyu Wang, Zhi Wang
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move most of the SKL+ universal plane register definitions
into their own file. Declutters i915_reg.h a bit more.
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
CC: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../gpu/drm/i915/display/intel_dpt_common.c | 1 +
.../drm/i915/display/skl_universal_plane.c | 1 +
.../i915/display/skl_universal_plane_regs.h | 405 ++++++++++++++++++
drivers/gpu/drm/i915/display/skl_watermark.c | 1 +
drivers/gpu/drm/i915/gvt/dmabuf.c | 3 +-
drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 +
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 395 -----------------
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
10 files changed, 414 insertions(+), 396 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ef986b508431..a2c331c696fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -119,6 +119,7 @@
#include "intel_wm.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
+#include "skl_universal_plane_regs.h"
#include "skl_watermark.h"
#include "vlv_dpio_phy_regs.h"
#include "vlv_dsi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dpt_common.c b/drivers/gpu/drm/i915/display/intel_dpt_common.c
index cdba47165c04..573f72068899 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt_common.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt_common.c
@@ -7,6 +7,7 @@
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dpt_common.h"
+#include "skl_universal_plane_regs.h"
void intel_dpt_configure(struct intel_crtc *crtc)
{
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 0a8e781a3648..ab560820bb23 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -21,6 +21,7 @@
#include "intel_psr_regs.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
+#include "skl_universal_plane_regs.h"
#include "skl_watermark.h"
#include "pxp/intel_pxp.h"
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
new file mode 100644
index 000000000000..7e34470beb74
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -0,0 +1,405 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __SKL_UNIVERSAL_PLANE_REGS_H__
+#define __SKL_UNIVERSAL_PLANE_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _PLANE_CTL_1_A 0x70180
+#define _PLANE_CTL_2_A 0x70280
+#define _PLANE_CTL_3_A 0x70380
+#define PLANE_CTL_ENABLE REG_BIT(31)
+#define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
+#define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
+#define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
+#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
+/*
+ * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
+ * expanded to include bit 23 as well. However, the shift-24 based values
+ * correctly map to the same formats in ICL, as long as bit 23 is set to 0
+ */
+#define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */
+#define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */
+#define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
+#define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1)
+#define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2)
+#define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3)
+#define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4)
+#define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5)
+#define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6)
+#define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7)
+#define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8)
+#define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12)
+#define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14)
+#define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1)
+#define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3)
+#define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5)
+#define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7)
+#define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9)
+#define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11)
+#define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
+#define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21)
+#define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1)
+#define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2)
+#define PLANE_CTL_ORDER_RGBX REG_BIT(20)
+#define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19)
+#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18)
+#define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16)
+#define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)
+#define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1)
+#define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2)
+#define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3)
+#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15)
+#define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14)
+#define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
+#define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
+#define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10)
+#define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0)
+#define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1)
+#define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4)
+#define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
+#define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
+#define PLANE_CTL_ASYNC_FLIP REG_BIT(9)
+#define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8)
+#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
+#define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
+#define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0)
+#define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2)
+#define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3)
+#define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0)
+#define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0)
+#define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
+#define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
+#define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
+#define _PLANE_STRIDE_1_A 0x70188
+#define _PLANE_STRIDE_2_A 0x70288
+#define _PLANE_STRIDE_3_A 0x70388
+#define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
+#define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
+#define _PLANE_POS_1_A 0x7018c
+#define _PLANE_POS_2_A 0x7028c
+#define _PLANE_POS_3_A 0x7038c
+#define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
+#define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
+#define PLANE_POS_X_MASK REG_GENMASK(15, 0)
+#define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
+#define _PLANE_SIZE_1_A 0x70190
+#define _PLANE_SIZE_2_A 0x70290
+#define _PLANE_SIZE_3_A 0x70390
+#define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
+#define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
+#define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
+#define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
+#define _PLANE_SURF_1_A 0x7019c
+#define _PLANE_SURF_2_A 0x7029c
+#define _PLANE_SURF_3_A 0x7039c
+#define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
+#define PLANE_SURF_DECRYPT REG_BIT(2)
+#define _PLANE_OFFSET_1_A 0x701a4
+#define _PLANE_OFFSET_2_A 0x702a4
+#define _PLANE_OFFSET_3_A 0x703a4
+#define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
+#define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
+#define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
+#define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))
+#define _PLANE_KEYVAL_1_A 0x70194
+#define _PLANE_KEYVAL_2_A 0x70294
+#define _PLANE_KEYMSK_1_A 0x70198
+#define _PLANE_KEYMSK_2_A 0x70298
+#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31)
+#define _PLANE_KEYMAX_1_A 0x701a0
+#define _PLANE_KEYMAX_2_A 0x702a0
+#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24)
+#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a))
+#define _PLANE_SURFLIVE_1_A 0x701ac
+#define _PLANE_SURFLIVE_2_A 0x702ac
+#define _PLANE_CC_VAL_1_A 0x701b4
+#define _PLANE_CC_VAL_2_A 0x702b4
+#define _PLANE_AUX_DIST_1_A 0x701c0
+#define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
+#define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
+#define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
+#define _PLANE_AUX_DIST_2_A 0x702c0
+#define _PLANE_AUX_OFFSET_1_A 0x701c4
+#define _PLANE_AUX_OFFSET_2_A 0x702c4
+#define _PLANE_CUS_CTL_1_A 0x701c8
+#define _PLANE_CUS_CTL_2_A 0x702c8
+#define PLANE_CUS_ENABLE REG_BIT(31)
+#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
+#define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
+#define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
+#define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
+#define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
+#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
+#define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16)
+#define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
+#define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
+#define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
+#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
+#define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12)
+#define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
+#define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
+#define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
+#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
+#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
+#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
+#define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
+#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
+#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
+#define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
+#define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
+#define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17)
+#define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
+#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)
+#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2)
+#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3)
+#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4)
+#define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13)
+#define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4)
+#define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
+#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
+#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
+#define _PLANE_CHICKEN_1_A 0x7026C /* tgl+ */
+#define _PLANE_CHICKEN_2_A 0x7036C /* tgl+ */
+#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
+#define _PLANE_BUF_CFG_1_A 0x7027c
+#define _PLANE_BUF_CFG_2_A 0x7037c
+/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
+#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
+#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
+#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
+#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
+#define _PLANE_NV12_BUF_CFG_1_A 0x70278
+#define _PLANE_NV12_BUF_CFG_2_A 0x70378
+
+#define _PLANE_CC_VAL_1_B 0x711b4
+#define _PLANE_CC_VAL_2_B 0x712b4
+#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
+#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
+#define PLANE_CC_VAL(pipe, plane, dw) \
+ _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
+
+/* Input CSC Register Definitions */
+#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
+#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
+
+#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
+#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
+
+#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
+ _PLANE_INPUT_CSC_RY_GY_1_B)
+#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
+ _PLANE_INPUT_CSC_RY_GY_2_B)
+
+#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
+#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
+#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
+ _PLANE_INPUT_CSC_PREOFF_HI_1_B)
+#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
+ _PLANE_INPUT_CSC_PREOFF_HI_2_B)
+#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
+ _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
+ _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
+ _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
+#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
+
+#define _PLANE_CTL_1_B 0x71180
+#define _PLANE_CTL_2_B 0x71280
+#define _PLANE_CTL_3_B 0x71380
+#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
+#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
+#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
+#define PLANE_CTL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
+
+#define _PLANE_STRIDE_1_B 0x71188
+#define _PLANE_STRIDE_2_B 0x71288
+#define _PLANE_STRIDE_3_B 0x71388
+#define _PLANE_STRIDE_1(pipe) \
+ _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
+#define _PLANE_STRIDE_2(pipe) \
+ _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
+#define _PLANE_STRIDE_3(pipe) \
+ _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
+#define PLANE_STRIDE(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
+
+#define _PLANE_POS_1_B 0x7118c
+#define _PLANE_POS_2_B 0x7128c
+#define _PLANE_POS_3_B 0x7138c
+#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
+#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
+#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
+#define PLANE_POS(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
+
+#define _PLANE_SIZE_1_B 0x71190
+#define _PLANE_SIZE_2_B 0x71290
+#define _PLANE_SIZE_3_B 0x71390
+#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
+#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
+#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
+#define PLANE_SIZE(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
+
+#define _PLANE_SURF_1_B 0x7119c
+#define _PLANE_SURF_2_B 0x7129c
+#define _PLANE_SURF_3_B 0x7139c
+#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
+#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
+#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
+#define PLANE_SURF(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+
+#define _PLANE_OFFSET_1_B 0x711a4
+#define _PLANE_OFFSET_2_B 0x712a4
+#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
+#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
+#define PLANE_OFFSET(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
+
+#define _PLANE_KEYVAL_1_B 0x71194
+#define _PLANE_KEYVAL_2_B 0x71294
+#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
+#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
+#define PLANE_KEYVAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
+
+#define _PLANE_KEYMSK_1_B 0x71198
+#define _PLANE_KEYMSK_2_B 0x71298
+#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
+#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
+#define PLANE_KEYMSK(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
+
+#define _PLANE_KEYMAX_1_B 0x711a0
+#define _PLANE_KEYMAX_2_B 0x712a0
+#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
+#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
+#define PLANE_KEYMAX(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
+
+#define _PLANE_SURFLIVE_1_B 0x711ac
+#define _PLANE_SURFLIVE_2_B 0x712ac
+#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B)
+#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
+#define PLANE_SURFLIVE(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
+
+#define _PLANE_CHICKEN_1_B 0x7126c
+#define _PLANE_CHICKEN_2_B 0x7136c
+#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B)
+#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
+#define PLANE_CHICKEN(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
+
+#define _PLANE_AUX_DIST_1_B 0x711c0
+#define _PLANE_AUX_DIST_2_B 0x712c0
+#define _PLANE_AUX_DIST_1(pipe) \
+ _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
+#define _PLANE_AUX_DIST_2(pipe) \
+ _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
+#define PLANE_AUX_DIST(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
+
+#define _PLANE_AUX_OFFSET_1_B 0x711c4
+#define _PLANE_AUX_OFFSET_2_B 0x712c4
+#define _PLANE_AUX_OFFSET_1(pipe) \
+ _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
+#define _PLANE_AUX_OFFSET_2(pipe) \
+ _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
+#define PLANE_AUX_OFFSET(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
+
+#define _PLANE_CUS_CTL_1_B 0x711c8
+#define _PLANE_CUS_CTL_2_B 0x712c8
+#define _PLANE_CUS_CTL_1(pipe) \
+ _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
+#define _PLANE_CUS_CTL_2(pipe) \
+ _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
+#define PLANE_CUS_CTL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
+
+#define _PLANE_COLOR_CTL_1_B 0x711CC
+#define _PLANE_COLOR_CTL_2_B 0x712CC
+#define _PLANE_COLOR_CTL_3_B 0x713CC
+#define _PLANE_COLOR_CTL_1(pipe) \
+ _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
+#define _PLANE_COLOR_CTL_2(pipe) \
+ _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
+#define PLANE_COLOR_CTL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
+
+/* Plane CSC Registers */
+#define _PLANE_CSC_RY_GY_1_A 0x70210
+#define _PLANE_CSC_RY_GY_2_A 0x70310
+
+#define _PLANE_CSC_RY_GY_1_B 0x71210
+#define _PLANE_CSC_RY_GY_2_B 0x71310
+
+#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
+ _PLANE_CSC_RY_GY_1_B)
+#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, \
+ _PLANE_CSC_RY_GY_2_B)
+#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
+ _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
+ _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
+
+#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
+#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
+
+#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
+#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
+
+#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
+ _PLANE_CSC_PREOFF_HI_1_B)
+#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
+ _PLANE_CSC_PREOFF_HI_2_B)
+#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
+ (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
+ (index) * 4)
+
+#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
+#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
+
+#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
+#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
+
+#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
+ _PLANE_CSC_POSTOFF_HI_1_B)
+#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
+ _PLANE_CSC_POSTOFF_HI_2_B)
+#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
+ (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
+ (index) * 4)
+
+#endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index f85980aba25e..53a565c673e2 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -21,6 +21,7 @@
#include "intel_fixed.h"
#include "intel_pcode.h"
#include "intel_wm.h"
+#include "skl_universal_plane_regs.h"
#include "skl_watermark.h"
#include "skl_watermark_regs.h"
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c
index 6834f9fe40cf..9efc3ca0ce82 100644
--- a/drivers/gpu/drm/i915/gvt/dmabuf.c
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
@@ -37,9 +37,10 @@
#include "gem/i915_gem_dmabuf.h"
#include "i915_drv.h"
-#include "i915_reg.h"
#include "gvt.h"
+#include "display/skl_universal_plane_regs.h"
+
#define GEN8_DECODE_PTE(pte) (pte & GENMASK_ULL(63, 12))
static int vgpu_gem_get_pages(struct drm_i915_gem_object *obj)
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 4140da68aabb..dd6eb0ae003a 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -41,6 +41,7 @@
#include "i915_reg.h"
#include "display/intel_sprite_regs.h"
+#include "display/skl_universal_plane_regs.h"
#define PRIMARY_FORMAT_NUM 16
struct pixel_format {
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 102eb354fed6..aae0443015f0 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -51,6 +51,7 @@
#include "display/intel_pps_regs.h"
#include "display/intel_psr_regs.h"
#include "display/intel_sprite_regs.h"
+#include "display/skl_universal_plane_regs.h"
#include "display/skl_watermark_regs.h"
#include "display/vlv_dsi_pll_regs.h"
#include "gt/intel_gt_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0f4a2d542d81..08725dc7883e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2481,358 +2481,6 @@
#define _PIPEDSI0CONF 0x7b008
#define _PIPEDSI1CONF 0x7b808
-/* Skylake plane registers */
-
-#define _PLANE_CTL_1_A 0x70180
-#define _PLANE_CTL_2_A 0x70280
-#define _PLANE_CTL_3_A 0x70380
-#define PLANE_CTL_ENABLE REG_BIT(31)
-#define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
-#define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
-#define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
-#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
-/*
- * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
- * expanded to include bit 23 as well. However, the shift-24 based values
- * correctly map to the same formats in ICL, as long as bit 23 is set to 0
- */
-#define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */
-#define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */
-#define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
-#define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1)
-#define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2)
-#define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3)
-#define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4)
-#define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5)
-#define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6)
-#define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7)
-#define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8)
-#define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12)
-#define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14)
-#define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1)
-#define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3)
-#define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5)
-#define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7)
-#define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9)
-#define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11)
-#define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
-#define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21)
-#define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1)
-#define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2)
-#define PLANE_CTL_ORDER_RGBX REG_BIT(20)
-#define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19)
-#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18)
-#define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16)
-#define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)
-#define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1)
-#define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2)
-#define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3)
-#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15)
-#define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14)
-#define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
-#define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
-#define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10)
-#define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0)
-#define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1)
-#define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4)
-#define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
-#define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
-#define PLANE_CTL_ASYNC_FLIP REG_BIT(9)
-#define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8)
-#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
-#define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
-#define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0)
-#define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2)
-#define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3)
-#define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0)
-#define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0)
-#define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
-#define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
-#define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
-#define _PLANE_STRIDE_1_A 0x70188
-#define _PLANE_STRIDE_2_A 0x70288
-#define _PLANE_STRIDE_3_A 0x70388
-#define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
-#define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
-#define _PLANE_POS_1_A 0x7018c
-#define _PLANE_POS_2_A 0x7028c
-#define _PLANE_POS_3_A 0x7038c
-#define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
-#define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
-#define PLANE_POS_X_MASK REG_GENMASK(15, 0)
-#define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
-#define _PLANE_SIZE_1_A 0x70190
-#define _PLANE_SIZE_2_A 0x70290
-#define _PLANE_SIZE_3_A 0x70390
-#define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
-#define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
-#define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
-#define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
-#define _PLANE_SURF_1_A 0x7019c
-#define _PLANE_SURF_2_A 0x7029c
-#define _PLANE_SURF_3_A 0x7039c
-#define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
-#define PLANE_SURF_DECRYPT REG_BIT(2)
-#define _PLANE_OFFSET_1_A 0x701a4
-#define _PLANE_OFFSET_2_A 0x702a4
-#define _PLANE_OFFSET_3_A 0x703a4
-#define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
-#define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
-#define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
-#define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))
-#define _PLANE_KEYVAL_1_A 0x70194
-#define _PLANE_KEYVAL_2_A 0x70294
-#define _PLANE_KEYMSK_1_A 0x70198
-#define _PLANE_KEYMSK_2_A 0x70298
-#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31)
-#define _PLANE_KEYMAX_1_A 0x701a0
-#define _PLANE_KEYMAX_2_A 0x702a0
-#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24)
-#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a))
-#define _PLANE_SURFLIVE_1_A 0x701ac
-#define _PLANE_SURFLIVE_2_A 0x702ac
-#define _PLANE_CC_VAL_1_A 0x701b4
-#define _PLANE_CC_VAL_2_A 0x702b4
-#define _PLANE_AUX_DIST_1_A 0x701c0
-#define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
-#define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
-#define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
-#define _PLANE_AUX_DIST_2_A 0x702c0
-#define _PLANE_AUX_OFFSET_1_A 0x701c4
-#define _PLANE_AUX_OFFSET_2_A 0x702c4
-#define _PLANE_CUS_CTL_1_A 0x701c8
-#define _PLANE_CUS_CTL_2_A 0x702c8
-#define PLANE_CUS_ENABLE REG_BIT(31)
-#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
-#define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
-#define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
-#define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
-#define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
-#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
-#define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16)
-#define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
-#define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
-#define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
-#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
-#define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12)
-#define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
-#define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
-#define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
-#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
-#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
-#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
-#define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
-#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
-#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
-#define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
-#define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
-#define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17)
-#define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
-#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)
-#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2)
-#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3)
-#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4)
-#define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13)
-#define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4)
-#define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
-#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
-#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
-#define _PLANE_CHICKEN_1_A 0x7026C /* tgl+ */
-#define _PLANE_CHICKEN_2_A 0x7036C /* tgl+ */
-#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
-#define _PLANE_BUF_CFG_1_A 0x7027c
-#define _PLANE_BUF_CFG_2_A 0x7037c
-/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
-#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
-#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
-#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
-#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
-#define _PLANE_NV12_BUF_CFG_1_A 0x70278
-#define _PLANE_NV12_BUF_CFG_2_A 0x70378
-
-#define _PLANE_CC_VAL_1_B 0x711b4
-#define _PLANE_CC_VAL_2_B 0x712b4
-#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
-#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
-#define PLANE_CC_VAL(pipe, plane, dw) \
- _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
-
-/* Input CSC Register Definitions */
-#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
-#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
-
-#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
-#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
-
-#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
- _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
- _PLANE_INPUT_CSC_RY_GY_1_B)
-#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
- _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
- _PLANE_INPUT_CSC_RY_GY_2_B)
-
-#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
- _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
-
-#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
-#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
-
-#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
-#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
-
-#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
- _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
- _PLANE_INPUT_CSC_PREOFF_HI_1_B)
-#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
- _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
- _PLANE_INPUT_CSC_PREOFF_HI_2_B)
-#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
- _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
-
-#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
-#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
-
-#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
-#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
-
-#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
- _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
- _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
-#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
- _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
- _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
-#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
- _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
-
-#define _PLANE_CTL_1_B 0x71180
-#define _PLANE_CTL_2_B 0x71280
-#define _PLANE_CTL_3_B 0x71380
-#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
-#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
-#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
-#define PLANE_CTL(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
-
-#define _PLANE_STRIDE_1_B 0x71188
-#define _PLANE_STRIDE_2_B 0x71288
-#define _PLANE_STRIDE_3_B 0x71388
-#define _PLANE_STRIDE_1(pipe) \
- _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
-#define _PLANE_STRIDE_2(pipe) \
- _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
-#define _PLANE_STRIDE_3(pipe) \
- _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
-#define PLANE_STRIDE(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
-
-#define _PLANE_POS_1_B 0x7118c
-#define _PLANE_POS_2_B 0x7128c
-#define _PLANE_POS_3_B 0x7138c
-#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
-#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
-#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
-#define PLANE_POS(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
-
-#define _PLANE_SIZE_1_B 0x71190
-#define _PLANE_SIZE_2_B 0x71290
-#define _PLANE_SIZE_3_B 0x71390
-#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
-#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
-#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
-#define PLANE_SIZE(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
-
-#define _PLANE_SURF_1_B 0x7119c
-#define _PLANE_SURF_2_B 0x7129c
-#define _PLANE_SURF_3_B 0x7139c
-#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
-#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
-#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
-#define PLANE_SURF(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
-
-#define _PLANE_OFFSET_1_B 0x711a4
-#define _PLANE_OFFSET_2_B 0x712a4
-#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
-#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
-#define PLANE_OFFSET(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
-
-#define _PLANE_KEYVAL_1_B 0x71194
-#define _PLANE_KEYVAL_2_B 0x71294
-#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
-#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
-#define PLANE_KEYVAL(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
-
-#define _PLANE_KEYMSK_1_B 0x71198
-#define _PLANE_KEYMSK_2_B 0x71298
-#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
-#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
-#define PLANE_KEYMSK(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
-
-#define _PLANE_KEYMAX_1_B 0x711a0
-#define _PLANE_KEYMAX_2_B 0x712a0
-#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
-#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
-#define PLANE_KEYMAX(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
-
-#define _PLANE_SURFLIVE_1_B 0x711ac
-#define _PLANE_SURFLIVE_2_B 0x712ac
-#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B)
-#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
-#define PLANE_SURFLIVE(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
-
-#define _PLANE_CHICKEN_1_B 0x7126c
-#define _PLANE_CHICKEN_2_B 0x7136c
-#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B)
-#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
-#define PLANE_CHICKEN(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
-
-#define _PLANE_AUX_DIST_1_B 0x711c0
-#define _PLANE_AUX_DIST_2_B 0x712c0
-#define _PLANE_AUX_DIST_1(pipe) \
- _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
-#define _PLANE_AUX_DIST_2(pipe) \
- _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
-#define PLANE_AUX_DIST(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
-
-#define _PLANE_AUX_OFFSET_1_B 0x711c4
-#define _PLANE_AUX_OFFSET_2_B 0x712c4
-#define _PLANE_AUX_OFFSET_1(pipe) \
- _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
-#define _PLANE_AUX_OFFSET_2(pipe) \
- _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
-#define PLANE_AUX_OFFSET(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
-
-#define _PLANE_CUS_CTL_1_B 0x711c8
-#define _PLANE_CUS_CTL_2_B 0x712c8
-#define _PLANE_CUS_CTL_1(pipe) \
- _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
-#define _PLANE_CUS_CTL_2(pipe) \
- _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
-#define PLANE_CUS_CTL(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
-
-#define _PLANE_COLOR_CTL_1_B 0x711CC
-#define _PLANE_COLOR_CTL_2_B 0x712CC
-#define _PLANE_COLOR_CTL_3_B 0x713CC
-#define _PLANE_COLOR_CTL_1(pipe) \
- _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
-#define _PLANE_COLOR_CTL_2(pipe) \
- _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
-#define PLANE_COLOR_CTL(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
/* VBIOS regs */
#define VGACNTRL _MMIO(0x71400)
@@ -5151,49 +4799,6 @@ enum skl_power_gate {
#define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
#define WM_DBG_DISALLOW_SPRITE (1 << 2)
-/* Plane CSC Registers */
-#define _PLANE_CSC_RY_GY_1_A 0x70210
-#define _PLANE_CSC_RY_GY_2_A 0x70310
-
-#define _PLANE_CSC_RY_GY_1_B 0x71210
-#define _PLANE_CSC_RY_GY_2_B 0x71310
-
-#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
- _PLANE_CSC_RY_GY_1_B)
-#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, \
- _PLANE_CSC_RY_GY_2_B)
-#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
- _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
- _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
-
-#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
-#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
-
-#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
-#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
-
-#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
- _PLANE_CSC_PREOFF_HI_1_B)
-#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
- _PLANE_CSC_PREOFF_HI_2_B)
-#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
- (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
- (index) * 4)
-
-#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
-#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
-
-#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
-#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
-
-#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
- _PLANE_CSC_POSTOFF_HI_1_B)
-#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
- _PLANE_CSC_POSTOFF_HI_2_B)
-#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
- (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
- (index) * 4)
-
/* Gen4+ Timestamp and Pipe Frame time stamp registers */
#define GEN4_TIMESTAMP _MMIO(0x2358)
#define ILK_TIMESTAMP_HI _MMIO(0x70070)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index e1a35f70b544..178eba121881 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -16,6 +16,7 @@
#include "display/intel_lvds_regs.h"
#include "display/intel_psr_regs.h"
#include "display/intel_sprite_regs.h"
+#include "display/skl_universal_plane_regs.h"
#include "display/skl_watermark_regs.h"
#include "display/vlv_dsi_pll_regs.h"
#include "gt/intel_engine_regs.h"
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 02/16] drm/i915: Extract skl_universal_plane_regs.h
2024-05-10 15:23 ` [PATCH 02/16] drm/i915: Extract skl_universal_plane_regs.h Ville Syrjala
@ 2024-05-13 10:07 ` Jani Nikula
0 siblings, 0 replies; 48+ messages in thread
From: Jani Nikula @ 2024-05-13 10:07 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: Zhenyu Wang, Zhi Wang
On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move most of the SKL+ universal plane register definitions
> into their own file. Declutters i915_reg.h a bit more.
>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> CC: Zhi Wang <zhi.wang.linux@gmail.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> .../gpu/drm/i915/display/intel_dpt_common.c | 1 +
> .../drm/i915/display/skl_universal_plane.c | 1 +
> .../i915/display/skl_universal_plane_regs.h | 405 ++++++++++++++++++
> drivers/gpu/drm/i915/display/skl_watermark.c | 1 +
> drivers/gpu/drm/i915/gvt/dmabuf.c | 3 +-
> drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 +
> drivers/gpu/drm/i915/gvt/handlers.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 395 -----------------
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
> 10 files changed, 414 insertions(+), 396 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ef986b508431..a2c331c696fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -119,6 +119,7 @@
> #include "intel_wm.h"
> #include "skl_scaler.h"
> #include "skl_universal_plane.h"
> +#include "skl_universal_plane_regs.h"
> #include "skl_watermark.h"
> #include "vlv_dpio_phy_regs.h"
> #include "vlv_dsi.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dpt_common.c b/drivers/gpu/drm/i915/display/intel_dpt_common.c
> index cdba47165c04..573f72068899 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpt_common.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpt_common.c
> @@ -7,6 +7,7 @@
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_dpt_common.h"
> +#include "skl_universal_plane_regs.h"
>
> void intel_dpt_configure(struct intel_crtc *crtc)
> {
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 0a8e781a3648..ab560820bb23 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -21,6 +21,7 @@
> #include "intel_psr_regs.h"
> #include "skl_scaler.h"
> #include "skl_universal_plane.h"
> +#include "skl_universal_plane_regs.h"
> #include "skl_watermark.h"
> #include "pxp/intel_pxp.h"
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> new file mode 100644
> index 000000000000..7e34470beb74
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> @@ -0,0 +1,405 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +#ifndef __SKL_UNIVERSAL_PLANE_REGS_H__
> +#define __SKL_UNIVERSAL_PLANE_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +#define _PLANE_CTL_1_A 0x70180
> +#define _PLANE_CTL_2_A 0x70280
> +#define _PLANE_CTL_3_A 0x70380
> +#define PLANE_CTL_ENABLE REG_BIT(31)
> +#define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
> +#define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
> +#define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
> +#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
> +/*
> + * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
> + * expanded to include bit 23 as well. However, the shift-24 based values
> + * correctly map to the same formats in ICL, as long as bit 23 is set to 0
> + */
> +#define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */
> +#define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */
> +#define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
> +#define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1)
> +#define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2)
> +#define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3)
> +#define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4)
> +#define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5)
> +#define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6)
> +#define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7)
> +#define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8)
> +#define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12)
> +#define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14)
> +#define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1)
> +#define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3)
> +#define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5)
> +#define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7)
> +#define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9)
> +#define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11)
> +#define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
> +#define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21)
> +#define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1)
> +#define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2)
> +#define PLANE_CTL_ORDER_RGBX REG_BIT(20)
> +#define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19)
> +#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18)
> +#define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16)
> +#define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)
> +#define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1)
> +#define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2)
> +#define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3)
> +#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15)
> +#define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14)
> +#define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
> +#define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
> +#define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10)
> +#define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0)
> +#define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1)
> +#define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4)
> +#define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
> +#define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
> +#define PLANE_CTL_ASYNC_FLIP REG_BIT(9)
> +#define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8)
> +#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
> +#define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
> +#define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0)
> +#define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2)
> +#define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3)
> +#define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0)
> +#define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0)
> +#define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
> +#define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
> +#define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
> +#define _PLANE_STRIDE_1_A 0x70188
> +#define _PLANE_STRIDE_2_A 0x70288
> +#define _PLANE_STRIDE_3_A 0x70388
> +#define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
> +#define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
> +#define _PLANE_POS_1_A 0x7018c
> +#define _PLANE_POS_2_A 0x7028c
> +#define _PLANE_POS_3_A 0x7038c
> +#define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
> +#define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
> +#define PLANE_POS_X_MASK REG_GENMASK(15, 0)
> +#define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
> +#define _PLANE_SIZE_1_A 0x70190
> +#define _PLANE_SIZE_2_A 0x70290
> +#define _PLANE_SIZE_3_A 0x70390
> +#define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
> +#define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
> +#define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
> +#define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
> +#define _PLANE_SURF_1_A 0x7019c
> +#define _PLANE_SURF_2_A 0x7029c
> +#define _PLANE_SURF_3_A 0x7039c
> +#define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
> +#define PLANE_SURF_DECRYPT REG_BIT(2)
> +#define _PLANE_OFFSET_1_A 0x701a4
> +#define _PLANE_OFFSET_2_A 0x702a4
> +#define _PLANE_OFFSET_3_A 0x703a4
> +#define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
> +#define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
> +#define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
> +#define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))
> +#define _PLANE_KEYVAL_1_A 0x70194
> +#define _PLANE_KEYVAL_2_A 0x70294
> +#define _PLANE_KEYMSK_1_A 0x70198
> +#define _PLANE_KEYMSK_2_A 0x70298
> +#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31)
> +#define _PLANE_KEYMAX_1_A 0x701a0
> +#define _PLANE_KEYMAX_2_A 0x702a0
> +#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24)
> +#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a))
> +#define _PLANE_SURFLIVE_1_A 0x701ac
> +#define _PLANE_SURFLIVE_2_A 0x702ac
> +#define _PLANE_CC_VAL_1_A 0x701b4
> +#define _PLANE_CC_VAL_2_A 0x702b4
> +#define _PLANE_AUX_DIST_1_A 0x701c0
> +#define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
> +#define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
> +#define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
> +#define _PLANE_AUX_DIST_2_A 0x702c0
> +#define _PLANE_AUX_OFFSET_1_A 0x701c4
> +#define _PLANE_AUX_OFFSET_2_A 0x702c4
> +#define _PLANE_CUS_CTL_1_A 0x701c8
> +#define _PLANE_CUS_CTL_2_A 0x702c8
> +#define PLANE_CUS_ENABLE REG_BIT(31)
> +#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
> +#define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
> +#define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
> +#define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
> +#define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
> +#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
> +#define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16)
> +#define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
> +#define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
> +#define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
> +#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
> +#define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12)
> +#define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
> +#define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
> +#define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
> +#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
> +#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
> +#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
> +#define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
> +#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
> +#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
> +#define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
> +#define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
> +#define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17)
> +#define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
> +#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)
> +#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2)
> +#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3)
> +#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4)
> +#define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13)
> +#define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4)
> +#define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
> +#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
> +#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
> +#define _PLANE_CHICKEN_1_A 0x7026C /* tgl+ */
> +#define _PLANE_CHICKEN_2_A 0x7036C /* tgl+ */
> +#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
> +#define _PLANE_BUF_CFG_1_A 0x7027c
> +#define _PLANE_BUF_CFG_2_A 0x7037c
> +/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
> +#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
> +#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
> +#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
> +#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
> +#define _PLANE_NV12_BUF_CFG_1_A 0x70278
> +#define _PLANE_NV12_BUF_CFG_2_A 0x70378
> +
> +#define _PLANE_CC_VAL_1_B 0x711b4
> +#define _PLANE_CC_VAL_2_B 0x712b4
> +#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
> +#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
> +#define PLANE_CC_VAL(pipe, plane, dw) \
> + _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
> +
> +/* Input CSC Register Definitions */
> +#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
> +#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
> +
> +#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
> +#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
> +
> +#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
> + _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
> + _PLANE_INPUT_CSC_RY_GY_1_B)
> +#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
> + _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
> + _PLANE_INPUT_CSC_RY_GY_2_B)
> +
> +#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
> + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
> + _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
> +
> +#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
> +#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
> +
> +#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
> +#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
> +
> +#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
> + _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
> + _PLANE_INPUT_CSC_PREOFF_HI_1_B)
> +#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
> + _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
> + _PLANE_INPUT_CSC_PREOFF_HI_2_B)
> +#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
> + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
> + _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
> +
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
> +
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
> +
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
> + _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
> + _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
> + _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
> + _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
> +#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
> + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
> + _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
> +
> +#define _PLANE_CTL_1_B 0x71180
> +#define _PLANE_CTL_2_B 0x71280
> +#define _PLANE_CTL_3_B 0x71380
> +#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
> +#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
> +#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
> +#define PLANE_CTL(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
> +
> +#define _PLANE_STRIDE_1_B 0x71188
> +#define _PLANE_STRIDE_2_B 0x71288
> +#define _PLANE_STRIDE_3_B 0x71388
> +#define _PLANE_STRIDE_1(pipe) \
> + _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
> +#define _PLANE_STRIDE_2(pipe) \
> + _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
> +#define _PLANE_STRIDE_3(pipe) \
> + _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
> +#define PLANE_STRIDE(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
> +
> +#define _PLANE_POS_1_B 0x7118c
> +#define _PLANE_POS_2_B 0x7128c
> +#define _PLANE_POS_3_B 0x7138c
> +#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
> +#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
> +#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
> +#define PLANE_POS(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
> +
> +#define _PLANE_SIZE_1_B 0x71190
> +#define _PLANE_SIZE_2_B 0x71290
> +#define _PLANE_SIZE_3_B 0x71390
> +#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
> +#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
> +#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
> +#define PLANE_SIZE(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
> +
> +#define _PLANE_SURF_1_B 0x7119c
> +#define _PLANE_SURF_2_B 0x7129c
> +#define _PLANE_SURF_3_B 0x7139c
> +#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
> +#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
> +#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
> +#define PLANE_SURF(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
> +
> +#define _PLANE_OFFSET_1_B 0x711a4
> +#define _PLANE_OFFSET_2_B 0x712a4
> +#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
> +#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
> +#define PLANE_OFFSET(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
> +
> +#define _PLANE_KEYVAL_1_B 0x71194
> +#define _PLANE_KEYVAL_2_B 0x71294
> +#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
> +#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
> +#define PLANE_KEYVAL(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
> +
> +#define _PLANE_KEYMSK_1_B 0x71198
> +#define _PLANE_KEYMSK_2_B 0x71298
> +#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
> +#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
> +#define PLANE_KEYMSK(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
> +
> +#define _PLANE_KEYMAX_1_B 0x711a0
> +#define _PLANE_KEYMAX_2_B 0x712a0
> +#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
> +#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
> +#define PLANE_KEYMAX(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
> +
> +#define _PLANE_SURFLIVE_1_B 0x711ac
> +#define _PLANE_SURFLIVE_2_B 0x712ac
> +#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B)
> +#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
> +#define PLANE_SURFLIVE(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
> +
> +#define _PLANE_CHICKEN_1_B 0x7126c
> +#define _PLANE_CHICKEN_2_B 0x7136c
> +#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B)
> +#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
> +#define PLANE_CHICKEN(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
> +
> +#define _PLANE_AUX_DIST_1_B 0x711c0
> +#define _PLANE_AUX_DIST_2_B 0x712c0
> +#define _PLANE_AUX_DIST_1(pipe) \
> + _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
> +#define _PLANE_AUX_DIST_2(pipe) \
> + _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
> +#define PLANE_AUX_DIST(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
> +
> +#define _PLANE_AUX_OFFSET_1_B 0x711c4
> +#define _PLANE_AUX_OFFSET_2_B 0x712c4
> +#define _PLANE_AUX_OFFSET_1(pipe) \
> + _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
> +#define _PLANE_AUX_OFFSET_2(pipe) \
> + _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
> +#define PLANE_AUX_OFFSET(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
> +
> +#define _PLANE_CUS_CTL_1_B 0x711c8
> +#define _PLANE_CUS_CTL_2_B 0x712c8
> +#define _PLANE_CUS_CTL_1(pipe) \
> + _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
> +#define _PLANE_CUS_CTL_2(pipe) \
> + _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
> +#define PLANE_CUS_CTL(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
> +
> +#define _PLANE_COLOR_CTL_1_B 0x711CC
> +#define _PLANE_COLOR_CTL_2_B 0x712CC
> +#define _PLANE_COLOR_CTL_3_B 0x713CC
> +#define _PLANE_COLOR_CTL_1(pipe) \
> + _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
> +#define _PLANE_COLOR_CTL_2(pipe) \
> + _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
> +#define PLANE_COLOR_CTL(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
> +
> +/* Plane CSC Registers */
> +#define _PLANE_CSC_RY_GY_1_A 0x70210
> +#define _PLANE_CSC_RY_GY_2_A 0x70310
> +
> +#define _PLANE_CSC_RY_GY_1_B 0x71210
> +#define _PLANE_CSC_RY_GY_2_B 0x71310
> +
> +#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
> + _PLANE_CSC_RY_GY_1_B)
> +#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, \
> + _PLANE_CSC_RY_GY_2_B)
> +#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
> + _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
> + _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
> +
> +#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
> +#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
> +
> +#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
> +#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
> +
> +#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
> + _PLANE_CSC_PREOFF_HI_1_B)
> +#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
> + _PLANE_CSC_PREOFF_HI_2_B)
> +#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
> + (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
> + (index) * 4)
> +
> +#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
> +#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
> +
> +#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
> +#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
> +
> +#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
> + _PLANE_CSC_POSTOFF_HI_1_B)
> +#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
> + _PLANE_CSC_POSTOFF_HI_2_B)
> +#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
> + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
> + (index) * 4)
> +
> +#endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index f85980aba25e..53a565c673e2 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -21,6 +21,7 @@
> #include "intel_fixed.h"
> #include "intel_pcode.h"
> #include "intel_wm.h"
> +#include "skl_universal_plane_regs.h"
> #include "skl_watermark.h"
> #include "skl_watermark_regs.h"
>
> diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c
> index 6834f9fe40cf..9efc3ca0ce82 100644
> --- a/drivers/gpu/drm/i915/gvt/dmabuf.c
> +++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
> @@ -37,9 +37,10 @@
> #include "gem/i915_gem_dmabuf.h"
>
> #include "i915_drv.h"
> -#include "i915_reg.h"
> #include "gvt.h"
>
> +#include "display/skl_universal_plane_regs.h"
> +
> #define GEN8_DECODE_PTE(pte) (pte & GENMASK_ULL(63, 12))
>
> static int vgpu_gem_get_pages(struct drm_i915_gem_object *obj)
> diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> index 4140da68aabb..dd6eb0ae003a 100644
> --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
> +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> @@ -41,6 +41,7 @@
> #include "i915_reg.h"
>
> #include "display/intel_sprite_regs.h"
> +#include "display/skl_universal_plane_regs.h"
>
> #define PRIMARY_FORMAT_NUM 16
> struct pixel_format {
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 102eb354fed6..aae0443015f0 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -51,6 +51,7 @@
> #include "display/intel_pps_regs.h"
> #include "display/intel_psr_regs.h"
> #include "display/intel_sprite_regs.h"
> +#include "display/skl_universal_plane_regs.h"
> #include "display/skl_watermark_regs.h"
> #include "display/vlv_dsi_pll_regs.h"
> #include "gt/intel_gt_regs.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0f4a2d542d81..08725dc7883e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2481,358 +2481,6 @@
> #define _PIPEDSI0CONF 0x7b008
> #define _PIPEDSI1CONF 0x7b808
>
> -/* Skylake plane registers */
> -
> -#define _PLANE_CTL_1_A 0x70180
> -#define _PLANE_CTL_2_A 0x70280
> -#define _PLANE_CTL_3_A 0x70380
> -#define PLANE_CTL_ENABLE REG_BIT(31)
> -#define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
> -#define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
> -#define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
> -#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
> -/*
> - * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
> - * expanded to include bit 23 as well. However, the shift-24 based values
> - * correctly map to the same formats in ICL, as long as bit 23 is set to 0
> - */
> -#define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */
> -#define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */
> -#define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
> -#define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1)
> -#define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2)
> -#define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3)
> -#define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4)
> -#define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5)
> -#define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6)
> -#define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7)
> -#define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8)
> -#define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12)
> -#define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14)
> -#define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1)
> -#define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3)
> -#define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5)
> -#define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7)
> -#define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9)
> -#define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11)
> -#define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
> -#define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21)
> -#define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1)
> -#define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2)
> -#define PLANE_CTL_ORDER_RGBX REG_BIT(20)
> -#define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19)
> -#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18)
> -#define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16)
> -#define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)
> -#define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1)
> -#define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2)
> -#define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3)
> -#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15)
> -#define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14)
> -#define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
> -#define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
> -#define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10)
> -#define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0)
> -#define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1)
> -#define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4)
> -#define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
> -#define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
> -#define PLANE_CTL_ASYNC_FLIP REG_BIT(9)
> -#define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8)
> -#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
> -#define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
> -#define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0)
> -#define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2)
> -#define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3)
> -#define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0)
> -#define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0)
> -#define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
> -#define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
> -#define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
> -#define _PLANE_STRIDE_1_A 0x70188
> -#define _PLANE_STRIDE_2_A 0x70288
> -#define _PLANE_STRIDE_3_A 0x70388
> -#define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
> -#define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
> -#define _PLANE_POS_1_A 0x7018c
> -#define _PLANE_POS_2_A 0x7028c
> -#define _PLANE_POS_3_A 0x7038c
> -#define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
> -#define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
> -#define PLANE_POS_X_MASK REG_GENMASK(15, 0)
> -#define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
> -#define _PLANE_SIZE_1_A 0x70190
> -#define _PLANE_SIZE_2_A 0x70290
> -#define _PLANE_SIZE_3_A 0x70390
> -#define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
> -#define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
> -#define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
> -#define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
> -#define _PLANE_SURF_1_A 0x7019c
> -#define _PLANE_SURF_2_A 0x7029c
> -#define _PLANE_SURF_3_A 0x7039c
> -#define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
> -#define PLANE_SURF_DECRYPT REG_BIT(2)
> -#define _PLANE_OFFSET_1_A 0x701a4
> -#define _PLANE_OFFSET_2_A 0x702a4
> -#define _PLANE_OFFSET_3_A 0x703a4
> -#define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
> -#define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
> -#define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
> -#define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))
> -#define _PLANE_KEYVAL_1_A 0x70194
> -#define _PLANE_KEYVAL_2_A 0x70294
> -#define _PLANE_KEYMSK_1_A 0x70198
> -#define _PLANE_KEYMSK_2_A 0x70298
> -#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31)
> -#define _PLANE_KEYMAX_1_A 0x701a0
> -#define _PLANE_KEYMAX_2_A 0x702a0
> -#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24)
> -#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a))
> -#define _PLANE_SURFLIVE_1_A 0x701ac
> -#define _PLANE_SURFLIVE_2_A 0x702ac
> -#define _PLANE_CC_VAL_1_A 0x701b4
> -#define _PLANE_CC_VAL_2_A 0x702b4
> -#define _PLANE_AUX_DIST_1_A 0x701c0
> -#define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
> -#define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
> -#define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
> -#define _PLANE_AUX_DIST_2_A 0x702c0
> -#define _PLANE_AUX_OFFSET_1_A 0x701c4
> -#define _PLANE_AUX_OFFSET_2_A 0x702c4
> -#define _PLANE_CUS_CTL_1_A 0x701c8
> -#define _PLANE_CUS_CTL_2_A 0x702c8
> -#define PLANE_CUS_ENABLE REG_BIT(31)
> -#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
> -#define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
> -#define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
> -#define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
> -#define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
> -#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
> -#define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16)
> -#define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
> -#define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
> -#define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
> -#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
> -#define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12)
> -#define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
> -#define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
> -#define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
> -#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
> -#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
> -#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
> -#define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
> -#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
> -#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
> -#define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
> -#define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
> -#define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17)
> -#define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
> -#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)
> -#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2)
> -#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3)
> -#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4)
> -#define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13)
> -#define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4)
> -#define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
> -#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
> -#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
> -#define _PLANE_CHICKEN_1_A 0x7026C /* tgl+ */
> -#define _PLANE_CHICKEN_2_A 0x7036C /* tgl+ */
> -#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
> -#define _PLANE_BUF_CFG_1_A 0x7027c
> -#define _PLANE_BUF_CFG_2_A 0x7037c
> -/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
> -#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
> -#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
> -#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
> -#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
> -#define _PLANE_NV12_BUF_CFG_1_A 0x70278
> -#define _PLANE_NV12_BUF_CFG_2_A 0x70378
> -
> -#define _PLANE_CC_VAL_1_B 0x711b4
> -#define _PLANE_CC_VAL_2_B 0x712b4
> -#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
> -#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
> -#define PLANE_CC_VAL(pipe, plane, dw) \
> - _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
> -
> -/* Input CSC Register Definitions */
> -#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
> -#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
> -
> -#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
> -#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
> -
> -#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
> - _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
> - _PLANE_INPUT_CSC_RY_GY_1_B)
> -#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
> - _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
> - _PLANE_INPUT_CSC_RY_GY_2_B)
> -
> -#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
> - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
> - _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
> -
> -#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
> -#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
> -
> -#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
> -#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
> -
> -#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
> - _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
> - _PLANE_INPUT_CSC_PREOFF_HI_1_B)
> -#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
> - _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
> - _PLANE_INPUT_CSC_PREOFF_HI_2_B)
> -#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
> - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
> - _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
> -
> -#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
> -#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
> -
> -#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
> -#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
> -
> -#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
> - _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
> - _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
> -#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
> - _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
> - _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
> -#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
> - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
> - _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
> -
> -#define _PLANE_CTL_1_B 0x71180
> -#define _PLANE_CTL_2_B 0x71280
> -#define _PLANE_CTL_3_B 0x71380
> -#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
> -#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
> -#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
> -#define PLANE_CTL(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
> -
> -#define _PLANE_STRIDE_1_B 0x71188
> -#define _PLANE_STRIDE_2_B 0x71288
> -#define _PLANE_STRIDE_3_B 0x71388
> -#define _PLANE_STRIDE_1(pipe) \
> - _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
> -#define _PLANE_STRIDE_2(pipe) \
> - _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
> -#define _PLANE_STRIDE_3(pipe) \
> - _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
> -#define PLANE_STRIDE(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
> -
> -#define _PLANE_POS_1_B 0x7118c
> -#define _PLANE_POS_2_B 0x7128c
> -#define _PLANE_POS_3_B 0x7138c
> -#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
> -#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
> -#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
> -#define PLANE_POS(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
> -
> -#define _PLANE_SIZE_1_B 0x71190
> -#define _PLANE_SIZE_2_B 0x71290
> -#define _PLANE_SIZE_3_B 0x71390
> -#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
> -#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
> -#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
> -#define PLANE_SIZE(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
> -
> -#define _PLANE_SURF_1_B 0x7119c
> -#define _PLANE_SURF_2_B 0x7129c
> -#define _PLANE_SURF_3_B 0x7139c
> -#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
> -#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
> -#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
> -#define PLANE_SURF(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
> -
> -#define _PLANE_OFFSET_1_B 0x711a4
> -#define _PLANE_OFFSET_2_B 0x712a4
> -#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
> -#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
> -#define PLANE_OFFSET(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
> -
> -#define _PLANE_KEYVAL_1_B 0x71194
> -#define _PLANE_KEYVAL_2_B 0x71294
> -#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
> -#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
> -#define PLANE_KEYVAL(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
> -
> -#define _PLANE_KEYMSK_1_B 0x71198
> -#define _PLANE_KEYMSK_2_B 0x71298
> -#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
> -#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
> -#define PLANE_KEYMSK(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
> -
> -#define _PLANE_KEYMAX_1_B 0x711a0
> -#define _PLANE_KEYMAX_2_B 0x712a0
> -#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
> -#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
> -#define PLANE_KEYMAX(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
> -
> -#define _PLANE_SURFLIVE_1_B 0x711ac
> -#define _PLANE_SURFLIVE_2_B 0x712ac
> -#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B)
> -#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
> -#define PLANE_SURFLIVE(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
> -
> -#define _PLANE_CHICKEN_1_B 0x7126c
> -#define _PLANE_CHICKEN_2_B 0x7136c
> -#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B)
> -#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
> -#define PLANE_CHICKEN(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
> -
> -#define _PLANE_AUX_DIST_1_B 0x711c0
> -#define _PLANE_AUX_DIST_2_B 0x712c0
> -#define _PLANE_AUX_DIST_1(pipe) \
> - _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
> -#define _PLANE_AUX_DIST_2(pipe) \
> - _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
> -#define PLANE_AUX_DIST(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
> -
> -#define _PLANE_AUX_OFFSET_1_B 0x711c4
> -#define _PLANE_AUX_OFFSET_2_B 0x712c4
> -#define _PLANE_AUX_OFFSET_1(pipe) \
> - _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
> -#define _PLANE_AUX_OFFSET_2(pipe) \
> - _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
> -#define PLANE_AUX_OFFSET(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
> -
> -#define _PLANE_CUS_CTL_1_B 0x711c8
> -#define _PLANE_CUS_CTL_2_B 0x712c8
> -#define _PLANE_CUS_CTL_1(pipe) \
> - _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
> -#define _PLANE_CUS_CTL_2(pipe) \
> - _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
> -#define PLANE_CUS_CTL(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
> -
> -#define _PLANE_COLOR_CTL_1_B 0x711CC
> -#define _PLANE_COLOR_CTL_2_B 0x712CC
> -#define _PLANE_COLOR_CTL_3_B 0x713CC
> -#define _PLANE_COLOR_CTL_1(pipe) \
> - _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
> -#define _PLANE_COLOR_CTL_2(pipe) \
> - _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
> -#define PLANE_COLOR_CTL(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
>
> /* VBIOS regs */
> #define VGACNTRL _MMIO(0x71400)
> @@ -5151,49 +4799,6 @@ enum skl_power_gate {
> #define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
> #define WM_DBG_DISALLOW_SPRITE (1 << 2)
>
> -/* Plane CSC Registers */
> -#define _PLANE_CSC_RY_GY_1_A 0x70210
> -#define _PLANE_CSC_RY_GY_2_A 0x70310
> -
> -#define _PLANE_CSC_RY_GY_1_B 0x71210
> -#define _PLANE_CSC_RY_GY_2_B 0x71310
> -
> -#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
> - _PLANE_CSC_RY_GY_1_B)
> -#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, \
> - _PLANE_CSC_RY_GY_2_B)
> -#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
> - _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
> - _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
> -
> -#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
> -#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
> -
> -#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
> -#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
> -
> -#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
> - _PLANE_CSC_PREOFF_HI_1_B)
> -#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
> - _PLANE_CSC_PREOFF_HI_2_B)
> -#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
> - (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
> - (index) * 4)
> -
> -#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
> -#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
> -
> -#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
> -#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
> -
> -#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
> - _PLANE_CSC_POSTOFF_HI_1_B)
> -#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
> - _PLANE_CSC_POSTOFF_HI_2_B)
> -#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
> - (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
> - (index) * 4)
> -
> /* Gen4+ Timestamp and Pipe Frame time stamp registers */
> #define GEN4_TIMESTAMP _MMIO(0x2358)
> #define ILK_TIMESTAMP_HI _MMIO(0x70070)
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index e1a35f70b544..178eba121881 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -16,6 +16,7 @@
> #include "display/intel_lvds_regs.h"
> #include "display/intel_psr_regs.h"
> #include "display/intel_sprite_regs.h"
> +#include "display/skl_universal_plane_regs.h"
> #include "display/skl_watermark_regs.h"
> #include "display/vlv_dsi_pll_regs.h"
> #include "gt/intel_engine_regs.h"
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 03/16] drm/i915: Extract intel_cursor_regs.h
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
2024-05-10 15:23 ` [PATCH 01/16] drm/i915: Nuke _MMIO_PLANE_GAMC() Ville Syrjala
2024-05-10 15:23 ` [PATCH 02/16] drm/i915: Extract skl_universal_plane_regs.h Ville Syrjala
@ 2024-05-10 15:23 ` Ville Syrjala
2024-05-13 10:10 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 04/16] drm/i915: Move skl+ wm/ddb registers to proper headers Ville Syrjala
` (18 subsequent siblings)
21 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2024-05-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Zhenyu Wang, Zhi Wang
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move most cursor register definitions into their own file.
Declutters i915_reg.h a bit more.
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
CC: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cursor.c | 1 +
.../gpu/drm/i915/display/intel_cursor_regs.h | 78 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 1 +
drivers/gpu/drm/i915/gvt/display.c | 1 +
drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 70 -----------------
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
8 files changed, 84 insertions(+), 70 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_cursor_regs.h
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 2118b87ccb10..d2b459634732 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -14,6 +14,7 @@
#include "intel_atomic.h"
#include "intel_atomic_plane.h"
#include "intel_cursor.h"
+#include "intel_cursor_regs.h"
#include "intel_de.h"
#include "intel_display.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
new file mode 100644
index 000000000000..62f7fb5c3f10
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __INTEL_CURSOR_REGS_H__
+#define __INTEL_CURSOR_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _CURACNTR 0x70080
+/* Old style CUR*CNTR flags (desktop 8xx) */
+#define CURSOR_ENABLE REG_BIT(31)
+#define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define CURSOR_STRIDE_MASK REG_GENMASK(29, 28)
+#define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */
+#define CURSOR_FORMAT_MASK REG_GENMASK(26, 24)
+#define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0)
+#define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1)
+#define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2)
+#define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4)
+#define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5)
+/* New style CUR*CNTR flags */
+#define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
+#define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */
+#define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28)
+#define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe))
+#define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26)
+#define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
+#define MCURSOR_ROTATE_180 REG_BIT(15)
+#define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14)
+#define MCURSOR_MODE_MASK 0x27
+#define MCURSOR_MODE_DISABLE 0x00
+#define MCURSOR_MODE_128_32B_AX 0x02
+#define MCURSOR_MODE_256_32B_AX 0x03
+#define MCURSOR_MODE_64_2B 0x04
+#define MCURSOR_MODE_64_32B_AX 0x07
+#define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX)
+#define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX)
+#define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX)
+#define _CURABASE 0x70084
+#define _CURAPOS 0x70088
+#define _CURAPOS_ERLY_TPT 0x7008c
+#define CURSOR_POS_Y_SIGN REG_BIT(31)
+#define CURSOR_POS_Y_MASK REG_GENMASK(30, 16)
+#define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))
+#define CURSOR_POS_X_SIGN REG_BIT(15)
+#define CURSOR_POS_X_MASK REG_GENMASK(14, 0)
+#define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))
+#define _CURASIZE 0x700a0 /* 845/865 */
+#define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12)
+#define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))
+#define CURSOR_WIDTH_MASK REG_GENMASK(9, 0)
+#define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))
+#define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
+#define CUR_FBC_EN REG_BIT(31)
+#define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0)
+#define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))
+#define _CUR_CHICKEN_A 0x700a4 /* mtl+ */
+#define _CURASURFLIVE 0x700ac /* g4x+ */
+#define _CURBCNTR 0x700c0
+#define _CURBBASE 0x700c4
+#define _CURBPOS 0x700c8
+
+#define _CURBCNTR_IVB 0x71080
+#define _CURBBASE_IVB 0x71084
+#define _CURBPOS_IVB 0x71088
+
+#define CURCNTR(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR)
+#define CURBASE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE)
+#define CURPOS(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS)
+#define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT)
+#define CURSIZE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE)
+#define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A)
+#define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A)
+#define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE)
+
+#endif /* __INTEL_CURSOR_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a2c331c696fe..839643c07566 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -65,6 +65,7 @@
#include "intel_crt.h"
#include "intel_crtc.h"
#include "intel_crtc_state_dump.h"
+#include "intel_cursor_regs.h"
#include "intel_ddi.h"
#include "intel_de.h"
#include "intel_display_driver.h"
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 595eb1b3b6c6..8cb12e7b157c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -29,6 +29,7 @@
#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_crtc.h"
+#include "intel_cursor_regs.h"
#include "intel_ddi.h"
#include "intel_de.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 2b7df7fcf369..527e0bb2b15e 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -37,6 +37,7 @@
#include "gvt.h"
#include "display/bxt_dpio_phy_regs.h"
+#include "display/intel_cursor_regs.h"
#include "display/intel_display.h"
#include "display/intel_dpio_phy.h"
#include "display/intel_sprite_regs.h"
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index dd6eb0ae003a..ac3ec9d1ef5f 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -40,6 +40,7 @@
#include "i915_pvinfo.h"
#include "i915_reg.h"
+#include "display/intel_cursor_regs.h"
#include "display/intel_sprite_regs.h"
#include "display/skl_universal_plane_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 08725dc7883e..52b029cd3981 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1762,8 +1762,6 @@
#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
-/* Display & cursor control */
-
/* Pipe A */
#define _PIPEADSL 0x70000
#define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
@@ -2266,74 +2264,6 @@
#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)
#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X)
-/* Cursor A & B regs */
-#define _CURACNTR 0x70080
-/* Old style CUR*CNTR flags (desktop 8xx) */
-#define CURSOR_ENABLE REG_BIT(31)
-#define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
-#define CURSOR_STRIDE_MASK REG_GENMASK(29, 28)
-#define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */
-#define CURSOR_FORMAT_MASK REG_GENMASK(26, 24)
-#define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0)
-#define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1)
-#define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2)
-#define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4)
-#define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5)
-/* New style CUR*CNTR flags */
-#define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
-#define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */
-#define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28)
-#define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe))
-#define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26)
-#define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
-#define MCURSOR_ROTATE_180 REG_BIT(15)
-#define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14)
-#define MCURSOR_MODE_MASK 0x27
-#define MCURSOR_MODE_DISABLE 0x00
-#define MCURSOR_MODE_128_32B_AX 0x02
-#define MCURSOR_MODE_256_32B_AX 0x03
-#define MCURSOR_MODE_64_2B 0x04
-#define MCURSOR_MODE_64_32B_AX 0x07
-#define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX)
-#define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX)
-#define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX)
-#define _CURABASE 0x70084
-#define _CURAPOS 0x70088
-#define _CURAPOS_ERLY_TPT 0x7008c
-#define CURSOR_POS_Y_SIGN REG_BIT(31)
-#define CURSOR_POS_Y_MASK REG_GENMASK(30, 16)
-#define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))
-#define CURSOR_POS_X_SIGN REG_BIT(15)
-#define CURSOR_POS_X_MASK REG_GENMASK(14, 0)
-#define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))
-#define _CURASIZE 0x700a0 /* 845/865 */
-#define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12)
-#define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))
-#define CURSOR_WIDTH_MASK REG_GENMASK(9, 0)
-#define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))
-#define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
-#define CUR_FBC_EN REG_BIT(31)
-#define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0)
-#define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))
-#define _CUR_CHICKEN_A 0x700a4 /* mtl+ */
-#define _CURASURFLIVE 0x700ac /* g4x+ */
-#define _CURBCNTR 0x700c0
-#define _CURBBASE 0x700c4
-#define _CURBPOS 0x700c8
-
-#define _CURBCNTR_IVB 0x71080
-#define _CURBBASE_IVB 0x71084
-#define _CURBPOS_IVB 0x71088
-
-#define CURCNTR(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR)
-#define CURBASE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE)
-#define CURPOS(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS)
-#define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT)
-#define CURSIZE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE)
-#define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A)
-#define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A)
-#define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE)
-
/* Display A control */
#define _DSPAADDR_VLV 0x7017C /* vlv/chv */
#define _DSPACNTR 0x70180
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 178eba121881..3b79c1c84b79 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -7,6 +7,7 @@
#include "display/intel_audio_regs.h"
#include "display/intel_backlight_regs.h"
#include "display/intel_color_regs.h"
+#include "display/intel_cursor_regs.h"
#include "display/intel_display_types.h"
#include "display/intel_dmc_regs.h"
#include "display/intel_dp_aux_regs.h"
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 03/16] drm/i915: Extract intel_cursor_regs.h
2024-05-10 15:23 ` [PATCH 03/16] drm/i915: Extract intel_cursor_regs.h Ville Syrjala
@ 2024-05-13 10:10 ` Jani Nikula
0 siblings, 0 replies; 48+ messages in thread
From: Jani Nikula @ 2024-05-13 10:10 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: Zhenyu Wang, Zhi Wang
On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move most cursor register definitions into their own file.
> Declutters i915_reg.h a bit more.
>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> CC: Zhi Wang <zhi.wang.linux@gmail.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cursor.c | 1 +
> .../gpu/drm/i915/display/intel_cursor_regs.h | 78 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 1 +
> drivers/gpu/drm/i915/gvt/display.c | 1 +
> drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 70 -----------------
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
> 8 files changed, 84 insertions(+), 70 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_cursor_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index 2118b87ccb10..d2b459634732 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -14,6 +14,7 @@
> #include "intel_atomic.h"
> #include "intel_atomic_plane.h"
> #include "intel_cursor.h"
> +#include "intel_cursor_regs.h"
> #include "intel_de.h"
> #include "intel_display.h"
> #include "intel_display_types.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> new file mode 100644
> index 000000000000..62f7fb5c3f10
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> @@ -0,0 +1,78 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +#ifndef __INTEL_CURSOR_REGS_H__
> +#define __INTEL_CURSOR_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +#define _CURACNTR 0x70080
> +/* Old style CUR*CNTR flags (desktop 8xx) */
> +#define CURSOR_ENABLE REG_BIT(31)
> +#define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
> +#define CURSOR_STRIDE_MASK REG_GENMASK(29, 28)
> +#define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */
> +#define CURSOR_FORMAT_MASK REG_GENMASK(26, 24)
> +#define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0)
> +#define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1)
> +#define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2)
> +#define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4)
> +#define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5)
> +/* New style CUR*CNTR flags */
> +#define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
> +#define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */
> +#define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28)
> +#define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe))
> +#define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26)
> +#define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
> +#define MCURSOR_ROTATE_180 REG_BIT(15)
> +#define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14)
> +#define MCURSOR_MODE_MASK 0x27
> +#define MCURSOR_MODE_DISABLE 0x00
> +#define MCURSOR_MODE_128_32B_AX 0x02
> +#define MCURSOR_MODE_256_32B_AX 0x03
> +#define MCURSOR_MODE_64_2B 0x04
> +#define MCURSOR_MODE_64_32B_AX 0x07
> +#define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX)
> +#define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX)
> +#define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX)
> +#define _CURABASE 0x70084
> +#define _CURAPOS 0x70088
> +#define _CURAPOS_ERLY_TPT 0x7008c
> +#define CURSOR_POS_Y_SIGN REG_BIT(31)
> +#define CURSOR_POS_Y_MASK REG_GENMASK(30, 16)
> +#define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))
> +#define CURSOR_POS_X_SIGN REG_BIT(15)
> +#define CURSOR_POS_X_MASK REG_GENMASK(14, 0)
> +#define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))
> +#define _CURASIZE 0x700a0 /* 845/865 */
> +#define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12)
> +#define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))
> +#define CURSOR_WIDTH_MASK REG_GENMASK(9, 0)
> +#define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))
> +#define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
> +#define CUR_FBC_EN REG_BIT(31)
> +#define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0)
> +#define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))
> +#define _CUR_CHICKEN_A 0x700a4 /* mtl+ */
> +#define _CURASURFLIVE 0x700ac /* g4x+ */
> +#define _CURBCNTR 0x700c0
> +#define _CURBBASE 0x700c4
> +#define _CURBPOS 0x700c8
> +
> +#define _CURBCNTR_IVB 0x71080
> +#define _CURBBASE_IVB 0x71084
> +#define _CURBPOS_IVB 0x71088
> +
> +#define CURCNTR(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR)
> +#define CURBASE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE)
> +#define CURPOS(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS)
> +#define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT)
> +#define CURSIZE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE)
> +#define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A)
> +#define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A)
> +#define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE)
> +
> +#endif /* __INTEL_CURSOR_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a2c331c696fe..839643c07566 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -65,6 +65,7 @@
> #include "intel_crt.h"
> #include "intel_crtc.h"
> #include "intel_crtc_state_dump.h"
> +#include "intel_cursor_regs.h"
> #include "intel_ddi.h"
> #include "intel_de.h"
> #include "intel_display_driver.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 595eb1b3b6c6..8cb12e7b157c 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -29,6 +29,7 @@
> #include "i915_reg.h"
> #include "intel_atomic.h"
> #include "intel_crtc.h"
> +#include "intel_cursor_regs.h"
> #include "intel_ddi.h"
> #include "intel_de.h"
> #include "intel_display_types.h"
> diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
> index 2b7df7fcf369..527e0bb2b15e 100644
> --- a/drivers/gpu/drm/i915/gvt/display.c
> +++ b/drivers/gpu/drm/i915/gvt/display.c
> @@ -37,6 +37,7 @@
> #include "gvt.h"
>
> #include "display/bxt_dpio_phy_regs.h"
> +#include "display/intel_cursor_regs.h"
> #include "display/intel_display.h"
> #include "display/intel_dpio_phy.h"
> #include "display/intel_sprite_regs.h"
> diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> index dd6eb0ae003a..ac3ec9d1ef5f 100644
> --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
> +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> @@ -40,6 +40,7 @@
> #include "i915_pvinfo.h"
> #include "i915_reg.h"
>
> +#include "display/intel_cursor_regs.h"
> #include "display/intel_sprite_regs.h"
> #include "display/skl_universal_plane_regs.h"
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 08725dc7883e..52b029cd3981 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1762,8 +1762,6 @@
> #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
> #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
>
> -/* Display & cursor control */
> -
> /* Pipe A */
> #define _PIPEADSL 0x70000
> #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
> @@ -2266,74 +2264,6 @@
> #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)
> #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X)
>
> -/* Cursor A & B regs */
> -#define _CURACNTR 0x70080
> -/* Old style CUR*CNTR flags (desktop 8xx) */
> -#define CURSOR_ENABLE REG_BIT(31)
> -#define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
> -#define CURSOR_STRIDE_MASK REG_GENMASK(29, 28)
> -#define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */
> -#define CURSOR_FORMAT_MASK REG_GENMASK(26, 24)
> -#define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0)
> -#define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1)
> -#define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2)
> -#define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4)
> -#define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5)
> -/* New style CUR*CNTR flags */
> -#define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
> -#define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */
> -#define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28)
> -#define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe))
> -#define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26)
> -#define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
> -#define MCURSOR_ROTATE_180 REG_BIT(15)
> -#define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14)
> -#define MCURSOR_MODE_MASK 0x27
> -#define MCURSOR_MODE_DISABLE 0x00
> -#define MCURSOR_MODE_128_32B_AX 0x02
> -#define MCURSOR_MODE_256_32B_AX 0x03
> -#define MCURSOR_MODE_64_2B 0x04
> -#define MCURSOR_MODE_64_32B_AX 0x07
> -#define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX)
> -#define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX)
> -#define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX)
> -#define _CURABASE 0x70084
> -#define _CURAPOS 0x70088
> -#define _CURAPOS_ERLY_TPT 0x7008c
> -#define CURSOR_POS_Y_SIGN REG_BIT(31)
> -#define CURSOR_POS_Y_MASK REG_GENMASK(30, 16)
> -#define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))
> -#define CURSOR_POS_X_SIGN REG_BIT(15)
> -#define CURSOR_POS_X_MASK REG_GENMASK(14, 0)
> -#define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))
> -#define _CURASIZE 0x700a0 /* 845/865 */
> -#define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12)
> -#define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))
> -#define CURSOR_WIDTH_MASK REG_GENMASK(9, 0)
> -#define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))
> -#define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
> -#define CUR_FBC_EN REG_BIT(31)
> -#define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0)
> -#define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))
> -#define _CUR_CHICKEN_A 0x700a4 /* mtl+ */
> -#define _CURASURFLIVE 0x700ac /* g4x+ */
> -#define _CURBCNTR 0x700c0
> -#define _CURBBASE 0x700c4
> -#define _CURBPOS 0x700c8
> -
> -#define _CURBCNTR_IVB 0x71080
> -#define _CURBBASE_IVB 0x71084
> -#define _CURBPOS_IVB 0x71088
> -
> -#define CURCNTR(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR)
> -#define CURBASE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE)
> -#define CURPOS(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS)
> -#define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT)
> -#define CURSIZE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE)
> -#define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A)
> -#define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A)
> -#define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE)
> -
> /* Display A control */
> #define _DSPAADDR_VLV 0x7017C /* vlv/chv */
> #define _DSPACNTR 0x70180
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 178eba121881..3b79c1c84b79 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -7,6 +7,7 @@
> #include "display/intel_audio_regs.h"
> #include "display/intel_backlight_regs.h"
> #include "display/intel_color_regs.h"
> +#include "display/intel_cursor_regs.h"
> #include "display/intel_display_types.h"
> #include "display/intel_dmc_regs.h"
> #include "display/intel_dp_aux_regs.h"
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 04/16] drm/i915: Move skl+ wm/ddb registers to proper headers
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
` (2 preceding siblings ...)
2024-05-10 15:23 ` [PATCH 03/16] drm/i915: Extract intel_cursor_regs.h Ville Syrjala
@ 2024-05-10 15:23 ` Ville Syrjala
2024-05-13 10:13 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 05/16] drm/i915/gvt: Use the proper PLANE_AUX_DIST() define Ville Syrjala
` (17 subsequent siblings)
21 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2024-05-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Zhenyu Wang, Zhi Wang
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
On SKL+ the watermark/DDB registers are proper per-plane
registers. Move the definitons to their respective files.
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
CC: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../gpu/drm/i915/display/intel_cursor_regs.h | 20 +++++
.../i915/display/skl_universal_plane_regs.h | 64 ++++++++++++++
drivers/gpu/drm/i915/display/skl_watermark.c | 1 +
.../gpu/drm/i915/display/skl_watermark_regs.h | 83 -------------------
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
5 files changed, 86 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index 62f7fb5c3f10..a478ef5787c5 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -75,4 +75,24 @@
#define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A)
#define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE)
+/* skl+ */
+#define _CUR_WM_A_0 0x70140
+#define _CUR_WM_B_0 0x71140
+#define _CUR_WM_SAGV_A 0x70158
+#define _CUR_WM_SAGV_B 0x71158
+#define _CUR_WM_SAGV_TRANS_A 0x7015C
+#define _CUR_WM_SAGV_TRANS_B 0x7115C
+#define _CUR_WM_TRANS_A 0x70168
+#define _CUR_WM_TRANS_B 0x71168
+#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
+#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
+#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
+#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
+#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
+
+/* skl+ */
+#define _CUR_BUF_CFG_A 0x7017c
+#define _CUR_BUF_CFG_B 0x7117c
+#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
+
#endif /* __INTEL_CURSOR_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 7e34470beb74..2222d0c760e8 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -402,4 +402,68 @@
(index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
(index) * 4)
+#define _PLANE_WM_1_A_0 0x70240
+#define _PLANE_WM_1_B_0 0x71240
+#define _PLANE_WM_2_A_0 0x70340
+#define _PLANE_WM_2_B_0 0x71340
+#define _PLANE_WM_SAGV_1_A 0x70258
+#define _PLANE_WM_SAGV_1_B 0x71258
+#define _PLANE_WM_SAGV_2_A 0x70358
+#define _PLANE_WM_SAGV_2_B 0x71358
+#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C
+#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C
+#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C
+#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C
+#define _PLANE_WM_TRANS_1_A 0x70268
+#define _PLANE_WM_TRANS_1_B 0x71268
+#define _PLANE_WM_TRANS_2_A 0x70368
+#define _PLANE_WM_TRANS_2_B 0x71368
+#define PLANE_WM_EN (1 << 31)
+#define PLANE_WM_IGNORE_LINES (1 << 30)
+#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
+#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
+
+#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
+#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
+#define _PLANE_WM_BASE(pipe, plane) \
+ _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
+#define PLANE_WM(pipe, plane, level) \
+ _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
+#define _PLANE_WM_SAGV_1(pipe) \
+ _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
+#define _PLANE_WM_SAGV_2(pipe) \
+ _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
+#define PLANE_WM_SAGV(pipe, plane) \
+ _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
+#define _PLANE_WM_SAGV_TRANS_1(pipe) \
+ _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
+#define _PLANE_WM_SAGV_TRANS_2(pipe) \
+ _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
+#define PLANE_WM_SAGV_TRANS(pipe, plane) \
+ _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
+#define _PLANE_WM_TRANS_1(pipe) \
+ _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
+#define _PLANE_WM_TRANS_2(pipe) \
+ _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
+#define PLANE_WM_TRANS(pipe, plane) \
+ _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
+
+#define _PLANE_BUF_CFG_1_B 0x7127c
+#define _PLANE_BUF_CFG_2_B 0x7137c
+#define _PLANE_BUF_CFG_1(pipe) \
+ _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
+#define _PLANE_BUF_CFG_2(pipe) \
+ _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
+#define PLANE_BUF_CFG(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
+
+#define _PLANE_NV12_BUF_CFG_1_B 0x71278
+#define _PLANE_NV12_BUF_CFG_2_B 0x71378
+#define _PLANE_NV12_BUF_CFG_1(pipe) \
+ _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
+#define _PLANE_NV12_BUF_CFG_2(pipe) \
+ _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
+#define PLANE_NV12_BUF_CFG(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
+
#endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 53a565c673e2..2a2073bf3aca 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -13,6 +13,7 @@
#include "intel_bw.h"
#include "intel_cdclk.h"
#include "intel_crtc.h"
+#include "intel_cursor_regs.h"
#include "intel_de.h"
#include "intel_display.h"
#include "intel_display_power.h"
diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
index 269163fa3350..c5572fc0e847 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
@@ -43,89 +43,6 @@
#define MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(15, 13)
#define MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
-/* Watermark register definitions for SKL */
-#define _CUR_WM_A_0 0x70140
-#define _CUR_WM_B_0 0x71140
-#define _CUR_WM_SAGV_A 0x70158
-#define _CUR_WM_SAGV_B 0x71158
-#define _CUR_WM_SAGV_TRANS_A 0x7015C
-#define _CUR_WM_SAGV_TRANS_B 0x7115C
-#define _CUR_WM_TRANS_A 0x70168
-#define _CUR_WM_TRANS_B 0x71168
-#define _PLANE_WM_1_A_0 0x70240
-#define _PLANE_WM_1_B_0 0x71240
-#define _PLANE_WM_2_A_0 0x70340
-#define _PLANE_WM_2_B_0 0x71340
-#define _PLANE_WM_SAGV_1_A 0x70258
-#define _PLANE_WM_SAGV_1_B 0x71258
-#define _PLANE_WM_SAGV_2_A 0x70358
-#define _PLANE_WM_SAGV_2_B 0x71358
-#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C
-#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C
-#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C
-#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C
-#define _PLANE_WM_TRANS_1_A 0x70268
-#define _PLANE_WM_TRANS_1_B 0x71268
-#define _PLANE_WM_TRANS_2_A 0x70368
-#define _PLANE_WM_TRANS_2_B 0x71368
-#define PLANE_WM_EN (1 << 31)
-#define PLANE_WM_IGNORE_LINES (1 << 30)
-#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
-#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
-
-#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
-#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
-#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
-#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
-#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
-#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
-#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
-#define _PLANE_WM_BASE(pipe, plane) \
- _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
-#define PLANE_WM(pipe, plane, level) \
- _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
-#define _PLANE_WM_SAGV_1(pipe) \
- _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
-#define _PLANE_WM_SAGV_2(pipe) \
- _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
-#define PLANE_WM_SAGV(pipe, plane) \
- _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
-#define _PLANE_WM_SAGV_TRANS_1(pipe) \
- _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
-#define _PLANE_WM_SAGV_TRANS_2(pipe) \
- _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
-#define PLANE_WM_SAGV_TRANS(pipe, plane) \
- _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
-#define _PLANE_WM_TRANS_1(pipe) \
- _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
-#define _PLANE_WM_TRANS_2(pipe) \
- _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
-#define PLANE_WM_TRANS(pipe, plane) \
- _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
-
-#define _PLANE_BUF_CFG_1_B 0x7127c
-#define _PLANE_BUF_CFG_2_B 0x7137c
-#define _PLANE_BUF_CFG_1(pipe) \
- _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
-#define _PLANE_BUF_CFG_2(pipe) \
- _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
-#define PLANE_BUF_CFG(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
-
-#define _PLANE_NV12_BUF_CFG_1_B 0x71278
-#define _PLANE_NV12_BUF_CFG_2_B 0x71378
-#define _PLANE_NV12_BUF_CFG_1(pipe) \
- _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
-#define _PLANE_NV12_BUF_CFG_2(pipe) \
- _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
-#define PLANE_NV12_BUF_CFG(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
-
-/* SKL new cursor registers */
-#define _CUR_BUF_CFG_A 0x7017c
-#define _CUR_BUF_CFG_B 0x7117c
-#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
-
/*
* The below are numbered starting from "S1" on gen11/gen12, but starting
* with display 13, the bspec switches to a 0-based numbering scheme
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index aae0443015f0..6c857beb5083 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -42,6 +42,7 @@
#include "i915_pvinfo.h"
#include "intel_mchbar_regs.h"
#include "display/bxt_dpio_phy_regs.h"
+#include "display/intel_cursor_regs.h"
#include "display/intel_display_types.h"
#include "display/intel_dmc_regs.h"
#include "display/intel_dp_aux_regs.h"
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 04/16] drm/i915: Move skl+ wm/ddb registers to proper headers
2024-05-10 15:23 ` [PATCH 04/16] drm/i915: Move skl+ wm/ddb registers to proper headers Ville Syrjala
@ 2024-05-13 10:13 ` Jani Nikula
0 siblings, 0 replies; 48+ messages in thread
From: Jani Nikula @ 2024-05-13 10:13 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: Zhenyu Wang, Zhi Wang
On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On SKL+ the watermark/DDB registers are proper per-plane
> registers. Move the definitons to their respective files.
>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> CC: Zhi Wang <zhi.wang.linux@gmail.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/intel_cursor_regs.h | 20 +++++
> .../i915/display/skl_universal_plane_regs.h | 64 ++++++++++++++
> drivers/gpu/drm/i915/display/skl_watermark.c | 1 +
> .../gpu/drm/i915/display/skl_watermark_regs.h | 83 -------------------
> drivers/gpu/drm/i915/gvt/handlers.c | 1 +
> 5 files changed, 86 insertions(+), 83 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> index 62f7fb5c3f10..a478ef5787c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> @@ -75,4 +75,24 @@
> #define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A)
> #define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE)
>
> +/* skl+ */
> +#define _CUR_WM_A_0 0x70140
> +#define _CUR_WM_B_0 0x71140
> +#define _CUR_WM_SAGV_A 0x70158
> +#define _CUR_WM_SAGV_B 0x71158
> +#define _CUR_WM_SAGV_TRANS_A 0x7015C
> +#define _CUR_WM_SAGV_TRANS_B 0x7115C
> +#define _CUR_WM_TRANS_A 0x70168
> +#define _CUR_WM_TRANS_B 0x71168
> +#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
> +#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
> +#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
> +#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
> +#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
> +
> +/* skl+ */
> +#define _CUR_BUF_CFG_A 0x7017c
> +#define _CUR_BUF_CFG_B 0x7117c
> +#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
> +
> #endif /* __INTEL_CURSOR_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> index 7e34470beb74..2222d0c760e8 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> @@ -402,4 +402,68 @@
> (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
> (index) * 4)
>
> +#define _PLANE_WM_1_A_0 0x70240
> +#define _PLANE_WM_1_B_0 0x71240
> +#define _PLANE_WM_2_A_0 0x70340
> +#define _PLANE_WM_2_B_0 0x71340
> +#define _PLANE_WM_SAGV_1_A 0x70258
> +#define _PLANE_WM_SAGV_1_B 0x71258
> +#define _PLANE_WM_SAGV_2_A 0x70358
> +#define _PLANE_WM_SAGV_2_B 0x71358
> +#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C
> +#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C
> +#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C
> +#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C
> +#define _PLANE_WM_TRANS_1_A 0x70268
> +#define _PLANE_WM_TRANS_1_B 0x71268
> +#define _PLANE_WM_TRANS_2_A 0x70368
> +#define _PLANE_WM_TRANS_2_B 0x71368
> +#define PLANE_WM_EN (1 << 31)
> +#define PLANE_WM_IGNORE_LINES (1 << 30)
> +#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
> +#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
> +
> +#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
> +#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
> +#define _PLANE_WM_BASE(pipe, plane) \
> + _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
> +#define PLANE_WM(pipe, plane, level) \
> + _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
> +#define _PLANE_WM_SAGV_1(pipe) \
> + _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
> +#define _PLANE_WM_SAGV_2(pipe) \
> + _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
> +#define PLANE_WM_SAGV(pipe, plane) \
> + _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
> +#define _PLANE_WM_SAGV_TRANS_1(pipe) \
> + _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
> +#define _PLANE_WM_SAGV_TRANS_2(pipe) \
> + _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
> +#define PLANE_WM_SAGV_TRANS(pipe, plane) \
> + _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
> +#define _PLANE_WM_TRANS_1(pipe) \
> + _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
> +#define _PLANE_WM_TRANS_2(pipe) \
> + _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
> +#define PLANE_WM_TRANS(pipe, plane) \
> + _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
> +
> +#define _PLANE_BUF_CFG_1_B 0x7127c
> +#define _PLANE_BUF_CFG_2_B 0x7137c
> +#define _PLANE_BUF_CFG_1(pipe) \
> + _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
> +#define _PLANE_BUF_CFG_2(pipe) \
> + _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
> +#define PLANE_BUF_CFG(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
> +
> +#define _PLANE_NV12_BUF_CFG_1_B 0x71278
> +#define _PLANE_NV12_BUF_CFG_2_B 0x71378
> +#define _PLANE_NV12_BUF_CFG_1(pipe) \
> + _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
> +#define _PLANE_NV12_BUF_CFG_2(pipe) \
> + _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
> +#define PLANE_NV12_BUF_CFG(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
> +
> #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 53a565c673e2..2a2073bf3aca 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -13,6 +13,7 @@
> #include "intel_bw.h"
> #include "intel_cdclk.h"
> #include "intel_crtc.h"
> +#include "intel_cursor_regs.h"
> #include "intel_de.h"
> #include "intel_display.h"
> #include "intel_display_power.h"
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> index 269163fa3350..c5572fc0e847 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> @@ -43,89 +43,6 @@
> #define MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(15, 13)
> #define MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
>
> -/* Watermark register definitions for SKL */
> -#define _CUR_WM_A_0 0x70140
> -#define _CUR_WM_B_0 0x71140
> -#define _CUR_WM_SAGV_A 0x70158
> -#define _CUR_WM_SAGV_B 0x71158
> -#define _CUR_WM_SAGV_TRANS_A 0x7015C
> -#define _CUR_WM_SAGV_TRANS_B 0x7115C
> -#define _CUR_WM_TRANS_A 0x70168
> -#define _CUR_WM_TRANS_B 0x71168
> -#define _PLANE_WM_1_A_0 0x70240
> -#define _PLANE_WM_1_B_0 0x71240
> -#define _PLANE_WM_2_A_0 0x70340
> -#define _PLANE_WM_2_B_0 0x71340
> -#define _PLANE_WM_SAGV_1_A 0x70258
> -#define _PLANE_WM_SAGV_1_B 0x71258
> -#define _PLANE_WM_SAGV_2_A 0x70358
> -#define _PLANE_WM_SAGV_2_B 0x71358
> -#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C
> -#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C
> -#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C
> -#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C
> -#define _PLANE_WM_TRANS_1_A 0x70268
> -#define _PLANE_WM_TRANS_1_B 0x71268
> -#define _PLANE_WM_TRANS_2_A 0x70368
> -#define _PLANE_WM_TRANS_2_B 0x71368
> -#define PLANE_WM_EN (1 << 31)
> -#define PLANE_WM_IGNORE_LINES (1 << 30)
> -#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
> -#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
> -
> -#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
> -#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
> -#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
> -#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
> -#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
> -#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
> -#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
> -#define _PLANE_WM_BASE(pipe, plane) \
> - _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
> -#define PLANE_WM(pipe, plane, level) \
> - _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
> -#define _PLANE_WM_SAGV_1(pipe) \
> - _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
> -#define _PLANE_WM_SAGV_2(pipe) \
> - _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
> -#define PLANE_WM_SAGV(pipe, plane) \
> - _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
> -#define _PLANE_WM_SAGV_TRANS_1(pipe) \
> - _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
> -#define _PLANE_WM_SAGV_TRANS_2(pipe) \
> - _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
> -#define PLANE_WM_SAGV_TRANS(pipe, plane) \
> - _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
> -#define _PLANE_WM_TRANS_1(pipe) \
> - _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
> -#define _PLANE_WM_TRANS_2(pipe) \
> - _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
> -#define PLANE_WM_TRANS(pipe, plane) \
> - _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
> -
> -#define _PLANE_BUF_CFG_1_B 0x7127c
> -#define _PLANE_BUF_CFG_2_B 0x7137c
> -#define _PLANE_BUF_CFG_1(pipe) \
> - _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
> -#define _PLANE_BUF_CFG_2(pipe) \
> - _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
> -#define PLANE_BUF_CFG(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
> -
> -#define _PLANE_NV12_BUF_CFG_1_B 0x71278
> -#define _PLANE_NV12_BUF_CFG_2_B 0x71378
> -#define _PLANE_NV12_BUF_CFG_1(pipe) \
> - _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
> -#define _PLANE_NV12_BUF_CFG_2(pipe) \
> - _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
> -#define PLANE_NV12_BUF_CFG(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
> -
> -/* SKL new cursor registers */
> -#define _CUR_BUF_CFG_A 0x7017c
> -#define _CUR_BUF_CFG_B 0x7117c
> -#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
> -
> /*
> * The below are numbered starting from "S1" on gen11/gen12, but starting
> * with display 13, the bspec switches to a 0-based numbering scheme
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index aae0443015f0..6c857beb5083 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -42,6 +42,7 @@
> #include "i915_pvinfo.h"
> #include "intel_mchbar_regs.h"
> #include "display/bxt_dpio_phy_regs.h"
> +#include "display/intel_cursor_regs.h"
> #include "display/intel_display_types.h"
> #include "display/intel_dmc_regs.h"
> #include "display/intel_dp_aux_regs.h"
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 05/16] drm/i915/gvt: Use the proper PLANE_AUX_DIST() define
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
` (3 preceding siblings ...)
2024-05-10 15:23 ` [PATCH 04/16] drm/i915: Move skl+ wm/ddb registers to proper headers Ville Syrjala
@ 2024-05-10 15:23 ` Ville Syrjala
2024-05-13 10:21 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 06/16] drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() define Ville Syrjala
` (16 subsequent siblings)
21 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2024-05-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Zhenyu Wang, Zhi Wang
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Stop hand rolling PLANE_AUX_DIST() and just use the real thing.
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
CC: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/gvt/handlers.c | 24 ++++++++++-----------
drivers/gpu/drm/i915/gvt/reg.h | 1 -
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 24 ++++++++++-----------
3 files changed, 24 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 6c857beb5083..6b02612ddef5 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2678,20 +2678,20 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_DIST(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_DIST(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_DIST(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_DIST(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_DIST(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_DIST(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_DIST(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_DIST(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_DIST(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_DIST(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
index d8216c63c39a..e8a56faafe95 100644
--- a/drivers/gpu/drm/i915/gvt/reg.h
+++ b/drivers/gpu/drm/i915/gvt/reg.h
@@ -57,7 +57,6 @@
#define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)
-#define _REG_701C0(pipe, plane) (0x701c0 + pipe * 0x1000 + (plane - 1) * 0x100)
#define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100)
#define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe))
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 3b79c1c84b79..cf45342a6db0 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -1006,18 +1006,18 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 1));
MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 2));
MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 3));
- MMIO_D(_MMIO(_REG_701C0(PIPE_A, 1)));
- MMIO_D(_MMIO(_REG_701C0(PIPE_A, 2)));
- MMIO_D(_MMIO(_REG_701C0(PIPE_A, 3)));
- MMIO_D(_MMIO(_REG_701C0(PIPE_A, 4)));
- MMIO_D(_MMIO(_REG_701C0(PIPE_B, 1)));
- MMIO_D(_MMIO(_REG_701C0(PIPE_B, 2)));
- MMIO_D(_MMIO(_REG_701C0(PIPE_B, 3)));
- MMIO_D(_MMIO(_REG_701C0(PIPE_B, 4)));
- MMIO_D(_MMIO(_REG_701C0(PIPE_C, 1)));
- MMIO_D(_MMIO(_REG_701C0(PIPE_C, 2)));
- MMIO_D(_MMIO(_REG_701C0(PIPE_C, 3)));
- MMIO_D(_MMIO(_REG_701C0(PIPE_C, 4)));
+ MMIO_D(PLANE_AUX_DIST(PIPE_A, 0));
+ MMIO_D(PLANE_AUX_DIST(PIPE_A, 1));
+ MMIO_D(PLANE_AUX_DIST(PIPE_A, 2));
+ MMIO_D(PLANE_AUX_DIST(PIPE_A, 3));
+ MMIO_D(PLANE_AUX_DIST(PIPE_B, 0));
+ MMIO_D(PLANE_AUX_DIST(PIPE_B, 1));
+ MMIO_D(PLANE_AUX_DIST(PIPE_B, 2));
+ MMIO_D(PLANE_AUX_DIST(PIPE_B, 3));
+ MMIO_D(PLANE_AUX_DIST(PIPE_C, 0));
+ MMIO_D(PLANE_AUX_DIST(PIPE_C, 1));
+ MMIO_D(PLANE_AUX_DIST(PIPE_C, 2));
+ MMIO_D(PLANE_AUX_DIST(PIPE_C, 3));
MMIO_D(_MMIO(_REG_701C4(PIPE_A, 1)));
MMIO_D(_MMIO(_REG_701C4(PIPE_A, 2)));
MMIO_D(_MMIO(_REG_701C4(PIPE_A, 3)));
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 05/16] drm/i915/gvt: Use the proper PLANE_AUX_DIST() define
2024-05-10 15:23 ` [PATCH 05/16] drm/i915/gvt: Use the proper PLANE_AUX_DIST() define Ville Syrjala
@ 2024-05-13 10:21 ` Jani Nikula
0 siblings, 0 replies; 48+ messages in thread
From: Jani Nikula @ 2024-05-13 10:21 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: Zhenyu Wang, Zhi Wang
On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Stop hand rolling PLANE_AUX_DIST() and just use the real thing.
>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> CC: Zhi Wang <zhi.wang.linux@gmail.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/gvt/handlers.c | 24 ++++++++++-----------
> drivers/gpu/drm/i915/gvt/reg.h | 1 -
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 24 ++++++++++-----------
> 3 files changed, 24 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 6c857beb5083..6b02612ddef5 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2678,20 +2678,20 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
> MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_DIST(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_DIST(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_DIST(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_DIST(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_DIST(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_DIST(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_DIST(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_DIST(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_DIST(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_DIST(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>
> MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
> index d8216c63c39a..e8a56faafe95 100644
> --- a/drivers/gpu/drm/i915/gvt/reg.h
> +++ b/drivers/gpu/drm/i915/gvt/reg.h
> @@ -57,7 +57,6 @@
>
> #define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)
>
> -#define _REG_701C0(pipe, plane) (0x701c0 + pipe * 0x1000 + (plane - 1) * 0x100)
> #define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100)
>
> #define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe))
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 3b79c1c84b79..cf45342a6db0 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -1006,18 +1006,18 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter)
> MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 1));
> MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 2));
> MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 3));
> - MMIO_D(_MMIO(_REG_701C0(PIPE_A, 1)));
> - MMIO_D(_MMIO(_REG_701C0(PIPE_A, 2)));
> - MMIO_D(_MMIO(_REG_701C0(PIPE_A, 3)));
> - MMIO_D(_MMIO(_REG_701C0(PIPE_A, 4)));
> - MMIO_D(_MMIO(_REG_701C0(PIPE_B, 1)));
> - MMIO_D(_MMIO(_REG_701C0(PIPE_B, 2)));
> - MMIO_D(_MMIO(_REG_701C0(PIPE_B, 3)));
> - MMIO_D(_MMIO(_REG_701C0(PIPE_B, 4)));
> - MMIO_D(_MMIO(_REG_701C0(PIPE_C, 1)));
> - MMIO_D(_MMIO(_REG_701C0(PIPE_C, 2)));
> - MMIO_D(_MMIO(_REG_701C0(PIPE_C, 3)));
> - MMIO_D(_MMIO(_REG_701C0(PIPE_C, 4)));
> + MMIO_D(PLANE_AUX_DIST(PIPE_A, 0));
> + MMIO_D(PLANE_AUX_DIST(PIPE_A, 1));
> + MMIO_D(PLANE_AUX_DIST(PIPE_A, 2));
> + MMIO_D(PLANE_AUX_DIST(PIPE_A, 3));
> + MMIO_D(PLANE_AUX_DIST(PIPE_B, 0));
> + MMIO_D(PLANE_AUX_DIST(PIPE_B, 1));
> + MMIO_D(PLANE_AUX_DIST(PIPE_B, 2));
> + MMIO_D(PLANE_AUX_DIST(PIPE_B, 3));
> + MMIO_D(PLANE_AUX_DIST(PIPE_C, 0));
> + MMIO_D(PLANE_AUX_DIST(PIPE_C, 1));
> + MMIO_D(PLANE_AUX_DIST(PIPE_C, 2));
> + MMIO_D(PLANE_AUX_DIST(PIPE_C, 3));
> MMIO_D(_MMIO(_REG_701C4(PIPE_A, 1)));
> MMIO_D(_MMIO(_REG_701C4(PIPE_A, 2)));
> MMIO_D(_MMIO(_REG_701C4(PIPE_A, 3)));
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 06/16] drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() define
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
` (4 preceding siblings ...)
2024-05-10 15:23 ` [PATCH 05/16] drm/i915/gvt: Use the proper PLANE_AUX_DIST() define Ville Syrjala
@ 2024-05-10 15:23 ` Ville Syrjala
2024-05-13 10:23 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 07/16] drm/i915/gvt: Use the full PLANE_KEY*() defines Ville Syrjala
` (15 subsequent siblings)
21 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2024-05-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Zhenyu Wang, Zhi Wang
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Stop hand rolling PLANE_AUX_OFFSET() and just use the real thing.
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
CC: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/gvt/handlers.c | 24 ++++++++++-----------
drivers/gpu/drm/i915/gvt/reg.h | 2 --
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 24 ++++++++++-----------
3 files changed, 24 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 6b02612ddef5..6f633035618e 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2693,20 +2693,20 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
- MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
+ MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
index e8a56faafe95..90d8eb1761a3 100644
--- a/drivers/gpu/drm/i915/gvt/reg.h
+++ b/drivers/gpu/drm/i915/gvt/reg.h
@@ -57,8 +57,6 @@
#define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)
-#define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100)
-
#define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe))
#define REG50080_FLIP_TYPE_MASK 0x3
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index cf45342a6db0..ad3bf60855bc 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -1018,18 +1018,18 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(PLANE_AUX_DIST(PIPE_C, 1));
MMIO_D(PLANE_AUX_DIST(PIPE_C, 2));
MMIO_D(PLANE_AUX_DIST(PIPE_C, 3));
- MMIO_D(_MMIO(_REG_701C4(PIPE_A, 1)));
- MMIO_D(_MMIO(_REG_701C4(PIPE_A, 2)));
- MMIO_D(_MMIO(_REG_701C4(PIPE_A, 3)));
- MMIO_D(_MMIO(_REG_701C4(PIPE_A, 4)));
- MMIO_D(_MMIO(_REG_701C4(PIPE_B, 1)));
- MMIO_D(_MMIO(_REG_701C4(PIPE_B, 2)));
- MMIO_D(_MMIO(_REG_701C4(PIPE_B, 3)));
- MMIO_D(_MMIO(_REG_701C4(PIPE_B, 4)));
- MMIO_D(_MMIO(_REG_701C4(PIPE_C, 1)));
- MMIO_D(_MMIO(_REG_701C4(PIPE_C, 2)));
- MMIO_D(_MMIO(_REG_701C4(PIPE_C, 3)));
- MMIO_D(_MMIO(_REG_701C4(PIPE_C, 4)));
+ MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 0));
+ MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 1));
+ MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 2));
+ MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 3));
+ MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 0));
+ MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 1));
+ MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 2));
+ MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 3));
+ MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 0));
+ MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 1));
+ MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 2));
+ MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 3));
MMIO_D(_MMIO(_PLANE_CTL_3_A));
MMIO_D(_MMIO(_PLANE_CTL_3_B));
MMIO_D(_MMIO(0x72380));
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 06/16] drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() define
2024-05-10 15:23 ` [PATCH 06/16] drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() define Ville Syrjala
@ 2024-05-13 10:23 ` Jani Nikula
0 siblings, 0 replies; 48+ messages in thread
From: Jani Nikula @ 2024-05-13 10:23 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: Zhenyu Wang, Zhi Wang
On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Stop hand rolling PLANE_AUX_OFFSET() and just use the real thing.
>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> CC: Zhi Wang <zhi.wang.linux@gmail.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/gvt/handlers.c | 24 ++++++++++-----------
> drivers/gpu/drm/i915/gvt/reg.h | 2 --
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 24 ++++++++++-----------
> 3 files changed, 24 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 6b02612ddef5..6f633035618e 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2693,20 +2693,20 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
> MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>
> MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>
> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
> index e8a56faafe95..90d8eb1761a3 100644
> --- a/drivers/gpu/drm/i915/gvt/reg.h
> +++ b/drivers/gpu/drm/i915/gvt/reg.h
> @@ -57,8 +57,6 @@
>
> #define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)
>
> -#define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100)
> -
> #define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe))
>
> #define REG50080_FLIP_TYPE_MASK 0x3
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index cf45342a6db0..ad3bf60855bc 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -1018,18 +1018,18 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter)
> MMIO_D(PLANE_AUX_DIST(PIPE_C, 1));
> MMIO_D(PLANE_AUX_DIST(PIPE_C, 2));
> MMIO_D(PLANE_AUX_DIST(PIPE_C, 3));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 1)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 2)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 3)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 4)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 1)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 2)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 3)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 4)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 1)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 2)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 3)));
> - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 4)));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 0));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 1));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 2));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 3));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 0));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 1));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 2));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 3));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 0));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 1));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 2));
> + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 3));
> MMIO_D(_MMIO(_PLANE_CTL_3_A));
> MMIO_D(_MMIO(_PLANE_CTL_3_B));
> MMIO_D(_MMIO(0x72380));
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 07/16] drm/i915/gvt: Use the full PLANE_KEY*() defines
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
` (5 preceding siblings ...)
2024-05-10 15:23 ` [PATCH 06/16] drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() define Ville Syrjala
@ 2024-05-10 15:23 ` Ville Syrjala
2024-05-13 10:25 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 08/16] drm/i915/gvt: Use PLANE_CTL and PLANE_SURF defines Ville Syrjala
` (14 subsequent siblings)
21 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2024-05-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Zhenyu Wang, Zhi Wang
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Stop hand rolling PLANE_KEY*() register defines and just
use the real thing.
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
CC: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index ad3bf60855bc..b53c98cd6d7f 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -1075,15 +1075,15 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(_MMIO(0x70034));
MMIO_D(_MMIO(0x71034));
MMIO_D(_MMIO(0x72034));
- MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)));
- MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)));
- MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)));
- MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)));
- MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)));
- MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)));
- MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)));
- MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)));
- MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)));
+ MMIO_D(PLANE_KEYVAL(PIPE_A, 0));
+ MMIO_D(PLANE_KEYVAL(PIPE_B, 0));
+ MMIO_D(PLANE_KEYVAL(PIPE_C, 0));
+ MMIO_D(PLANE_KEYMAX(PIPE_A, 0));
+ MMIO_D(PLANE_KEYMAX(PIPE_B, 0));
+ MMIO_D(PLANE_KEYMAX(PIPE_C, 0));
+ MMIO_D(PLANE_KEYMSK(PIPE_A, 0));
+ MMIO_D(PLANE_KEYMSK(PIPE_B, 0));
+ MMIO_D(PLANE_KEYMSK(PIPE_C, 0));
MMIO_D(_MMIO(0x44500));
#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
MMIO_RING_D(CSFE_CHICKEN1_REG);
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 07/16] drm/i915/gvt: Use the full PLANE_KEY*() defines
2024-05-10 15:23 ` [PATCH 07/16] drm/i915/gvt: Use the full PLANE_KEY*() defines Ville Syrjala
@ 2024-05-13 10:25 ` Jani Nikula
0 siblings, 0 replies; 48+ messages in thread
From: Jani Nikula @ 2024-05-13 10:25 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: Zhenyu Wang, Zhi Wang
On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Stop hand rolling PLANE_KEY*() register defines and just
> use the real thing.
>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> CC: Zhi Wang <zhi.wang.linux@gmail.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index ad3bf60855bc..b53c98cd6d7f 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -1075,15 +1075,15 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter)
> MMIO_D(_MMIO(0x70034));
> MMIO_D(_MMIO(0x71034));
> MMIO_D(_MMIO(0x72034));
> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)));
> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)));
> - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)));
> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)));
> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)));
> - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)));
> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)));
> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)));
> - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)));
> + MMIO_D(PLANE_KEYVAL(PIPE_A, 0));
> + MMIO_D(PLANE_KEYVAL(PIPE_B, 0));
> + MMIO_D(PLANE_KEYVAL(PIPE_C, 0));
> + MMIO_D(PLANE_KEYMAX(PIPE_A, 0));
> + MMIO_D(PLANE_KEYMAX(PIPE_B, 0));
> + MMIO_D(PLANE_KEYMAX(PIPE_C, 0));
> + MMIO_D(PLANE_KEYMSK(PIPE_A, 0));
> + MMIO_D(PLANE_KEYMSK(PIPE_B, 0));
> + MMIO_D(PLANE_KEYMSK(PIPE_C, 0));
> MMIO_D(_MMIO(0x44500));
> #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
> MMIO_RING_D(CSFE_CHICKEN1_REG);
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 08/16] drm/i915/gvt: Use PLANE_CTL and PLANE_SURF defines
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
` (6 preceding siblings ...)
2024-05-10 15:23 ` [PATCH 07/16] drm/i915/gvt: Use the full PLANE_KEY*() defines Ville Syrjala
@ 2024-05-10 15:23 ` Ville Syrjala
2024-05-13 10:30 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 09/16] drm/i915: Drop useless PLANE_FOO_3 register defines Ville Syrjala
` (13 subsequent siblings)
21 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2024-05-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Zhenyu Wang, Zhi Wang
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Stop hand rolling PLANE_CTL and PLANE_SURF for the third plane
and just use the real thing.
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
CC: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index b53c98cd6d7f..843bdb46d49c 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -1030,12 +1030,12 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 1));
MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 2));
MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 3));
- MMIO_D(_MMIO(_PLANE_CTL_3_A));
- MMIO_D(_MMIO(_PLANE_CTL_3_B));
- MMIO_D(_MMIO(0x72380));
- MMIO_D(_MMIO(0x7239c));
- MMIO_D(_MMIO(_PLANE_SURF_3_A));
- MMIO_D(_MMIO(_PLANE_SURF_3_B));
+ MMIO_D(PLANE_CTL(PIPE_A, 2));
+ MMIO_D(PLANE_CTL(PIPE_B, 2));
+ MMIO_D(PLANE_CTL(PIPE_C, 2));
+ MMIO_D(PLANE_SURF(PIPE_A, 2));
+ MMIO_D(PLANE_SURF(PIPE_B, 2));
+ MMIO_D(PLANE_SURF(PIPE_C, 2));
MMIO_D(DMC_SSP_BASE);
MMIO_D(DMC_HTP_SKL);
MMIO_D(DMC_LAST_WRITE);
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 08/16] drm/i915/gvt: Use PLANE_CTL and PLANE_SURF defines
2024-05-10 15:23 ` [PATCH 08/16] drm/i915/gvt: Use PLANE_CTL and PLANE_SURF defines Ville Syrjala
@ 2024-05-13 10:30 ` Jani Nikula
0 siblings, 0 replies; 48+ messages in thread
From: Jani Nikula @ 2024-05-13 10:30 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: Zhenyu Wang, Zhi Wang
On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Stop hand rolling PLANE_CTL and PLANE_SURF for the third plane
> and just use the real thing.
>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> CC: Zhi Wang <zhi.wang.linux@gmail.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
The original is a baffling mix.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index b53c98cd6d7f..843bdb46d49c 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -1030,12 +1030,12 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter)
> MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 1));
> MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 2));
> MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 3));
> - MMIO_D(_MMIO(_PLANE_CTL_3_A));
> - MMIO_D(_MMIO(_PLANE_CTL_3_B));
> - MMIO_D(_MMIO(0x72380));
> - MMIO_D(_MMIO(0x7239c));
> - MMIO_D(_MMIO(_PLANE_SURF_3_A));
> - MMIO_D(_MMIO(_PLANE_SURF_3_B));
> + MMIO_D(PLANE_CTL(PIPE_A, 2));
> + MMIO_D(PLANE_CTL(PIPE_B, 2));
> + MMIO_D(PLANE_CTL(PIPE_C, 2));
> + MMIO_D(PLANE_SURF(PIPE_A, 2));
> + MMIO_D(PLANE_SURF(PIPE_B, 2));
> + MMIO_D(PLANE_SURF(PIPE_C, 2));
> MMIO_D(DMC_SSP_BASE);
> MMIO_D(DMC_HTP_SKL);
> MMIO_D(DMC_LAST_WRITE);
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 09/16] drm/i915: Drop useless PLANE_FOO_3 register defines
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
` (7 preceding siblings ...)
2024-05-10 15:23 ` [PATCH 08/16] drm/i915/gvt: Use PLANE_CTL and PLANE_SURF defines Ville Syrjala
@ 2024-05-10 15:23 ` Ville Syrjala
2024-05-13 10:32 ` Jani Nikula
2024-05-13 16:58 ` [PATCH v2 " Ville Syrjala
2024-05-10 15:23 ` [PATCH 10/16] drm/i915: Shuffle the skl+ plane register definitions Ville Syrjala
` (12 subsequent siblings)
21 siblings, 2 replies; 48+ messages in thread
From: Ville Syrjala @ 2024-05-10 15:23 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We only need register defines for the first two planes
on the first two pipes. Nuke everything else.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../gpu/drm/i915/display/skl_universal_plane_regs.h | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 2222d0c760e8..0558d97614e1 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -234,49 +234,38 @@
#define _PLANE_CTL_1_B 0x71180
#define _PLANE_CTL_2_B 0x71280
-#define _PLANE_CTL_3_B 0x71380
#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
-#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
#define PLANE_CTL(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
#define _PLANE_STRIDE_1_B 0x71188
#define _PLANE_STRIDE_2_B 0x71288
-#define _PLANE_STRIDE_3_B 0x71388
#define _PLANE_STRIDE_1(pipe) \
_PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
#define _PLANE_STRIDE_2(pipe) \
_PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
-#define _PLANE_STRIDE_3(pipe) \
- _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
#define PLANE_STRIDE(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
#define _PLANE_POS_1_B 0x7118c
#define _PLANE_POS_2_B 0x7128c
-#define _PLANE_POS_3_B 0x7138c
#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
-#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
#define PLANE_POS(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
#define _PLANE_SIZE_1_B 0x71190
#define _PLANE_SIZE_2_B 0x71290
-#define _PLANE_SIZE_3_B 0x71390
#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
-#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
#define PLANE_SIZE(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
#define _PLANE_SURF_1_B 0x7119c
#define _PLANE_SURF_2_B 0x7129c
-#define _PLANE_SURF_3_B 0x7139c
#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
-#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
@@ -351,7 +340,6 @@
#define _PLANE_COLOR_CTL_1_B 0x711CC
#define _PLANE_COLOR_CTL_2_B 0x712CC
-#define _PLANE_COLOR_CTL_3_B 0x713CC
#define _PLANE_COLOR_CTL_1(pipe) \
_PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
#define _PLANE_COLOR_CTL_2(pipe) \
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 09/16] drm/i915: Drop useless PLANE_FOO_3 register defines
2024-05-10 15:23 ` [PATCH 09/16] drm/i915: Drop useless PLANE_FOO_3 register defines Ville Syrjala
@ 2024-05-13 10:32 ` Jani Nikula
2024-05-13 16:58 ` [PATCH v2 " Ville Syrjala
1 sibling, 0 replies; 48+ messages in thread
From: Jani Nikula @ 2024-05-13 10:32 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We only need register defines for the first two planes
> on the first two pipes. Nuke everything else.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/skl_universal_plane_regs.h | 12 ------------
> 1 file changed, 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> index 2222d0c760e8..0558d97614e1 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> @@ -234,49 +234,38 @@
>
> #define _PLANE_CTL_1_B 0x71180
> #define _PLANE_CTL_2_B 0x71280
> -#define _PLANE_CTL_3_B 0x71380
> #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
> #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
> -#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
> #define PLANE_CTL(pipe, plane) \
> _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
>
> #define _PLANE_STRIDE_1_B 0x71188
> #define _PLANE_STRIDE_2_B 0x71288
> -#define _PLANE_STRIDE_3_B 0x71388
> #define _PLANE_STRIDE_1(pipe) \
> _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
> #define _PLANE_STRIDE_2(pipe) \
> _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
> -#define _PLANE_STRIDE_3(pipe) \
> - _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
> #define PLANE_STRIDE(pipe, plane) \
> _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
>
> #define _PLANE_POS_1_B 0x7118c
> #define _PLANE_POS_2_B 0x7128c
> -#define _PLANE_POS_3_B 0x7138c
> #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
> #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
> -#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
> #define PLANE_POS(pipe, plane) \
> _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
>
> #define _PLANE_SIZE_1_B 0x71190
> #define _PLANE_SIZE_2_B 0x71290
> -#define _PLANE_SIZE_3_B 0x71390
> #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
> #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
> -#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
> #define PLANE_SIZE(pipe, plane) \
> _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
>
> #define _PLANE_SURF_1_B 0x7119c
> #define _PLANE_SURF_2_B 0x7129c
> -#define _PLANE_SURF_3_B 0x7139c
> #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
> #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
> -#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
> #define PLANE_SURF(pipe, plane) \
> _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
>
> @@ -351,7 +340,6 @@
>
> #define _PLANE_COLOR_CTL_1_B 0x711CC
> #define _PLANE_COLOR_CTL_2_B 0x712CC
> -#define _PLANE_COLOR_CTL_3_B 0x713CC
> #define _PLANE_COLOR_CTL_1(pipe) \
> _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
> #define _PLANE_COLOR_CTL_2(pipe) \
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH v2 09/16] drm/i915: Drop useless PLANE_FOO_3 register defines
2024-05-10 15:23 ` [PATCH 09/16] drm/i915: Drop useless PLANE_FOO_3 register defines Ville Syrjala
2024-05-13 10:32 ` Jani Nikula
@ 2024-05-13 16:58 ` Ville Syrjala
1 sibling, 0 replies; 48+ messages in thread
From: Ville Syrjala @ 2024-05-13 16:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We only need register defines for the first two planes
on the first two pipes. Nuke everything else.
v2: Drop a few more that snuck through
Reviewed-by: Jani Nikula <jani.nikula@intel.com> #v1
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../i915/display/skl_universal_plane_regs.h | 19 -------------------
1 file changed, 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 2222d0c760e8..49278584caa7 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -10,7 +10,6 @@
#define _PLANE_CTL_1_A 0x70180
#define _PLANE_CTL_2_A 0x70280
-#define _PLANE_CTL_3_A 0x70380
#define PLANE_CTL_ENABLE REG_BIT(31)
#define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
#define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
@@ -76,31 +75,26 @@
#define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
#define _PLANE_STRIDE_1_A 0x70188
#define _PLANE_STRIDE_2_A 0x70288
-#define _PLANE_STRIDE_3_A 0x70388
#define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
#define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
#define _PLANE_POS_1_A 0x7018c
#define _PLANE_POS_2_A 0x7028c
-#define _PLANE_POS_3_A 0x7038c
#define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
#define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
#define PLANE_POS_X_MASK REG_GENMASK(15, 0)
#define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
#define _PLANE_SIZE_1_A 0x70190
#define _PLANE_SIZE_2_A 0x70290
-#define _PLANE_SIZE_3_A 0x70390
#define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
#define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
#define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
#define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
#define _PLANE_SURF_1_A 0x7019c
#define _PLANE_SURF_2_A 0x7029c
-#define _PLANE_SURF_3_A 0x7039c
#define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
#define PLANE_SURF_DECRYPT REG_BIT(2)
#define _PLANE_OFFSET_1_A 0x701a4
#define _PLANE_OFFSET_2_A 0x702a4
-#define _PLANE_OFFSET_3_A 0x703a4
#define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
#define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
#define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
@@ -145,7 +139,6 @@
#define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
-#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
#define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
@@ -234,49 +227,38 @@
#define _PLANE_CTL_1_B 0x71180
#define _PLANE_CTL_2_B 0x71280
-#define _PLANE_CTL_3_B 0x71380
#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
-#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
#define PLANE_CTL(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
#define _PLANE_STRIDE_1_B 0x71188
#define _PLANE_STRIDE_2_B 0x71288
-#define _PLANE_STRIDE_3_B 0x71388
#define _PLANE_STRIDE_1(pipe) \
_PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
#define _PLANE_STRIDE_2(pipe) \
_PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
-#define _PLANE_STRIDE_3(pipe) \
- _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
#define PLANE_STRIDE(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
#define _PLANE_POS_1_B 0x7118c
#define _PLANE_POS_2_B 0x7128c
-#define _PLANE_POS_3_B 0x7138c
#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
-#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
#define PLANE_POS(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
#define _PLANE_SIZE_1_B 0x71190
#define _PLANE_SIZE_2_B 0x71290
-#define _PLANE_SIZE_3_B 0x71390
#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
-#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
#define PLANE_SIZE(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
#define _PLANE_SURF_1_B 0x7119c
#define _PLANE_SURF_2_B 0x7129c
-#define _PLANE_SURF_3_B 0x7139c
#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
-#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
@@ -351,7 +333,6 @@
#define _PLANE_COLOR_CTL_1_B 0x711CC
#define _PLANE_COLOR_CTL_2_B 0x712CC
-#define _PLANE_COLOR_CTL_3_B 0x713CC
#define _PLANE_COLOR_CTL_1(pipe) \
_PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
#define _PLANE_COLOR_CTL_2(pipe) \
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 10/16] drm/i915: Shuffle the skl+ plane register definitions
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
` (8 preceding siblings ...)
2024-05-10 15:23 ` [PATCH 09/16] drm/i915: Drop useless PLANE_FOO_3 register defines Ville Syrjala
@ 2024-05-10 15:23 ` Ville Syrjala
2024-05-13 11:28 ` Jani Nikula
2024-05-13 16:59 ` [PATCH v2 " Ville Syrjala
2024-05-10 15:23 ` [PATCH 11/16] drm/i915: Use REG_BIT for PLANE_WM bits Ville Syrjala
` (11 subsequent siblings)
21 siblings, 2 replies; 48+ messages in thread
From: Ville Syrjala @ 2024-05-10 15:23 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rearrange the plane skl+ universal plane register definitions:
- keep everything related to the same register in one place
- sort based on register offset
- unify the whitespace/etc a bit
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../i915/display/skl_universal_plane_regs.h | 502 ++++++++----------
1 file changed, 207 insertions(+), 295 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 0558d97614e1..0ad14727e334 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -9,8 +9,6 @@
#include "intel_display_reg_defs.h"
#define _PLANE_CTL_1_A 0x70180
-#define _PLANE_CTL_2_A 0x70280
-#define _PLANE_CTL_3_A 0x70380
#define PLANE_CTL_ENABLE REG_BIT(31)
#define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
#define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
@@ -74,59 +72,132 @@
#define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
#define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
#define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
+#define _PLANE_CTL_2_A 0x70280
+#define _PLANE_CTL_1_B 0x71180
+#define _PLANE_CTL_2_B 0x71280
+#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
+#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
+#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
+
#define _PLANE_STRIDE_1_A 0x70188
-#define _PLANE_STRIDE_2_A 0x70288
-#define _PLANE_STRIDE_3_A 0x70388
#define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
#define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
+#define _PLANE_STRIDE_2_A 0x70288
+#define _PLANE_STRIDE_1_B 0x71188
+#define _PLANE_STRIDE_2_B 0x71288
+#define _PLANE_STRIDE_1(pipe) _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
+#define _PLANE_STRIDE_2(pipe) _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
+#define PLANE_STRIDE(pipe, plane) _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
+
#define _PLANE_POS_1_A 0x7018c
-#define _PLANE_POS_2_A 0x7028c
-#define _PLANE_POS_3_A 0x7038c
#define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
#define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
#define PLANE_POS_X_MASK REG_GENMASK(15, 0)
#define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
+#define _PLANE_POS_2_A 0x7028c
+#define _PLANE_POS_1_B 0x7118c
+#define _PLANE_POS_2_B 0x7128c
+#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
+#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
+#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
+
#define _PLANE_SIZE_1_A 0x70190
-#define _PLANE_SIZE_2_A 0x70290
-#define _PLANE_SIZE_3_A 0x70390
#define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
#define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
#define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
#define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
+#define _PLANE_SIZE_2_A 0x70290
+#define _PLANE_SIZE_1_B 0x71190
+#define _PLANE_SIZE_2_B 0x71290
+#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
+#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
+#define PLANE_SIZE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
+
+#define _PLANE_KEYVAL_1_A 0x70194
+#define _PLANE_KEYVAL_2_A 0x70294
+#define _PLANE_KEYVAL_1_B 0x71194
+#define _PLANE_KEYVAL_2_B 0x71294
+#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
+#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
+#define PLANE_KEYVAL(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
+
+#define _PLANE_KEYMSK_1_A 0x70198
+#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31)
+#define _PLANE_KEYMSK_2_A 0x70298
+#define _PLANE_KEYMSK_1_B 0x71198
+#define _PLANE_KEYMSK_2_B 0x71298
+#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
+#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
+#define PLANE_KEYMSK(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
+
#define _PLANE_SURF_1_A 0x7019c
-#define _PLANE_SURF_2_A 0x7029c
-#define _PLANE_SURF_3_A 0x7039c
#define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
#define PLANE_SURF_DECRYPT REG_BIT(2)
+#define _PLANE_SURF_2_A 0x7029c
+#define _PLANE_SURF_1_B 0x7119c
+#define _PLANE_SURF_2_B 0x7129c
+#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
+#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
+#define PLANE_SURF(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+
+#define _PLANE_KEYMAX_1_A 0x701a0
+#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24)
+#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a))
+#define _PLANE_KEYMAX_2_A 0x702a0
+#define _PLANE_KEYMAX_1_B 0x711a0
+#define _PLANE_KEYMAX_2_B 0x712a0
+#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
+#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
+#define PLANE_KEYMAX(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
+
#define _PLANE_OFFSET_1_A 0x701a4
-#define _PLANE_OFFSET_2_A 0x702a4
-#define _PLANE_OFFSET_3_A 0x703a4
#define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
#define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
#define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
#define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))
-#define _PLANE_KEYVAL_1_A 0x70194
-#define _PLANE_KEYVAL_2_A 0x70294
-#define _PLANE_KEYMSK_1_A 0x70198
-#define _PLANE_KEYMSK_2_A 0x70298
-#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31)
-#define _PLANE_KEYMAX_1_A 0x701a0
-#define _PLANE_KEYMAX_2_A 0x702a0
-#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24)
-#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a))
+#define _PLANE_OFFSET_2_A 0x702a4
+#define _PLANE_OFFSET_1_B 0x711a4
+#define _PLANE_OFFSET_2_B 0x712a4
+#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
+#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
+#define PLANE_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
+
#define _PLANE_SURFLIVE_1_A 0x701ac
#define _PLANE_SURFLIVE_2_A 0x702ac
+#define _PLANE_SURFLIVE_1_B 0x711ac
+#define _PLANE_SURFLIVE_2_B 0x712ac
+#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B)
+#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
+#define PLANE_SURFLIVE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
+
#define _PLANE_CC_VAL_1_A 0x701b4
#define _PLANE_CC_VAL_2_A 0x702b4
+#define _PLANE_CC_VAL_1_B 0x711b4
+#define _PLANE_CC_VAL_2_B 0x712b4
+#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
+#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
+#define PLANE_CC_VAL(pipe, plane, dw) _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
+
#define _PLANE_AUX_DIST_1_A 0x701c0
#define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
#define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
#define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
#define _PLANE_AUX_DIST_2_A 0x702c0
+#define _PLANE_AUX_DIST_1_B 0x711c0
+#define _PLANE_AUX_DIST_2_B 0x712c0
+#define _PLANE_AUX_DIST_1(pipe) _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
+#define _PLANE_AUX_DIST_2(pipe) _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
+#define PLANE_AUX_DIST(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
+
#define _PLANE_AUX_OFFSET_1_A 0x701c4
#define _PLANE_AUX_OFFSET_2_A 0x702c4
+#define _PLANE_AUX_OFFSET_1_B 0x711c4
+#define _PLANE_AUX_OFFSET_2_B 0x712c4
+#define _PLANE_AUX_OFFSET_1(pipe) _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
+#define _PLANE_AUX_OFFSET_2(pipe) _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
+#define PLANE_AUX_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
+
#define _PLANE_CUS_CTL_1_A 0x701c8
-#define _PLANE_CUS_CTL_2_A 0x702c8
#define PLANE_CUS_ENABLE REG_BIT(31)
#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
#define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
@@ -143,9 +214,14 @@
#define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
#define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
#define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
-#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
-#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
-#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
+#define _PLANE_CUS_CTL_2_A 0x702c8
+#define _PLANE_CUS_CTL_1_B 0x711c8
+#define _PLANE_CUS_CTL_2_B 0x712c8
+#define _PLANE_CUS_CTL_1(pipe) _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
+#define _PLANE_CUS_CTL_2(pipe) _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
+#define PLANE_CUS_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
+
+#define _PLANE_COLOR_CTL_1_A 0x701cc /* GLK+ */
#define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
@@ -162,296 +238,132 @@
#define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
-#define _PLANE_CHICKEN_1_A 0x7026C /* tgl+ */
-#define _PLANE_CHICKEN_2_A 0x7036C /* tgl+ */
-#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
-#define _PLANE_BUF_CFG_1_A 0x7027c
-#define _PLANE_BUF_CFG_2_A 0x7037c
-/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
-#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
-#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
-#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
-#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
-#define _PLANE_NV12_BUF_CFG_1_A 0x70278
-#define _PLANE_NV12_BUF_CFG_2_A 0x70378
-
-#define _PLANE_CC_VAL_1_B 0x711b4
-#define _PLANE_CC_VAL_2_B 0x712b4
-#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
-#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
-#define PLANE_CC_VAL(pipe, plane, dw) \
- _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
-
-/* Input CSC Register Definitions */
-#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
-#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
-
-#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
-#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
-
-#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
- _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
- _PLANE_INPUT_CSC_RY_GY_1_B)
-#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
- _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
- _PLANE_INPUT_CSC_RY_GY_2_B)
-
-#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
- _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
-
-#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
-#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
-
-#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
-#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
-
-#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
- _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
- _PLANE_INPUT_CSC_PREOFF_HI_1_B)
-#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
- _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
- _PLANE_INPUT_CSC_PREOFF_HI_2_B)
-#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
- _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
+#define _PLANE_COLOR_CTL_2_A 0x702cc
+#define _PLANE_COLOR_CTL_1_B 0x711cc
+#define _PLANE_COLOR_CTL_2_B 0x712cc
+#define _PLANE_COLOR_CTL_1(pipe) _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
+#define _PLANE_COLOR_CTL_2(pipe) _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
+#define PLANE_COLOR_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
+
+#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701e0
+#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702e0
+#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711e0
+#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712e0
+#define _PLANE_INPUT_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, _PLANE_INPUT_CSC_RY_GY_1_B)
+#define _PLANE_INPUT_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, _PLANE_INPUT_CSC_RY_GY_2_B)
+#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701f8
+#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702f8
+#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711f8
+#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712f8
+#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, _PLANE_INPUT_CSC_PREOFF_HI_1_B)
+#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, _PLANE_INPUT_CSC_PREOFF_HI_2_B)
+#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
-
#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
-
-#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
- _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
- _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
-#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
- _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
- _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
-#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
- _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
-
-#define _PLANE_CTL_1_B 0x71180
-#define _PLANE_CTL_2_B 0x71280
-#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
-#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
-#define PLANE_CTL(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
-
-#define _PLANE_STRIDE_1_B 0x71188
-#define _PLANE_STRIDE_2_B 0x71288
-#define _PLANE_STRIDE_1(pipe) \
- _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
-#define _PLANE_STRIDE_2(pipe) \
- _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
-#define PLANE_STRIDE(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
-
-#define _PLANE_POS_1_B 0x7118c
-#define _PLANE_POS_2_B 0x7128c
-#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
-#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
-#define PLANE_POS(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
-
-#define _PLANE_SIZE_1_B 0x71190
-#define _PLANE_SIZE_2_B 0x71290
-#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
-#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
-#define PLANE_SIZE(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
-
-#define _PLANE_SURF_1_B 0x7119c
-#define _PLANE_SURF_2_B 0x7129c
-#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
-#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
-#define PLANE_SURF(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
-
-#define _PLANE_OFFSET_1_B 0x711a4
-#define _PLANE_OFFSET_2_B 0x712a4
-#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
-#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
-#define PLANE_OFFSET(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
-
-#define _PLANE_KEYVAL_1_B 0x71194
-#define _PLANE_KEYVAL_2_B 0x71294
-#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
-#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
-#define PLANE_KEYVAL(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
-
-#define _PLANE_KEYMSK_1_B 0x71198
-#define _PLANE_KEYMSK_2_B 0x71298
-#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
-#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
-#define PLANE_KEYMSK(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
-
-#define _PLANE_KEYMAX_1_B 0x711a0
-#define _PLANE_KEYMAX_2_B 0x712a0
-#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
-#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
-#define PLANE_KEYMAX(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
-
-#define _PLANE_SURFLIVE_1_B 0x711ac
-#define _PLANE_SURFLIVE_2_B 0x712ac
-#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B)
-#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
-#define PLANE_SURFLIVE(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
-
-#define _PLANE_CHICKEN_1_B 0x7126c
-#define _PLANE_CHICKEN_2_B 0x7136c
-#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B)
-#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
-#define PLANE_CHICKEN(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
-
-#define _PLANE_AUX_DIST_1_B 0x711c0
-#define _PLANE_AUX_DIST_2_B 0x712c0
-#define _PLANE_AUX_DIST_1(pipe) \
- _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
-#define _PLANE_AUX_DIST_2(pipe) \
- _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
-#define PLANE_AUX_DIST(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
-
-#define _PLANE_AUX_OFFSET_1_B 0x711c4
-#define _PLANE_AUX_OFFSET_2_B 0x712c4
-#define _PLANE_AUX_OFFSET_1(pipe) \
- _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
-#define _PLANE_AUX_OFFSET_2(pipe) \
- _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
-#define PLANE_AUX_OFFSET(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
-
-#define _PLANE_CUS_CTL_1_B 0x711c8
-#define _PLANE_CUS_CTL_2_B 0x712c8
-#define _PLANE_CUS_CTL_1(pipe) \
- _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
-#define _PLANE_CUS_CTL_2(pipe) \
- _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
-#define PLANE_CUS_CTL(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
-
-#define _PLANE_COLOR_CTL_1_B 0x711CC
-#define _PLANE_COLOR_CTL_2_B 0x712CC
-#define _PLANE_COLOR_CTL_1(pipe) \
- _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
-#define _PLANE_COLOR_CTL_2(pipe) \
- _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
-#define PLANE_COLOR_CTL(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
-
-/* Plane CSC Registers */
-#define _PLANE_CSC_RY_GY_1_A 0x70210
-#define _PLANE_CSC_RY_GY_2_A 0x70310
-
-#define _PLANE_CSC_RY_GY_1_B 0x71210
-#define _PLANE_CSC_RY_GY_2_B 0x71310
-
-#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
- _PLANE_CSC_RY_GY_1_B)
-#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, \
- _PLANE_CSC_RY_GY_2_B)
-#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
- _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
- _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
+#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
+
+#define _PLANE_CSC_RY_GY_1_A 0x70210
+#define _PLANE_CSC_RY_GY_2_A 0x70310
+#define _PLANE_CSC_RY_GY_1_B 0x71210
+#define _PLANE_CSC_RY_GY_2_B 0x71310
+#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, _PLANE_CSC_RY_GY_1_B)
+#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, _PLANE_CSC_RY_GY_2_B)
+#define PLANE_CSC_COEFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
-
#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
-
-#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
- _PLANE_CSC_PREOFF_HI_1_B)
-#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
- _PLANE_CSC_PREOFF_HI_2_B)
-#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
- (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
- (index) * 4)
+#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, _PLANE_CSC_PREOFF_HI_1_B)
+#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, _PLANE_CSC_PREOFF_HI_2_B)
+#define PLANE_CSC_PREOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + (index) * 4)
#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
-
#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
+#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, _PLANE_CSC_POSTOFF_HI_1_B)
+#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, _PLANE_CSC_POSTOFF_HI_2_B)
+#define PLANE_CSC_POSTOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
-#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
- _PLANE_CSC_POSTOFF_HI_1_B)
-#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
- _PLANE_CSC_POSTOFF_HI_2_B)
-#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
- (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
- (index) * 4)
+#define _PLANE_WM_1_A_0 0x70240
+#define PLANE_WM_EN (1 << 31)
+#define PLANE_WM_IGNORE_LINES (1 << 30)
+#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
+#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
+#define _PLANE_WM_1_B_0 0x71240
+#define _PLANE_WM_2_A_0 0x70340
+#define _PLANE_WM_2_B_0 0x71340
+#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
+#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
+#define _PLANE_WM_BASE(pipe, plane) _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
+#define PLANE_WM(pipe, plane, level) _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
-#define _PLANE_WM_1_A_0 0x70240
-#define _PLANE_WM_1_B_0 0x71240
-#define _PLANE_WM_2_A_0 0x70340
-#define _PLANE_WM_2_B_0 0x71340
-#define _PLANE_WM_SAGV_1_A 0x70258
-#define _PLANE_WM_SAGV_1_B 0x71258
-#define _PLANE_WM_SAGV_2_A 0x70358
-#define _PLANE_WM_SAGV_2_B 0x71358
-#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C
-#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C
-#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C
-#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C
-#define _PLANE_WM_TRANS_1_A 0x70268
-#define _PLANE_WM_TRANS_1_B 0x71268
-#define _PLANE_WM_TRANS_2_A 0x70368
-#define _PLANE_WM_TRANS_2_B 0x71368
-#define PLANE_WM_EN (1 << 31)
-#define PLANE_WM_IGNORE_LINES (1 << 30)
-#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
-#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
+#define _PLANE_WM_SAGV_1_A 0x70258
+#define _PLANE_WM_SAGV_1_B 0x71258
+#define _PLANE_WM_SAGV_2_A 0x70358
+#define _PLANE_WM_SAGV_2_B 0x71358
+#define _PLANE_WM_SAGV_1(pipe) _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
+#define _PLANE_WM_SAGV_2(pipe) _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
+#define PLANE_WM_SAGV(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
-#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
-#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
-#define _PLANE_WM_BASE(pipe, plane) \
- _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
-#define PLANE_WM(pipe, plane, level) \
- _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
-#define _PLANE_WM_SAGV_1(pipe) \
- _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
-#define _PLANE_WM_SAGV_2(pipe) \
- _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
-#define PLANE_WM_SAGV(pipe, plane) \
- _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
-#define _PLANE_WM_SAGV_TRANS_1(pipe) \
- _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
-#define _PLANE_WM_SAGV_TRANS_2(pipe) \
- _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
-#define PLANE_WM_SAGV_TRANS(pipe, plane) \
- _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
-#define _PLANE_WM_TRANS_1(pipe) \
- _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
-#define _PLANE_WM_TRANS_2(pipe) \
- _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
-#define PLANE_WM_TRANS(pipe, plane) \
- _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
+#define _PLANE_WM_SAGV_TRANS_1_A 0x7025c
+#define _PLANE_WM_SAGV_TRANS_1_B 0x7125c
+#define _PLANE_WM_SAGV_TRANS_2_A 0x7035c
+#define _PLANE_WM_SAGV_TRANS_2_B 0x7135c
+#define _PLANE_WM_SAGV_TRANS_1(pipe) _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
+#define _PLANE_WM_SAGV_TRANS_2(pipe) _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
+#define PLANE_WM_SAGV_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
+#define _PLANE_WM_TRANS_1_A 0x70268
+#define _PLANE_WM_TRANS_1_B 0x71268
+#define _PLANE_WM_TRANS_2_A 0x70368
+#define _PLANE_WM_TRANS_2_B 0x71368
+#define _PLANE_WM_TRANS_1(pipe) _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
+#define _PLANE_WM_TRANS_2(pipe) _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
+#define PLANE_WM_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
+
+#define _PLANE_CHICKEN_1_A 0x7026c /* tgl+ */
+#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
+#define _PLANE_CHICKEN_2_A 0x7036c
+#define _PLANE_CHICKEN_1_B 0x7126c
+#define _PLANE_CHICKEN_2_B 0x7136c
+#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B)
+#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
+#define PLANE_CHICKEN(pipe, plane) _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
+
+#define _PLANE_NV12_BUF_CFG_1_A 0x70278
+#define _PLANE_NV12_BUF_CFG_2_A 0x70378
+#define _PLANE_NV12_BUF_CFG_1_B 0x71278
+#define _PLANE_NV12_BUF_CFG_2_B 0x71378
+#define _PLANE_NV12_BUF_CFG_1(pipe) _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
+#define _PLANE_NV12_BUF_CFG_2(pipe) _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
+#define PLANE_NV12_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
+
+#define _PLANE_BUF_CFG_1_A 0x7027c
+#define _PLANE_BUF_CFG_2_A 0x7037c
+/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
+#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
+#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
+#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
+#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
#define _PLANE_BUF_CFG_1_B 0x7127c
#define _PLANE_BUF_CFG_2_B 0x7137c
-#define _PLANE_BUF_CFG_1(pipe) \
- _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
-#define _PLANE_BUF_CFG_2(pipe) \
- _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
-#define PLANE_BUF_CFG(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
-
-#define _PLANE_NV12_BUF_CFG_1_B 0x71278
-#define _PLANE_NV12_BUF_CFG_2_B 0x71378
-#define _PLANE_NV12_BUF_CFG_1(pipe) \
- _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
-#define _PLANE_NV12_BUF_CFG_2(pipe) \
- _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
-#define PLANE_NV12_BUF_CFG(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
+#define _PLANE_BUF_CFG_1(pipe) _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
+#define _PLANE_BUF_CFG_2(pipe) _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
+#define PLANE_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
#endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 10/16] drm/i915: Shuffle the skl+ plane register definitions
2024-05-10 15:23 ` [PATCH 10/16] drm/i915: Shuffle the skl+ plane register definitions Ville Syrjala
@ 2024-05-13 11:28 ` Jani Nikula
2024-05-13 16:13 ` Ville Syrjälä
2024-05-13 16:59 ` [PATCH v2 " Ville Syrjala
1 sibling, 1 reply; 48+ messages in thread
From: Jani Nikula @ 2024-05-13 11:28 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rearrange the plane skl+ universal plane register definitions:
> - keep everything related to the same register in one place
> - sort based on register offset
> - unify the whitespace/etc a bit
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> .../i915/display/skl_universal_plane_regs.h | 502 ++++++++----------
> 1 file changed, 207 insertions(+), 295 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> index 0558d97614e1..0ad14727e334 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> @@ -9,8 +9,6 @@
> #include "intel_display_reg_defs.h"
>
> #define _PLANE_CTL_1_A 0x70180
> -#define _PLANE_CTL_2_A 0x70280
> -#define _PLANE_CTL_3_A 0x70380
> #define PLANE_CTL_ENABLE REG_BIT(31)
> #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
> #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
> @@ -74,59 +72,132 @@
> #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
> #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
> #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
This is a painful patch to review (in part because some newline removals
throw off --color-moved) so I want to check something first.
Shouldn't the above register *content* definitions be...
> +#define _PLANE_CTL_2_A 0x70280
> +#define _PLANE_CTL_1_B 0x71180
> +#define _PLANE_CTL_2_B 0x71280
> +#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
> +#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
> +#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
...here after all the register *offset* definitions, not right after the
plane 1 / pipe A register offset macro? Ditto for a bunch of the other
changes here.
BR,
Jani.
> +
> #define _PLANE_STRIDE_1_A 0x70188
> -#define _PLANE_STRIDE_2_A 0x70288
> -#define _PLANE_STRIDE_3_A 0x70388
> #define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
> #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
> +#define _PLANE_STRIDE_2_A 0x70288
> +#define _PLANE_STRIDE_1_B 0x71188
> +#define _PLANE_STRIDE_2_B 0x71288
> +#define _PLANE_STRIDE_1(pipe) _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
> +#define _PLANE_STRIDE_2(pipe) _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
> +#define PLANE_STRIDE(pipe, plane) _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
> +
> #define _PLANE_POS_1_A 0x7018c
> -#define _PLANE_POS_2_A 0x7028c
> -#define _PLANE_POS_3_A 0x7038c
> #define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
> #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
> #define PLANE_POS_X_MASK REG_GENMASK(15, 0)
> #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
> +#define _PLANE_POS_2_A 0x7028c
> +#define _PLANE_POS_1_B 0x7118c
> +#define _PLANE_POS_2_B 0x7128c
> +#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
> +#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
> +#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
> +
> #define _PLANE_SIZE_1_A 0x70190
> -#define _PLANE_SIZE_2_A 0x70290
> -#define _PLANE_SIZE_3_A 0x70390
> #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
> #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
> #define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
> #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
> +#define _PLANE_SIZE_2_A 0x70290
> +#define _PLANE_SIZE_1_B 0x71190
> +#define _PLANE_SIZE_2_B 0x71290
> +#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
> +#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
> +#define PLANE_SIZE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
> +
> +#define _PLANE_KEYVAL_1_A 0x70194
> +#define _PLANE_KEYVAL_2_A 0x70294
> +#define _PLANE_KEYVAL_1_B 0x71194
> +#define _PLANE_KEYVAL_2_B 0x71294
> +#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
> +#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
> +#define PLANE_KEYVAL(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
> +
> +#define _PLANE_KEYMSK_1_A 0x70198
> +#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31)
> +#define _PLANE_KEYMSK_2_A 0x70298
> +#define _PLANE_KEYMSK_1_B 0x71198
> +#define _PLANE_KEYMSK_2_B 0x71298
> +#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
> +#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
> +#define PLANE_KEYMSK(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
> +
> #define _PLANE_SURF_1_A 0x7019c
> -#define _PLANE_SURF_2_A 0x7029c
> -#define _PLANE_SURF_3_A 0x7039c
> #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
> #define PLANE_SURF_DECRYPT REG_BIT(2)
> +#define _PLANE_SURF_2_A 0x7029c
> +#define _PLANE_SURF_1_B 0x7119c
> +#define _PLANE_SURF_2_B 0x7129c
> +#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
> +#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
> +#define PLANE_SURF(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
> +
> +#define _PLANE_KEYMAX_1_A 0x701a0
> +#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24)
> +#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a))
> +#define _PLANE_KEYMAX_2_A 0x702a0
> +#define _PLANE_KEYMAX_1_B 0x711a0
> +#define _PLANE_KEYMAX_2_B 0x712a0
> +#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
> +#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
> +#define PLANE_KEYMAX(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
> +
> #define _PLANE_OFFSET_1_A 0x701a4
> -#define _PLANE_OFFSET_2_A 0x702a4
> -#define _PLANE_OFFSET_3_A 0x703a4
> #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
> #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
> #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
> #define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))
> -#define _PLANE_KEYVAL_1_A 0x70194
> -#define _PLANE_KEYVAL_2_A 0x70294
> -#define _PLANE_KEYMSK_1_A 0x70198
> -#define _PLANE_KEYMSK_2_A 0x70298
> -#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31)
> -#define _PLANE_KEYMAX_1_A 0x701a0
> -#define _PLANE_KEYMAX_2_A 0x702a0
> -#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24)
> -#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a))
> +#define _PLANE_OFFSET_2_A 0x702a4
> +#define _PLANE_OFFSET_1_B 0x711a4
> +#define _PLANE_OFFSET_2_B 0x712a4
> +#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
> +#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
> +#define PLANE_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
> +
> #define _PLANE_SURFLIVE_1_A 0x701ac
> #define _PLANE_SURFLIVE_2_A 0x702ac
> +#define _PLANE_SURFLIVE_1_B 0x711ac
> +#define _PLANE_SURFLIVE_2_B 0x712ac
> +#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B)
> +#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
> +#define PLANE_SURFLIVE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
> +
> #define _PLANE_CC_VAL_1_A 0x701b4
> #define _PLANE_CC_VAL_2_A 0x702b4
> +#define _PLANE_CC_VAL_1_B 0x711b4
> +#define _PLANE_CC_VAL_2_B 0x712b4
> +#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
> +#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
> +#define PLANE_CC_VAL(pipe, plane, dw) _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
> +
> #define _PLANE_AUX_DIST_1_A 0x701c0
> #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
> #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
> #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
> #define _PLANE_AUX_DIST_2_A 0x702c0
> +#define _PLANE_AUX_DIST_1_B 0x711c0
> +#define _PLANE_AUX_DIST_2_B 0x712c0
> +#define _PLANE_AUX_DIST_1(pipe) _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
> +#define _PLANE_AUX_DIST_2(pipe) _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
> +#define PLANE_AUX_DIST(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
> +
> #define _PLANE_AUX_OFFSET_1_A 0x701c4
> #define _PLANE_AUX_OFFSET_2_A 0x702c4
> +#define _PLANE_AUX_OFFSET_1_B 0x711c4
> +#define _PLANE_AUX_OFFSET_2_B 0x712c4
> +#define _PLANE_AUX_OFFSET_1(pipe) _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
> +#define _PLANE_AUX_OFFSET_2(pipe) _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
> +#define PLANE_AUX_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
> +
> #define _PLANE_CUS_CTL_1_A 0x701c8
> -#define _PLANE_CUS_CTL_2_A 0x702c8
> #define PLANE_CUS_ENABLE REG_BIT(31)
> #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
> #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
> @@ -143,9 +214,14 @@
> #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
> #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
> #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
> -#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
> -#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
> -#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
> +#define _PLANE_CUS_CTL_2_A 0x702c8
> +#define _PLANE_CUS_CTL_1_B 0x711c8
> +#define _PLANE_CUS_CTL_2_B 0x712c8
> +#define _PLANE_CUS_CTL_1(pipe) _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
> +#define _PLANE_CUS_CTL_2(pipe) _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
> +#define PLANE_CUS_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
> +
> +#define _PLANE_COLOR_CTL_1_A 0x701cc /* GLK+ */
> #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
> #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
> #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
> @@ -162,296 +238,132 @@
> #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
> #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
> #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
> -#define _PLANE_CHICKEN_1_A 0x7026C /* tgl+ */
> -#define _PLANE_CHICKEN_2_A 0x7036C /* tgl+ */
> -#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
> -#define _PLANE_BUF_CFG_1_A 0x7027c
> -#define _PLANE_BUF_CFG_2_A 0x7037c
> -/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
> -#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
> -#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
> -#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
> -#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
> -#define _PLANE_NV12_BUF_CFG_1_A 0x70278
> -#define _PLANE_NV12_BUF_CFG_2_A 0x70378
> -
> -#define _PLANE_CC_VAL_1_B 0x711b4
> -#define _PLANE_CC_VAL_2_B 0x712b4
> -#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
> -#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
> -#define PLANE_CC_VAL(pipe, plane, dw) \
> - _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
> -
> -/* Input CSC Register Definitions */
> -#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
> -#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
> -
> -#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
> -#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
> -
> -#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
> - _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
> - _PLANE_INPUT_CSC_RY_GY_1_B)
> -#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
> - _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
> - _PLANE_INPUT_CSC_RY_GY_2_B)
> -
> -#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
> - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
> - _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
> -
> -#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
> -#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
> -
> -#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
> -#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
> -
> -#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
> - _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
> - _PLANE_INPUT_CSC_PREOFF_HI_1_B)
> -#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
> - _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
> - _PLANE_INPUT_CSC_PREOFF_HI_2_B)
> -#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
> - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
> - _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
> +#define _PLANE_COLOR_CTL_2_A 0x702cc
> +#define _PLANE_COLOR_CTL_1_B 0x711cc
> +#define _PLANE_COLOR_CTL_2_B 0x712cc
> +#define _PLANE_COLOR_CTL_1(pipe) _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
> +#define _PLANE_COLOR_CTL_2(pipe) _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
> +#define PLANE_COLOR_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
> +
> +#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701e0
> +#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702e0
> +#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711e0
> +#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712e0
> +#define _PLANE_INPUT_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, _PLANE_INPUT_CSC_RY_GY_1_B)
> +#define _PLANE_INPUT_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, _PLANE_INPUT_CSC_RY_GY_2_B)
> +#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
> + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
> +
> +#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701f8
> +#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702f8
> +#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711f8
> +#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712f8
> +#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, _PLANE_INPUT_CSC_PREOFF_HI_1_B)
> +#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, _PLANE_INPUT_CSC_PREOFF_HI_2_B)
> +#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
> + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
>
> #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
> #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
> -
> #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
> #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
> -
> -#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
> - _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
> - _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
> -#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
> - _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
> - _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
> -#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
> - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
> - _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
> -
> -#define _PLANE_CTL_1_B 0x71180
> -#define _PLANE_CTL_2_B 0x71280
> -#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
> -#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
> -#define PLANE_CTL(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
> -
> -#define _PLANE_STRIDE_1_B 0x71188
> -#define _PLANE_STRIDE_2_B 0x71288
> -#define _PLANE_STRIDE_1(pipe) \
> - _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
> -#define _PLANE_STRIDE_2(pipe) \
> - _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
> -#define PLANE_STRIDE(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
> -
> -#define _PLANE_POS_1_B 0x7118c
> -#define _PLANE_POS_2_B 0x7128c
> -#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
> -#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
> -#define PLANE_POS(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
> -
> -#define _PLANE_SIZE_1_B 0x71190
> -#define _PLANE_SIZE_2_B 0x71290
> -#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
> -#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
> -#define PLANE_SIZE(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
> -
> -#define _PLANE_SURF_1_B 0x7119c
> -#define _PLANE_SURF_2_B 0x7129c
> -#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
> -#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
> -#define PLANE_SURF(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
> -
> -#define _PLANE_OFFSET_1_B 0x711a4
> -#define _PLANE_OFFSET_2_B 0x712a4
> -#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
> -#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
> -#define PLANE_OFFSET(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
> -
> -#define _PLANE_KEYVAL_1_B 0x71194
> -#define _PLANE_KEYVAL_2_B 0x71294
> -#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
> -#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
> -#define PLANE_KEYVAL(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
> -
> -#define _PLANE_KEYMSK_1_B 0x71198
> -#define _PLANE_KEYMSK_2_B 0x71298
> -#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
> -#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
> -#define PLANE_KEYMSK(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
> -
> -#define _PLANE_KEYMAX_1_B 0x711a0
> -#define _PLANE_KEYMAX_2_B 0x712a0
> -#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
> -#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
> -#define PLANE_KEYMAX(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
> -
> -#define _PLANE_SURFLIVE_1_B 0x711ac
> -#define _PLANE_SURFLIVE_2_B 0x712ac
> -#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B)
> -#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
> -#define PLANE_SURFLIVE(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
> -
> -#define _PLANE_CHICKEN_1_B 0x7126c
> -#define _PLANE_CHICKEN_2_B 0x7136c
> -#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B)
> -#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
> -#define PLANE_CHICKEN(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
> -
> -#define _PLANE_AUX_DIST_1_B 0x711c0
> -#define _PLANE_AUX_DIST_2_B 0x712c0
> -#define _PLANE_AUX_DIST_1(pipe) \
> - _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
> -#define _PLANE_AUX_DIST_2(pipe) \
> - _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
> -#define PLANE_AUX_DIST(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
> -
> -#define _PLANE_AUX_OFFSET_1_B 0x711c4
> -#define _PLANE_AUX_OFFSET_2_B 0x712c4
> -#define _PLANE_AUX_OFFSET_1(pipe) \
> - _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
> -#define _PLANE_AUX_OFFSET_2(pipe) \
> - _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
> -#define PLANE_AUX_OFFSET(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
> -
> -#define _PLANE_CUS_CTL_1_B 0x711c8
> -#define _PLANE_CUS_CTL_2_B 0x712c8
> -#define _PLANE_CUS_CTL_1(pipe) \
> - _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
> -#define _PLANE_CUS_CTL_2(pipe) \
> - _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
> -#define PLANE_CUS_CTL(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
> -
> -#define _PLANE_COLOR_CTL_1_B 0x711CC
> -#define _PLANE_COLOR_CTL_2_B 0x712CC
> -#define _PLANE_COLOR_CTL_1(pipe) \
> - _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
> -#define _PLANE_COLOR_CTL_2(pipe) \
> - _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
> -#define PLANE_COLOR_CTL(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
> -
> -/* Plane CSC Registers */
> -#define _PLANE_CSC_RY_GY_1_A 0x70210
> -#define _PLANE_CSC_RY_GY_2_A 0x70310
> -
> -#define _PLANE_CSC_RY_GY_1_B 0x71210
> -#define _PLANE_CSC_RY_GY_2_B 0x71310
> -
> -#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
> - _PLANE_CSC_RY_GY_1_B)
> -#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, \
> - _PLANE_CSC_RY_GY_2_B)
> -#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
> - _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
> - _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
> +#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
> + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
> +
> +#define _PLANE_CSC_RY_GY_1_A 0x70210
> +#define _PLANE_CSC_RY_GY_2_A 0x70310
> +#define _PLANE_CSC_RY_GY_1_B 0x71210
> +#define _PLANE_CSC_RY_GY_2_B 0x71310
> +#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, _PLANE_CSC_RY_GY_1_B)
> +#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, _PLANE_CSC_RY_GY_2_B)
> +#define PLANE_CSC_COEFF(pipe, plane, index) \
> + _MMIO_PLANE(plane, _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
>
> #define _PLANE_CSC_PREOFF_HI_1_A 0x70228
> #define _PLANE_CSC_PREOFF_HI_2_A 0x70328
> -
> #define _PLANE_CSC_PREOFF_HI_1_B 0x71228
> #define _PLANE_CSC_PREOFF_HI_2_B 0x71328
> -
> -#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
> - _PLANE_CSC_PREOFF_HI_1_B)
> -#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
> - _PLANE_CSC_PREOFF_HI_2_B)
> -#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
> - (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
> - (index) * 4)
> +#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, _PLANE_CSC_PREOFF_HI_1_B)
> +#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, _PLANE_CSC_PREOFF_HI_2_B)
> +#define PLANE_CSC_PREOFF(pipe, plane, index) \
> + _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + (index) * 4)
>
> #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
> #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
> -
> #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
> #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
> +#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, _PLANE_CSC_POSTOFF_HI_1_B)
> +#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, _PLANE_CSC_POSTOFF_HI_2_B)
> +#define PLANE_CSC_POSTOFF(pipe, plane, index) \
> + _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
>
> -#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
> - _PLANE_CSC_POSTOFF_HI_1_B)
> -#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
> - _PLANE_CSC_POSTOFF_HI_2_B)
> -#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
> - (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
> - (index) * 4)
> +#define _PLANE_WM_1_A_0 0x70240
> +#define PLANE_WM_EN (1 << 31)
> +#define PLANE_WM_IGNORE_LINES (1 << 30)
> +#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
> +#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
> +#define _PLANE_WM_1_B_0 0x71240
> +#define _PLANE_WM_2_A_0 0x70340
> +#define _PLANE_WM_2_B_0 0x71340
> +#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
> +#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
> +#define _PLANE_WM_BASE(pipe, plane) _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
> +#define PLANE_WM(pipe, plane, level) _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
>
> -#define _PLANE_WM_1_A_0 0x70240
> -#define _PLANE_WM_1_B_0 0x71240
> -#define _PLANE_WM_2_A_0 0x70340
> -#define _PLANE_WM_2_B_0 0x71340
> -#define _PLANE_WM_SAGV_1_A 0x70258
> -#define _PLANE_WM_SAGV_1_B 0x71258
> -#define _PLANE_WM_SAGV_2_A 0x70358
> -#define _PLANE_WM_SAGV_2_B 0x71358
> -#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C
> -#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C
> -#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C
> -#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C
> -#define _PLANE_WM_TRANS_1_A 0x70268
> -#define _PLANE_WM_TRANS_1_B 0x71268
> -#define _PLANE_WM_TRANS_2_A 0x70368
> -#define _PLANE_WM_TRANS_2_B 0x71368
> -#define PLANE_WM_EN (1 << 31)
> -#define PLANE_WM_IGNORE_LINES (1 << 30)
> -#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
> -#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
> +#define _PLANE_WM_SAGV_1_A 0x70258
> +#define _PLANE_WM_SAGV_1_B 0x71258
> +#define _PLANE_WM_SAGV_2_A 0x70358
> +#define _PLANE_WM_SAGV_2_B 0x71358
> +#define _PLANE_WM_SAGV_1(pipe) _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
> +#define _PLANE_WM_SAGV_2(pipe) _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
> +#define PLANE_WM_SAGV(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
>
> -#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
> -#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
> -#define _PLANE_WM_BASE(pipe, plane) \
> - _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
> -#define PLANE_WM(pipe, plane, level) \
> - _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
> -#define _PLANE_WM_SAGV_1(pipe) \
> - _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
> -#define _PLANE_WM_SAGV_2(pipe) \
> - _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
> -#define PLANE_WM_SAGV(pipe, plane) \
> - _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
> -#define _PLANE_WM_SAGV_TRANS_1(pipe) \
> - _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
> -#define _PLANE_WM_SAGV_TRANS_2(pipe) \
> - _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
> -#define PLANE_WM_SAGV_TRANS(pipe, plane) \
> - _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
> -#define _PLANE_WM_TRANS_1(pipe) \
> - _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
> -#define _PLANE_WM_TRANS_2(pipe) \
> - _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
> -#define PLANE_WM_TRANS(pipe, plane) \
> - _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
> +#define _PLANE_WM_SAGV_TRANS_1_A 0x7025c
> +#define _PLANE_WM_SAGV_TRANS_1_B 0x7125c
> +#define _PLANE_WM_SAGV_TRANS_2_A 0x7035c
> +#define _PLANE_WM_SAGV_TRANS_2_B 0x7135c
> +#define _PLANE_WM_SAGV_TRANS_1(pipe) _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
> +#define _PLANE_WM_SAGV_TRANS_2(pipe) _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
> +#define PLANE_WM_SAGV_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
>
> +#define _PLANE_WM_TRANS_1_A 0x70268
> +#define _PLANE_WM_TRANS_1_B 0x71268
> +#define _PLANE_WM_TRANS_2_A 0x70368
> +#define _PLANE_WM_TRANS_2_B 0x71368
> +#define _PLANE_WM_TRANS_1(pipe) _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
> +#define _PLANE_WM_TRANS_2(pipe) _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
> +#define PLANE_WM_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
> +
> +#define _PLANE_CHICKEN_1_A 0x7026c /* tgl+ */
> +#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
> +#define _PLANE_CHICKEN_2_A 0x7036c
> +#define _PLANE_CHICKEN_1_B 0x7126c
> +#define _PLANE_CHICKEN_2_B 0x7136c
> +#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B)
> +#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
> +#define PLANE_CHICKEN(pipe, plane) _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
> +
> +#define _PLANE_NV12_BUF_CFG_1_A 0x70278
> +#define _PLANE_NV12_BUF_CFG_2_A 0x70378
> +#define _PLANE_NV12_BUF_CFG_1_B 0x71278
> +#define _PLANE_NV12_BUF_CFG_2_B 0x71378
> +#define _PLANE_NV12_BUF_CFG_1(pipe) _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
> +#define _PLANE_NV12_BUF_CFG_2(pipe) _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
> +#define PLANE_NV12_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
> +
> +#define _PLANE_BUF_CFG_1_A 0x7027c
> +#define _PLANE_BUF_CFG_2_A 0x7037c
> +/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
> +#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
> +#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
> +#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
> +#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
> #define _PLANE_BUF_CFG_1_B 0x7127c
> #define _PLANE_BUF_CFG_2_B 0x7137c
> -#define _PLANE_BUF_CFG_1(pipe) \
> - _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
> -#define _PLANE_BUF_CFG_2(pipe) \
> - _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
> -#define PLANE_BUF_CFG(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
> -
> -#define _PLANE_NV12_BUF_CFG_1_B 0x71278
> -#define _PLANE_NV12_BUF_CFG_2_B 0x71378
> -#define _PLANE_NV12_BUF_CFG_1(pipe) \
> - _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
> -#define _PLANE_NV12_BUF_CFG_2(pipe) \
> - _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
> -#define PLANE_NV12_BUF_CFG(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
> +#define _PLANE_BUF_CFG_1(pipe) _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
> +#define _PLANE_BUF_CFG_2(pipe) _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
> +#define PLANE_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
>
> #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 10/16] drm/i915: Shuffle the skl+ plane register definitions
2024-05-13 11:28 ` Jani Nikula
@ 2024-05-13 16:13 ` Ville Syrjälä
0 siblings, 0 replies; 48+ messages in thread
From: Ville Syrjälä @ 2024-05-13 16:13 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Mon, May 13, 2024 at 02:28:11PM +0300, Jani Nikula wrote:
> On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Rearrange the plane skl+ universal plane register definitions:
> > - keep everything related to the same register in one place
> > - sort based on register offset
> > - unify the whitespace/etc a bit
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > .../i915/display/skl_universal_plane_regs.h | 502 ++++++++----------
> > 1 file changed, 207 insertions(+), 295 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > index 0558d97614e1..0ad14727e334 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > @@ -9,8 +9,6 @@
> > #include "intel_display_reg_defs.h"
> >
> > #define _PLANE_CTL_1_A 0x70180
> > -#define _PLANE_CTL_2_A 0x70280
> > -#define _PLANE_CTL_3_A 0x70380
> > #define PLANE_CTL_ENABLE REG_BIT(31)
> > #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
> > #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
> > @@ -74,59 +72,132 @@
> > #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
> > #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
> > #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
>
> This is a painful patch to review (in part because some newline removals
> throw off --color-moved) so I want to check something first.
>
> Shouldn't the above register *content* definitions be...
>
> > +#define _PLANE_CTL_2_A 0x70280
> > +#define _PLANE_CTL_1_B 0x71180
> > +#define _PLANE_CTL_2_B 0x71280
> > +#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
> > +#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
> > +#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
>
> ...here after all the register *offset* definitions, not right after the
> plane 1 / pipe A register offset macro? Ditto for a bunch of the other
> changes here.
Shrug. I don't think we have any real consistency in how these
things are laid out. Sometimes the bits are defined after the
_FOO_A, sometimes after all the _FOO_?, and sometimes after FOO().
I guess we should try to standardize on one of those. And I suppose
it should be that last option of those three (which is what you
suggest as well) since we don't always have any intermediate _FOO
defines at all. I can respin with that.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH v2 10/16] drm/i915: Shuffle the skl+ plane register definitions
2024-05-10 15:23 ` [PATCH 10/16] drm/i915: Shuffle the skl+ plane register definitions Ville Syrjala
2024-05-13 11:28 ` Jani Nikula
@ 2024-05-13 16:59 ` Ville Syrjala
2024-05-13 20:30 ` Jani Nikula
1 sibling, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2024-05-13 16:59 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rearrange the plane skl+ universal plane register definitions:
- keep everything related to the same register in one place
- sort based on register offset
- unify the whitespace/etc a bit
v2: Define register contents after all offsets (Jani)
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../i915/display/skl_universal_plane_regs.h | 481 ++++++++----------
1 file changed, 200 insertions(+), 281 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 49278584caa7..5fcd5898af4f 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -10,6 +10,11 @@
#define _PLANE_CTL_1_A 0x70180
#define _PLANE_CTL_2_A 0x70280
+#define _PLANE_CTL_1_B 0x71180
+#define _PLANE_CTL_2_B 0x71280
+#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
+#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
+#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
#define PLANE_CTL_ENABLE REG_BIT(31)
#define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
#define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
@@ -73,54 +78,132 @@
#define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
#define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
#define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
+
#define _PLANE_STRIDE_1_A 0x70188
#define _PLANE_STRIDE_2_A 0x70288
+#define _PLANE_STRIDE_1_B 0x71188
+#define _PLANE_STRIDE_2_B 0x71288
+#define _PLANE_STRIDE_1(pipe) _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
+#define _PLANE_STRIDE_2(pipe) _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
+#define PLANE_STRIDE(pipe, plane) _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
#define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
#define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
+
#define _PLANE_POS_1_A 0x7018c
#define _PLANE_POS_2_A 0x7028c
+#define _PLANE_POS_1_B 0x7118c
+#define _PLANE_POS_2_B 0x7128c
+#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
+#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
+#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
#define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
#define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
#define PLANE_POS_X_MASK REG_GENMASK(15, 0)
#define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
+
#define _PLANE_SIZE_1_A 0x70190
#define _PLANE_SIZE_2_A 0x70290
+#define _PLANE_SIZE_1_B 0x71190
+#define _PLANE_SIZE_2_B 0x71290
+#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
+#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
+#define PLANE_SIZE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
#define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
#define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
#define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
#define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
+
+#define _PLANE_KEYVAL_1_A 0x70194
+#define _PLANE_KEYVAL_2_A 0x70294
+#define _PLANE_KEYVAL_1_B 0x71194
+#define _PLANE_KEYVAL_2_B 0x71294
+#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
+#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
+#define PLANE_KEYVAL(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
+
+#define _PLANE_KEYMSK_1_A 0x70198
+#define _PLANE_KEYMSK_2_A 0x70298
+#define _PLANE_KEYMSK_1_B 0x71198
+#define _PLANE_KEYMSK_2_B 0x71298
+#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
+#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
+#define PLANE_KEYMSK(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
+#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31)
+
#define _PLANE_SURF_1_A 0x7019c
#define _PLANE_SURF_2_A 0x7029c
+#define _PLANE_SURF_1_B 0x7119c
+#define _PLANE_SURF_2_B 0x7129c
+#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
+#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
+#define PLANE_SURF(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
#define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
#define PLANE_SURF_DECRYPT REG_BIT(2)
+
+#define _PLANE_KEYMAX_1_A 0x701a0
+#define _PLANE_KEYMAX_2_A 0x702a0
+#define _PLANE_KEYMAX_1_B 0x711a0
+#define _PLANE_KEYMAX_2_B 0x712a0
+#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
+#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
+#define PLANE_KEYMAX(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
+#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24)
+#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a))
+
#define _PLANE_OFFSET_1_A 0x701a4
#define _PLANE_OFFSET_2_A 0x702a4
+#define _PLANE_OFFSET_1_B 0x711a4
+#define _PLANE_OFFSET_2_B 0x712a4
+#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
+#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
+#define PLANE_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
#define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
#define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
#define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
#define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))
-#define _PLANE_KEYVAL_1_A 0x70194
-#define _PLANE_KEYVAL_2_A 0x70294
-#define _PLANE_KEYMSK_1_A 0x70198
-#define _PLANE_KEYMSK_2_A 0x70298
-#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31)
-#define _PLANE_KEYMAX_1_A 0x701a0
-#define _PLANE_KEYMAX_2_A 0x702a0
-#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24)
-#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a))
+
#define _PLANE_SURFLIVE_1_A 0x701ac
#define _PLANE_SURFLIVE_2_A 0x702ac
+#define _PLANE_SURFLIVE_1_B 0x711ac
+#define _PLANE_SURFLIVE_2_B 0x712ac
+#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B)
+#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
+#define PLANE_SURFLIVE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
+
#define _PLANE_CC_VAL_1_A 0x701b4
#define _PLANE_CC_VAL_2_A 0x702b4
+#define _PLANE_CC_VAL_1_B 0x711b4
+#define _PLANE_CC_VAL_2_B 0x712b4
+#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
+#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
+#define PLANE_CC_VAL(pipe, plane, dw) _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
+
#define _PLANE_AUX_DIST_1_A 0x701c0
+#define _PLANE_AUX_DIST_2_A 0x702c0
+#define _PLANE_AUX_DIST_1_B 0x711c0
+#define _PLANE_AUX_DIST_2_B 0x712c0
+#define _PLANE_AUX_DIST_1(pipe) _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
+#define _PLANE_AUX_DIST_2(pipe) _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
+#define PLANE_AUX_DIST(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
#define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
#define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
#define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
-#define _PLANE_AUX_DIST_2_A 0x702c0
+
#define _PLANE_AUX_OFFSET_1_A 0x701c4
#define _PLANE_AUX_OFFSET_2_A 0x702c4
+#define _PLANE_AUX_OFFSET_1_B 0x711c4
+#define _PLANE_AUX_OFFSET_2_B 0x712c4
+#define _PLANE_AUX_OFFSET_1(pipe) _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
+#define _PLANE_AUX_OFFSET_2(pipe) _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
+#define PLANE_AUX_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
+
#define _PLANE_CUS_CTL_1_A 0x701c8
#define _PLANE_CUS_CTL_2_A 0x702c8
+#define _PLANE_CUS_CTL_1_B 0x711c8
+#define _PLANE_CUS_CTL_2_B 0x712c8
+#define _PLANE_CUS_CTL_1(pipe) _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
+#define _PLANE_CUS_CTL_2(pipe) _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
+#define PLANE_CUS_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
#define PLANE_CUS_ENABLE REG_BIT(31)
#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
#define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
@@ -137,8 +220,14 @@
#define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
#define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
#define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
-#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
-#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
+
+#define _PLANE_COLOR_CTL_1_A 0x701cc /* GLK+ */
+#define _PLANE_COLOR_CTL_2_A 0x702cc
+#define _PLANE_COLOR_CTL_1_B 0x711cc
+#define _PLANE_COLOR_CTL_2_B 0x712cc
+#define _PLANE_COLOR_CTL_1(pipe) _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
+#define _PLANE_COLOR_CTL_2(pipe) _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
+#define PLANE_COLOR_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
#define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
@@ -155,296 +244,126 @@
#define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
-#define _PLANE_CHICKEN_1_A 0x7026C /* tgl+ */
-#define _PLANE_CHICKEN_2_A 0x7036C /* tgl+ */
-#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
-#define _PLANE_BUF_CFG_1_A 0x7027c
-#define _PLANE_BUF_CFG_2_A 0x7037c
-/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
-#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
-#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
-#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
-#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
-#define _PLANE_NV12_BUF_CFG_1_A 0x70278
-#define _PLANE_NV12_BUF_CFG_2_A 0x70378
-#define _PLANE_CC_VAL_1_B 0x711b4
-#define _PLANE_CC_VAL_2_B 0x712b4
-#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
-#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
-#define PLANE_CC_VAL(pipe, plane, dw) \
- _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
-
-/* Input CSC Register Definitions */
-#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
-#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
-
-#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
-#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
-
-#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
- _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
- _PLANE_INPUT_CSC_RY_GY_1_B)
-#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
- _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
- _PLANE_INPUT_CSC_RY_GY_2_B)
-
-#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
- _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
-
-#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
-#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
-
-#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
-#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
-
-#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
- _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
- _PLANE_INPUT_CSC_PREOFF_HI_1_B)
-#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
- _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
- _PLANE_INPUT_CSC_PREOFF_HI_2_B)
-#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
- _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
+#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701e0
+#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702e0
+#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711e0
+#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712e0
+#define _PLANE_INPUT_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, _PLANE_INPUT_CSC_RY_GY_1_B)
+#define _PLANE_INPUT_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, _PLANE_INPUT_CSC_RY_GY_2_B)
+#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701f8
+#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702f8
+#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711f8
+#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712f8
+#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, _PLANE_INPUT_CSC_PREOFF_HI_1_B)
+#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, _PLANE_INPUT_CSC_PREOFF_HI_2_B)
+#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
-
#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
-
-#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
- _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
- _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
-#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
- _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
- _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
-#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
- _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
-
-#define _PLANE_CTL_1_B 0x71180
-#define _PLANE_CTL_2_B 0x71280
-#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
-#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
-#define PLANE_CTL(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
-
-#define _PLANE_STRIDE_1_B 0x71188
-#define _PLANE_STRIDE_2_B 0x71288
-#define _PLANE_STRIDE_1(pipe) \
- _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
-#define _PLANE_STRIDE_2(pipe) \
- _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
-#define PLANE_STRIDE(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
-
-#define _PLANE_POS_1_B 0x7118c
-#define _PLANE_POS_2_B 0x7128c
-#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
-#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
-#define PLANE_POS(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
-
-#define _PLANE_SIZE_1_B 0x71190
-#define _PLANE_SIZE_2_B 0x71290
-#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
-#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
-#define PLANE_SIZE(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
-
-#define _PLANE_SURF_1_B 0x7119c
-#define _PLANE_SURF_2_B 0x7129c
-#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
-#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
-#define PLANE_SURF(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
-
-#define _PLANE_OFFSET_1_B 0x711a4
-#define _PLANE_OFFSET_2_B 0x712a4
-#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
-#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
-#define PLANE_OFFSET(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
-
-#define _PLANE_KEYVAL_1_B 0x71194
-#define _PLANE_KEYVAL_2_B 0x71294
-#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
-#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
-#define PLANE_KEYVAL(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
-
-#define _PLANE_KEYMSK_1_B 0x71198
-#define _PLANE_KEYMSK_2_B 0x71298
-#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
-#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
-#define PLANE_KEYMSK(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
-
-#define _PLANE_KEYMAX_1_B 0x711a0
-#define _PLANE_KEYMAX_2_B 0x712a0
-#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
-#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
-#define PLANE_KEYMAX(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
-
-#define _PLANE_SURFLIVE_1_B 0x711ac
-#define _PLANE_SURFLIVE_2_B 0x712ac
-#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B)
-#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
-#define PLANE_SURFLIVE(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
-
-#define _PLANE_CHICKEN_1_B 0x7126c
-#define _PLANE_CHICKEN_2_B 0x7136c
-#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B)
-#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
-#define PLANE_CHICKEN(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
-
-#define _PLANE_AUX_DIST_1_B 0x711c0
-#define _PLANE_AUX_DIST_2_B 0x712c0
-#define _PLANE_AUX_DIST_1(pipe) \
- _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
-#define _PLANE_AUX_DIST_2(pipe) \
- _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
-#define PLANE_AUX_DIST(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
-
-#define _PLANE_AUX_OFFSET_1_B 0x711c4
-#define _PLANE_AUX_OFFSET_2_B 0x712c4
-#define _PLANE_AUX_OFFSET_1(pipe) \
- _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
-#define _PLANE_AUX_OFFSET_2(pipe) \
- _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
-#define PLANE_AUX_OFFSET(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
-
-#define _PLANE_CUS_CTL_1_B 0x711c8
-#define _PLANE_CUS_CTL_2_B 0x712c8
-#define _PLANE_CUS_CTL_1(pipe) \
- _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
-#define _PLANE_CUS_CTL_2(pipe) \
- _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
-#define PLANE_CUS_CTL(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
-
-#define _PLANE_COLOR_CTL_1_B 0x711CC
-#define _PLANE_COLOR_CTL_2_B 0x712CC
-#define _PLANE_COLOR_CTL_1(pipe) \
- _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
-#define _PLANE_COLOR_CTL_2(pipe) \
- _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
-#define PLANE_COLOR_CTL(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
-
-/* Plane CSC Registers */
-#define _PLANE_CSC_RY_GY_1_A 0x70210
-#define _PLANE_CSC_RY_GY_2_A 0x70310
-
-#define _PLANE_CSC_RY_GY_1_B 0x71210
-#define _PLANE_CSC_RY_GY_2_B 0x71310
-
-#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
- _PLANE_CSC_RY_GY_1_B)
-#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, \
- _PLANE_CSC_RY_GY_2_B)
-#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
- _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
- _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
+#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
+
+#define _PLANE_CSC_RY_GY_1_A 0x70210
+#define _PLANE_CSC_RY_GY_2_A 0x70310
+#define _PLANE_CSC_RY_GY_1_B 0x71210
+#define _PLANE_CSC_RY_GY_2_B 0x71310
+#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, _PLANE_CSC_RY_GY_1_B)
+#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, _PLANE_CSC_RY_GY_2_B)
+#define PLANE_CSC_COEFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
-
#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
-
-#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
- _PLANE_CSC_PREOFF_HI_1_B)
-#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
- _PLANE_CSC_PREOFF_HI_2_B)
-#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
- (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
- (index) * 4)
+#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, _PLANE_CSC_PREOFF_HI_1_B)
+#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, _PLANE_CSC_PREOFF_HI_2_B)
+#define PLANE_CSC_PREOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + (index) * 4)
#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
-
#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
+#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, _PLANE_CSC_POSTOFF_HI_1_B)
+#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, _PLANE_CSC_POSTOFF_HI_2_B)
+#define PLANE_CSC_POSTOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
-#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
- _PLANE_CSC_POSTOFF_HI_1_B)
-#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
- _PLANE_CSC_POSTOFF_HI_2_B)
-#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
- (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
- (index) * 4)
+#define _PLANE_WM_1_A_0 0x70240
+#define _PLANE_WM_1_B_0 0x71240
+#define _PLANE_WM_2_A_0 0x70340
+#define _PLANE_WM_2_B_0 0x71340
+#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
+#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
+#define _PLANE_WM_BASE(pipe, plane) _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
+#define PLANE_WM(pipe, plane, level) _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
+#define PLANE_WM_EN (1 << 31)
+#define PLANE_WM_IGNORE_LINES (1 << 30)
+#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
+#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
-#define _PLANE_WM_1_A_0 0x70240
-#define _PLANE_WM_1_B_0 0x71240
-#define _PLANE_WM_2_A_0 0x70340
-#define _PLANE_WM_2_B_0 0x71340
-#define _PLANE_WM_SAGV_1_A 0x70258
-#define _PLANE_WM_SAGV_1_B 0x71258
-#define _PLANE_WM_SAGV_2_A 0x70358
-#define _PLANE_WM_SAGV_2_B 0x71358
-#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C
-#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C
-#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C
-#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C
-#define _PLANE_WM_TRANS_1_A 0x70268
-#define _PLANE_WM_TRANS_1_B 0x71268
-#define _PLANE_WM_TRANS_2_A 0x70368
-#define _PLANE_WM_TRANS_2_B 0x71368
-#define PLANE_WM_EN (1 << 31)
-#define PLANE_WM_IGNORE_LINES (1 << 30)
-#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
-#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
+#define _PLANE_WM_SAGV_1_A 0x70258
+#define _PLANE_WM_SAGV_1_B 0x71258
+#define _PLANE_WM_SAGV_2_A 0x70358
+#define _PLANE_WM_SAGV_2_B 0x71358
+#define _PLANE_WM_SAGV_1(pipe) _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
+#define _PLANE_WM_SAGV_2(pipe) _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
+#define PLANE_WM_SAGV(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
-#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
-#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
-#define _PLANE_WM_BASE(pipe, plane) \
- _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
-#define PLANE_WM(pipe, plane, level) \
- _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
-#define _PLANE_WM_SAGV_1(pipe) \
- _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
-#define _PLANE_WM_SAGV_2(pipe) \
- _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
-#define PLANE_WM_SAGV(pipe, plane) \
- _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
-#define _PLANE_WM_SAGV_TRANS_1(pipe) \
- _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
-#define _PLANE_WM_SAGV_TRANS_2(pipe) \
- _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
-#define PLANE_WM_SAGV_TRANS(pipe, plane) \
- _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
-#define _PLANE_WM_TRANS_1(pipe) \
- _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
-#define _PLANE_WM_TRANS_2(pipe) \
- _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
-#define PLANE_WM_TRANS(pipe, plane) \
- _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
+#define _PLANE_WM_SAGV_TRANS_1_A 0x7025c
+#define _PLANE_WM_SAGV_TRANS_1_B 0x7125c
+#define _PLANE_WM_SAGV_TRANS_2_A 0x7035c
+#define _PLANE_WM_SAGV_TRANS_2_B 0x7135c
+#define _PLANE_WM_SAGV_TRANS_1(pipe) _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
+#define _PLANE_WM_SAGV_TRANS_2(pipe) _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
+#define PLANE_WM_SAGV_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
+#define _PLANE_WM_TRANS_1_A 0x70268
+#define _PLANE_WM_TRANS_1_B 0x71268
+#define _PLANE_WM_TRANS_2_A 0x70368
+#define _PLANE_WM_TRANS_2_B 0x71368
+#define _PLANE_WM_TRANS_1(pipe) _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
+#define _PLANE_WM_TRANS_2(pipe) _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
+#define PLANE_WM_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
+
+#define _PLANE_CHICKEN_1_A 0x7026c /* tgl+ */
+#define _PLANE_CHICKEN_2_A 0x7036c
+#define _PLANE_CHICKEN_1_B 0x7126c
+#define _PLANE_CHICKEN_2_B 0x7136c
+#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B)
+#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
+#define PLANE_CHICKEN(pipe, plane) _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
+#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
+
+#define _PLANE_NV12_BUF_CFG_1_A 0x70278
+#define _PLANE_NV12_BUF_CFG_2_A 0x70378
+#define _PLANE_NV12_BUF_CFG_1_B 0x71278
+#define _PLANE_NV12_BUF_CFG_2_B 0x71378
+#define _PLANE_NV12_BUF_CFG_1(pipe) _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
+#define _PLANE_NV12_BUF_CFG_2(pipe) _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
+#define PLANE_NV12_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
+
+#define _PLANE_BUF_CFG_1_A 0x7027c
+#define _PLANE_BUF_CFG_2_A 0x7037c
#define _PLANE_BUF_CFG_1_B 0x7127c
#define _PLANE_BUF_CFG_2_B 0x7137c
-#define _PLANE_BUF_CFG_1(pipe) \
- _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
-#define _PLANE_BUF_CFG_2(pipe) \
- _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
-#define PLANE_BUF_CFG(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
-
-#define _PLANE_NV12_BUF_CFG_1_B 0x71278
-#define _PLANE_NV12_BUF_CFG_2_B 0x71378
-#define _PLANE_NV12_BUF_CFG_1(pipe) \
- _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
-#define _PLANE_NV12_BUF_CFG_2(pipe) \
- _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
-#define PLANE_NV12_BUF_CFG(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
+#define _PLANE_BUF_CFG_1(pipe) _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
+#define _PLANE_BUF_CFG_2(pipe) _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
+#define PLANE_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
+/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
+#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
+#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
+#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
+#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
#endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* Re: [PATCH v2 10/16] drm/i915: Shuffle the skl+ plane register definitions
2024-05-13 16:59 ` [PATCH v2 " Ville Syrjala
@ 2024-05-13 20:30 ` Jani Nikula
0 siblings, 0 replies; 48+ messages in thread
From: Jani Nikula @ 2024-05-13 20:30 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Mon, 13 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rearrange the plane skl+ universal plane register definitions:
> - keep everything related to the same register in one place
> - sort based on register offset
> - unify the whitespace/etc a bit
>
> v2: Define register contents after all offsets (Jani)
Thanks for doing this.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> .../i915/display/skl_universal_plane_regs.h | 481 ++++++++----------
> 1 file changed, 200 insertions(+), 281 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> index 49278584caa7..5fcd5898af4f 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> @@ -10,6 +10,11 @@
>
> #define _PLANE_CTL_1_A 0x70180
> #define _PLANE_CTL_2_A 0x70280
> +#define _PLANE_CTL_1_B 0x71180
> +#define _PLANE_CTL_2_B 0x71280
> +#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
> +#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
> +#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
> #define PLANE_CTL_ENABLE REG_BIT(31)
> #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
> #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
> @@ -73,54 +78,132 @@
> #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
> #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
> #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
> +
> #define _PLANE_STRIDE_1_A 0x70188
> #define _PLANE_STRIDE_2_A 0x70288
> +#define _PLANE_STRIDE_1_B 0x71188
> +#define _PLANE_STRIDE_2_B 0x71288
> +#define _PLANE_STRIDE_1(pipe) _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
> +#define _PLANE_STRIDE_2(pipe) _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
> +#define PLANE_STRIDE(pipe, plane) _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
> #define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
> #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
> +
> #define _PLANE_POS_1_A 0x7018c
> #define _PLANE_POS_2_A 0x7028c
> +#define _PLANE_POS_1_B 0x7118c
> +#define _PLANE_POS_2_B 0x7128c
> +#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
> +#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
> +#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
> #define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
> #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
> #define PLANE_POS_X_MASK REG_GENMASK(15, 0)
> #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
> +
> #define _PLANE_SIZE_1_A 0x70190
> #define _PLANE_SIZE_2_A 0x70290
> +#define _PLANE_SIZE_1_B 0x71190
> +#define _PLANE_SIZE_2_B 0x71290
> +#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
> +#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
> +#define PLANE_SIZE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
> #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
> #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
> #define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
> #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
> +
> +#define _PLANE_KEYVAL_1_A 0x70194
> +#define _PLANE_KEYVAL_2_A 0x70294
> +#define _PLANE_KEYVAL_1_B 0x71194
> +#define _PLANE_KEYVAL_2_B 0x71294
> +#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
> +#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
> +#define PLANE_KEYVAL(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
> +
> +#define _PLANE_KEYMSK_1_A 0x70198
> +#define _PLANE_KEYMSK_2_A 0x70298
> +#define _PLANE_KEYMSK_1_B 0x71198
> +#define _PLANE_KEYMSK_2_B 0x71298
> +#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
> +#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
> +#define PLANE_KEYMSK(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
> +#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31)
> +
> #define _PLANE_SURF_1_A 0x7019c
> #define _PLANE_SURF_2_A 0x7029c
> +#define _PLANE_SURF_1_B 0x7119c
> +#define _PLANE_SURF_2_B 0x7129c
> +#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
> +#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
> +#define PLANE_SURF(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
> #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
> #define PLANE_SURF_DECRYPT REG_BIT(2)
> +
> +#define _PLANE_KEYMAX_1_A 0x701a0
> +#define _PLANE_KEYMAX_2_A 0x702a0
> +#define _PLANE_KEYMAX_1_B 0x711a0
> +#define _PLANE_KEYMAX_2_B 0x712a0
> +#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
> +#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
> +#define PLANE_KEYMAX(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
> +#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24)
> +#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a))
> +
> #define _PLANE_OFFSET_1_A 0x701a4
> #define _PLANE_OFFSET_2_A 0x702a4
> +#define _PLANE_OFFSET_1_B 0x711a4
> +#define _PLANE_OFFSET_2_B 0x712a4
> +#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
> +#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
> +#define PLANE_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
> #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
> #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
> #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
> #define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))
> -#define _PLANE_KEYVAL_1_A 0x70194
> -#define _PLANE_KEYVAL_2_A 0x70294
> -#define _PLANE_KEYMSK_1_A 0x70198
> -#define _PLANE_KEYMSK_2_A 0x70298
> -#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31)
> -#define _PLANE_KEYMAX_1_A 0x701a0
> -#define _PLANE_KEYMAX_2_A 0x702a0
> -#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24)
> -#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a))
> +
> #define _PLANE_SURFLIVE_1_A 0x701ac
> #define _PLANE_SURFLIVE_2_A 0x702ac
> +#define _PLANE_SURFLIVE_1_B 0x711ac
> +#define _PLANE_SURFLIVE_2_B 0x712ac
> +#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B)
> +#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
> +#define PLANE_SURFLIVE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
> +
> #define _PLANE_CC_VAL_1_A 0x701b4
> #define _PLANE_CC_VAL_2_A 0x702b4
> +#define _PLANE_CC_VAL_1_B 0x711b4
> +#define _PLANE_CC_VAL_2_B 0x712b4
> +#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
> +#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
> +#define PLANE_CC_VAL(pipe, plane, dw) _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
> +
> #define _PLANE_AUX_DIST_1_A 0x701c0
> +#define _PLANE_AUX_DIST_2_A 0x702c0
> +#define _PLANE_AUX_DIST_1_B 0x711c0
> +#define _PLANE_AUX_DIST_2_B 0x712c0
> +#define _PLANE_AUX_DIST_1(pipe) _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
> +#define _PLANE_AUX_DIST_2(pipe) _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
> +#define PLANE_AUX_DIST(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
> #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
> #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
> #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
> -#define _PLANE_AUX_DIST_2_A 0x702c0
> +
> #define _PLANE_AUX_OFFSET_1_A 0x701c4
> #define _PLANE_AUX_OFFSET_2_A 0x702c4
> +#define _PLANE_AUX_OFFSET_1_B 0x711c4
> +#define _PLANE_AUX_OFFSET_2_B 0x712c4
> +#define _PLANE_AUX_OFFSET_1(pipe) _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
> +#define _PLANE_AUX_OFFSET_2(pipe) _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
> +#define PLANE_AUX_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
> +
> #define _PLANE_CUS_CTL_1_A 0x701c8
> #define _PLANE_CUS_CTL_2_A 0x702c8
> +#define _PLANE_CUS_CTL_1_B 0x711c8
> +#define _PLANE_CUS_CTL_2_B 0x712c8
> +#define _PLANE_CUS_CTL_1(pipe) _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
> +#define _PLANE_CUS_CTL_2(pipe) _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
> +#define PLANE_CUS_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
> #define PLANE_CUS_ENABLE REG_BIT(31)
> #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
> #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
> @@ -137,8 +220,14 @@
> #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
> #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
> #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
> -#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
> -#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
> +
> +#define _PLANE_COLOR_CTL_1_A 0x701cc /* GLK+ */
> +#define _PLANE_COLOR_CTL_2_A 0x702cc
> +#define _PLANE_COLOR_CTL_1_B 0x711cc
> +#define _PLANE_COLOR_CTL_2_B 0x712cc
> +#define _PLANE_COLOR_CTL_1(pipe) _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
> +#define _PLANE_COLOR_CTL_2(pipe) _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
> +#define PLANE_COLOR_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
> #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
> #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
> #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
> @@ -155,296 +244,126 @@
> #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
> #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
> #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
> -#define _PLANE_CHICKEN_1_A 0x7026C /* tgl+ */
> -#define _PLANE_CHICKEN_2_A 0x7036C /* tgl+ */
> -#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
> -#define _PLANE_BUF_CFG_1_A 0x7027c
> -#define _PLANE_BUF_CFG_2_A 0x7037c
> -/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
> -#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
> -#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
> -#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
> -#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
> -#define _PLANE_NV12_BUF_CFG_1_A 0x70278
> -#define _PLANE_NV12_BUF_CFG_2_A 0x70378
>
> -#define _PLANE_CC_VAL_1_B 0x711b4
> -#define _PLANE_CC_VAL_2_B 0x712b4
> -#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
> -#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
> -#define PLANE_CC_VAL(pipe, plane, dw) \
> - _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
> -
> -/* Input CSC Register Definitions */
> -#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
> -#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
> -
> -#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
> -#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
> -
> -#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
> - _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
> - _PLANE_INPUT_CSC_RY_GY_1_B)
> -#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
> - _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
> - _PLANE_INPUT_CSC_RY_GY_2_B)
> -
> -#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
> - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
> - _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
> -
> -#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
> -#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
> -
> -#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
> -#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
> -
> -#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
> - _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
> - _PLANE_INPUT_CSC_PREOFF_HI_1_B)
> -#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
> - _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
> - _PLANE_INPUT_CSC_PREOFF_HI_2_B)
> -#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
> - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
> - _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
> +#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701e0
> +#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702e0
> +#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711e0
> +#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712e0
> +#define _PLANE_INPUT_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, _PLANE_INPUT_CSC_RY_GY_1_B)
> +#define _PLANE_INPUT_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, _PLANE_INPUT_CSC_RY_GY_2_B)
> +#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
> + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
> +
> +#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701f8
> +#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702f8
> +#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711f8
> +#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712f8
> +#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, _PLANE_INPUT_CSC_PREOFF_HI_1_B)
> +#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, _PLANE_INPUT_CSC_PREOFF_HI_2_B)
> +#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
> + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
>
> #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
> #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
> -
> #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
> #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
> -
> -#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
> - _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
> - _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
> -#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
> - _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
> - _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
> -#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
> - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
> - _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
> -
> -#define _PLANE_CTL_1_B 0x71180
> -#define _PLANE_CTL_2_B 0x71280
> -#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
> -#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
> -#define PLANE_CTL(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
> -
> -#define _PLANE_STRIDE_1_B 0x71188
> -#define _PLANE_STRIDE_2_B 0x71288
> -#define _PLANE_STRIDE_1(pipe) \
> - _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
> -#define _PLANE_STRIDE_2(pipe) \
> - _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
> -#define PLANE_STRIDE(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
> -
> -#define _PLANE_POS_1_B 0x7118c
> -#define _PLANE_POS_2_B 0x7128c
> -#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
> -#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
> -#define PLANE_POS(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
> -
> -#define _PLANE_SIZE_1_B 0x71190
> -#define _PLANE_SIZE_2_B 0x71290
> -#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
> -#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
> -#define PLANE_SIZE(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
> -
> -#define _PLANE_SURF_1_B 0x7119c
> -#define _PLANE_SURF_2_B 0x7129c
> -#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
> -#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
> -#define PLANE_SURF(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
> -
> -#define _PLANE_OFFSET_1_B 0x711a4
> -#define _PLANE_OFFSET_2_B 0x712a4
> -#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
> -#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
> -#define PLANE_OFFSET(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
> -
> -#define _PLANE_KEYVAL_1_B 0x71194
> -#define _PLANE_KEYVAL_2_B 0x71294
> -#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
> -#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
> -#define PLANE_KEYVAL(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
> -
> -#define _PLANE_KEYMSK_1_B 0x71198
> -#define _PLANE_KEYMSK_2_B 0x71298
> -#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
> -#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
> -#define PLANE_KEYMSK(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
> -
> -#define _PLANE_KEYMAX_1_B 0x711a0
> -#define _PLANE_KEYMAX_2_B 0x712a0
> -#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
> -#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
> -#define PLANE_KEYMAX(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
> -
> -#define _PLANE_SURFLIVE_1_B 0x711ac
> -#define _PLANE_SURFLIVE_2_B 0x712ac
> -#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B)
> -#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
> -#define PLANE_SURFLIVE(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
> -
> -#define _PLANE_CHICKEN_1_B 0x7126c
> -#define _PLANE_CHICKEN_2_B 0x7136c
> -#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B)
> -#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
> -#define PLANE_CHICKEN(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
> -
> -#define _PLANE_AUX_DIST_1_B 0x711c0
> -#define _PLANE_AUX_DIST_2_B 0x712c0
> -#define _PLANE_AUX_DIST_1(pipe) \
> - _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
> -#define _PLANE_AUX_DIST_2(pipe) \
> - _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
> -#define PLANE_AUX_DIST(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
> -
> -#define _PLANE_AUX_OFFSET_1_B 0x711c4
> -#define _PLANE_AUX_OFFSET_2_B 0x712c4
> -#define _PLANE_AUX_OFFSET_1(pipe) \
> - _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
> -#define _PLANE_AUX_OFFSET_2(pipe) \
> - _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
> -#define PLANE_AUX_OFFSET(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
> -
> -#define _PLANE_CUS_CTL_1_B 0x711c8
> -#define _PLANE_CUS_CTL_2_B 0x712c8
> -#define _PLANE_CUS_CTL_1(pipe) \
> - _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
> -#define _PLANE_CUS_CTL_2(pipe) \
> - _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
> -#define PLANE_CUS_CTL(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
> -
> -#define _PLANE_COLOR_CTL_1_B 0x711CC
> -#define _PLANE_COLOR_CTL_2_B 0x712CC
> -#define _PLANE_COLOR_CTL_1(pipe) \
> - _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
> -#define _PLANE_COLOR_CTL_2(pipe) \
> - _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
> -#define PLANE_COLOR_CTL(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
> -
> -/* Plane CSC Registers */
> -#define _PLANE_CSC_RY_GY_1_A 0x70210
> -#define _PLANE_CSC_RY_GY_2_A 0x70310
> -
> -#define _PLANE_CSC_RY_GY_1_B 0x71210
> -#define _PLANE_CSC_RY_GY_2_B 0x71310
> -
> -#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
> - _PLANE_CSC_RY_GY_1_B)
> -#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, \
> - _PLANE_CSC_RY_GY_2_B)
> -#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
> - _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
> - _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
> +#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
> + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
> +
> +#define _PLANE_CSC_RY_GY_1_A 0x70210
> +#define _PLANE_CSC_RY_GY_2_A 0x70310
> +#define _PLANE_CSC_RY_GY_1_B 0x71210
> +#define _PLANE_CSC_RY_GY_2_B 0x71310
> +#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, _PLANE_CSC_RY_GY_1_B)
> +#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, _PLANE_CSC_RY_GY_2_B)
> +#define PLANE_CSC_COEFF(pipe, plane, index) \
> + _MMIO_PLANE(plane, _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
>
> #define _PLANE_CSC_PREOFF_HI_1_A 0x70228
> #define _PLANE_CSC_PREOFF_HI_2_A 0x70328
> -
> #define _PLANE_CSC_PREOFF_HI_1_B 0x71228
> #define _PLANE_CSC_PREOFF_HI_2_B 0x71328
> -
> -#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
> - _PLANE_CSC_PREOFF_HI_1_B)
> -#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
> - _PLANE_CSC_PREOFF_HI_2_B)
> -#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
> - (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
> - (index) * 4)
> +#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, _PLANE_CSC_PREOFF_HI_1_B)
> +#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, _PLANE_CSC_PREOFF_HI_2_B)
> +#define PLANE_CSC_PREOFF(pipe, plane, index) \
> + _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + (index) * 4)
>
> #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
> #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
> -
> #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
> #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
> +#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, _PLANE_CSC_POSTOFF_HI_1_B)
> +#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, _PLANE_CSC_POSTOFF_HI_2_B)
> +#define PLANE_CSC_POSTOFF(pipe, plane, index) \
> + _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
>
> -#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
> - _PLANE_CSC_POSTOFF_HI_1_B)
> -#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
> - _PLANE_CSC_POSTOFF_HI_2_B)
> -#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
> - (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
> - (index) * 4)
> +#define _PLANE_WM_1_A_0 0x70240
> +#define _PLANE_WM_1_B_0 0x71240
> +#define _PLANE_WM_2_A_0 0x70340
> +#define _PLANE_WM_2_B_0 0x71340
> +#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
> +#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
> +#define _PLANE_WM_BASE(pipe, plane) _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
> +#define PLANE_WM(pipe, plane, level) _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
> +#define PLANE_WM_EN (1 << 31)
> +#define PLANE_WM_IGNORE_LINES (1 << 30)
> +#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
> +#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
>
> -#define _PLANE_WM_1_A_0 0x70240
> -#define _PLANE_WM_1_B_0 0x71240
> -#define _PLANE_WM_2_A_0 0x70340
> -#define _PLANE_WM_2_B_0 0x71340
> -#define _PLANE_WM_SAGV_1_A 0x70258
> -#define _PLANE_WM_SAGV_1_B 0x71258
> -#define _PLANE_WM_SAGV_2_A 0x70358
> -#define _PLANE_WM_SAGV_2_B 0x71358
> -#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C
> -#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C
> -#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C
> -#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C
> -#define _PLANE_WM_TRANS_1_A 0x70268
> -#define _PLANE_WM_TRANS_1_B 0x71268
> -#define _PLANE_WM_TRANS_2_A 0x70368
> -#define _PLANE_WM_TRANS_2_B 0x71368
> -#define PLANE_WM_EN (1 << 31)
> -#define PLANE_WM_IGNORE_LINES (1 << 30)
> -#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
> -#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
> +#define _PLANE_WM_SAGV_1_A 0x70258
> +#define _PLANE_WM_SAGV_1_B 0x71258
> +#define _PLANE_WM_SAGV_2_A 0x70358
> +#define _PLANE_WM_SAGV_2_B 0x71358
> +#define _PLANE_WM_SAGV_1(pipe) _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
> +#define _PLANE_WM_SAGV_2(pipe) _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
> +#define PLANE_WM_SAGV(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
>
> -#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
> -#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
> -#define _PLANE_WM_BASE(pipe, plane) \
> - _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
> -#define PLANE_WM(pipe, plane, level) \
> - _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
> -#define _PLANE_WM_SAGV_1(pipe) \
> - _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
> -#define _PLANE_WM_SAGV_2(pipe) \
> - _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
> -#define PLANE_WM_SAGV(pipe, plane) \
> - _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
> -#define _PLANE_WM_SAGV_TRANS_1(pipe) \
> - _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
> -#define _PLANE_WM_SAGV_TRANS_2(pipe) \
> - _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
> -#define PLANE_WM_SAGV_TRANS(pipe, plane) \
> - _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
> -#define _PLANE_WM_TRANS_1(pipe) \
> - _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
> -#define _PLANE_WM_TRANS_2(pipe) \
> - _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
> -#define PLANE_WM_TRANS(pipe, plane) \
> - _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
> +#define _PLANE_WM_SAGV_TRANS_1_A 0x7025c
> +#define _PLANE_WM_SAGV_TRANS_1_B 0x7125c
> +#define _PLANE_WM_SAGV_TRANS_2_A 0x7035c
> +#define _PLANE_WM_SAGV_TRANS_2_B 0x7135c
> +#define _PLANE_WM_SAGV_TRANS_1(pipe) _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
> +#define _PLANE_WM_SAGV_TRANS_2(pipe) _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
> +#define PLANE_WM_SAGV_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
>
> +#define _PLANE_WM_TRANS_1_A 0x70268
> +#define _PLANE_WM_TRANS_1_B 0x71268
> +#define _PLANE_WM_TRANS_2_A 0x70368
> +#define _PLANE_WM_TRANS_2_B 0x71368
> +#define _PLANE_WM_TRANS_1(pipe) _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
> +#define _PLANE_WM_TRANS_2(pipe) _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
> +#define PLANE_WM_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
> +
> +#define _PLANE_CHICKEN_1_A 0x7026c /* tgl+ */
> +#define _PLANE_CHICKEN_2_A 0x7036c
> +#define _PLANE_CHICKEN_1_B 0x7126c
> +#define _PLANE_CHICKEN_2_B 0x7136c
> +#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B)
> +#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
> +#define PLANE_CHICKEN(pipe, plane) _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
> +#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
> +
> +#define _PLANE_NV12_BUF_CFG_1_A 0x70278
> +#define _PLANE_NV12_BUF_CFG_2_A 0x70378
> +#define _PLANE_NV12_BUF_CFG_1_B 0x71278
> +#define _PLANE_NV12_BUF_CFG_2_B 0x71378
> +#define _PLANE_NV12_BUF_CFG_1(pipe) _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
> +#define _PLANE_NV12_BUF_CFG_2(pipe) _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
> +#define PLANE_NV12_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
> +
> +#define _PLANE_BUF_CFG_1_A 0x7027c
> +#define _PLANE_BUF_CFG_2_A 0x7037c
> #define _PLANE_BUF_CFG_1_B 0x7127c
> #define _PLANE_BUF_CFG_2_B 0x7137c
> -#define _PLANE_BUF_CFG_1(pipe) \
> - _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
> -#define _PLANE_BUF_CFG_2(pipe) \
> - _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
> -#define PLANE_BUF_CFG(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
> -
> -#define _PLANE_NV12_BUF_CFG_1_B 0x71278
> -#define _PLANE_NV12_BUF_CFG_2_B 0x71378
> -#define _PLANE_NV12_BUF_CFG_1(pipe) \
> - _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
> -#define _PLANE_NV12_BUF_CFG_2(pipe) \
> - _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
> -#define PLANE_NV12_BUF_CFG(pipe, plane) \
> - _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
> +#define _PLANE_BUF_CFG_1(pipe) _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
> +#define _PLANE_BUF_CFG_2(pipe) _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
> +#define PLANE_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
> +/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
> +#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
> +#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
> +#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
> +#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
>
> #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 11/16] drm/i915: Use REG_BIT for PLANE_WM bits
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
` (9 preceding siblings ...)
2024-05-10 15:23 ` [PATCH 10/16] drm/i915: Shuffle the skl+ plane register definitions Ville Syrjala
@ 2024-05-10 15:23 ` Ville Syrjala
2024-05-13 10:38 ` Jani Nikula
2024-05-13 16:59 ` [PATCH v2 " Ville Syrjala
2024-05-10 15:23 ` [PATCH 12/16] drm/i915: Drop a few unwanted tabs from skl+ plane reg defines Ville Syrjala
` (10 subsequent siblings)
21 siblings, 2 replies; 48+ messages in thread
From: Ville Syrjala @ 2024-05-10 15:23 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
A couple of PLANE_WM bits were still using the hand
rolled (1<<N) form. Replace with REG_BIT().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 0ad14727e334..8ef9bd50d021 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -300,8 +300,8 @@
_MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
#define _PLANE_WM_1_A_0 0x70240
-#define PLANE_WM_EN (1 << 31)
-#define PLANE_WM_IGNORE_LINES (1 << 30)
+#define PLANE_WM_EN REG_BIT(31)
+#define PLANE_WM_IGNORE_LINES REG_BIT(30)
#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
#define _PLANE_WM_1_B_0 0x71240
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 11/16] drm/i915: Use REG_BIT for PLANE_WM bits
2024-05-10 15:23 ` [PATCH 11/16] drm/i915: Use REG_BIT for PLANE_WM bits Ville Syrjala
@ 2024-05-13 10:38 ` Jani Nikula
2024-05-13 16:59 ` [PATCH v2 " Ville Syrjala
1 sibling, 0 replies; 48+ messages in thread
From: Jani Nikula @ 2024-05-13 10:38 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> A couple of PLANE_WM bits were still using the hand
> rolled (1<<N) form. Replace with REG_BIT().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> index 0ad14727e334..8ef9bd50d021 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> @@ -300,8 +300,8 @@
> _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
>
> #define _PLANE_WM_1_A_0 0x70240
> -#define PLANE_WM_EN (1 << 31)
> -#define PLANE_WM_IGNORE_LINES (1 << 30)
> +#define PLANE_WM_EN REG_BIT(31)
> +#define PLANE_WM_IGNORE_LINES REG_BIT(30)
> #define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
> #define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
> #define _PLANE_WM_1_B_0 0x71240
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH v2 11/16] drm/i915: Use REG_BIT for PLANE_WM bits
2024-05-10 15:23 ` [PATCH 11/16] drm/i915: Use REG_BIT for PLANE_WM bits Ville Syrjala
2024-05-13 10:38 ` Jani Nikula
@ 2024-05-13 16:59 ` Ville Syrjala
1 sibling, 0 replies; 48+ messages in thread
From: Ville Syrjala @ 2024-05-13 16:59 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
A couple of PLANE_WM bits were still using the hand
rolled (1<<N) form. Replace with REG_BIT().
v2: Rebase
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 5fcd5898af4f..e8d399592fd3 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -307,8 +307,8 @@
#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
#define _PLANE_WM_BASE(pipe, plane) _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
#define PLANE_WM(pipe, plane, level) _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
-#define PLANE_WM_EN (1 << 31)
-#define PLANE_WM_IGNORE_LINES (1 << 30)
+#define PLANE_WM_EN REG_BIT(31)
+#define PLANE_WM_IGNORE_LINES REG_BIT(30)
#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0)
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 12/16] drm/i915: Drop a few unwanted tabs from skl+ plane reg defines
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
` (10 preceding siblings ...)
2024-05-10 15:23 ` [PATCH 11/16] drm/i915: Use REG_BIT for PLANE_WM bits Ville Syrjala
@ 2024-05-10 15:23 ` Ville Syrjala
2024-05-13 10:40 ` Jani Nikula
2024-05-13 17:00 ` [PATCH v2 " Ville Syrjala
2024-05-10 15:23 ` [PATCH 13/16] drm/i915: Refactor skl+ plane register offset calculations Ville Syrjala
` (9 subsequent siblings)
21 siblings, 2 replies; 48+ messages in thread
From: Ville Syrjala @ 2024-05-10 15:23 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
A few extra tabs have snuck into the skl+ plane register bit
definitions. Remove them.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 8ef9bd50d021..18dbe717ea21 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -199,17 +199,17 @@
#define _PLANE_CUS_CTL_1_A 0x701c8
#define PLANE_CUS_ENABLE REG_BIT(31)
-#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
+#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
#define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
#define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
#define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
#define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
-#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
+#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
#define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16)
#define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
#define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
#define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
-#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
+#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
#define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12)
#define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
#define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 12/16] drm/i915: Drop a few unwanted tabs from skl+ plane reg defines
2024-05-10 15:23 ` [PATCH 12/16] drm/i915: Drop a few unwanted tabs from skl+ plane reg defines Ville Syrjala
@ 2024-05-13 10:40 ` Jani Nikula
2024-05-13 17:00 ` [PATCH v2 " Ville Syrjala
1 sibling, 0 replies; 48+ messages in thread
From: Jani Nikula @ 2024-05-13 10:40 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> A few extra tabs have snuck into the skl+ plane register bit
> definitions. Remove them.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> index 8ef9bd50d021..18dbe717ea21 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> @@ -199,17 +199,17 @@
>
> #define _PLANE_CUS_CTL_1_A 0x701c8
> #define PLANE_CUS_ENABLE REG_BIT(31)
> -#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
> +#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
> #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
> #define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
> #define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
> #define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
> -#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
> +#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
> #define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16)
> #define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
> #define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
> #define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
> -#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
> +#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
> #define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12)
> #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
> #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH v2 12/16] drm/i915: Drop a few unwanted tabs from skl+ plane reg defines
2024-05-10 15:23 ` [PATCH 12/16] drm/i915: Drop a few unwanted tabs from skl+ plane reg defines Ville Syrjala
2024-05-13 10:40 ` Jani Nikula
@ 2024-05-13 17:00 ` Ville Syrjala
1 sibling, 0 replies; 48+ messages in thread
From: Ville Syrjala @ 2024-05-13 17:00 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
A few extra tabs have snuck into the skl+ plane register bit
definitions. Remove them.
v2: Rebase
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index e8d399592fd3..0b4f97059479 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -205,17 +205,17 @@
#define _PLANE_CUS_CTL_2(pipe) _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
#define PLANE_CUS_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
#define PLANE_CUS_ENABLE REG_BIT(31)
-#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
+#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
#define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
#define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
#define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
#define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
-#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
+#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
#define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16)
#define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
#define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
#define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
-#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
+#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
#define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12)
#define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
#define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 13/16] drm/i915: Refactor skl+ plane register offset calculations
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
` (11 preceding siblings ...)
2024-05-10 15:23 ` [PATCH 12/16] drm/i915: Drop a few unwanted tabs from skl+ plane reg defines Ville Syrjala
@ 2024-05-10 15:23 ` Ville Syrjala
2024-05-13 17:00 ` [PATCH v2 " Ville Syrjala
2024-05-10 15:23 ` [PATCH 14/16] drm/i915: Extract skl_plane_{wm,ddb}_reg_val() Ville Syrjala
` (8 subsequent siblings)
21 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2024-05-10 15:23 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Currentluy every skl+ plane register defines some intermediate
macros to calculate the final register offset. Pull all of that
into common macros, simplifying the final register offset stuff
into just five defines:
- raw register offsets for the planes 1 and 2 on pipes A and B
- the final parametrized macro
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../i915/display/skl_universal_plane_regs.h | 186 +++++++++---------
1 file changed, 93 insertions(+), 93 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 18dbe717ea21..07bcdf4e195d 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -8,6 +8,15 @@
#include "intel_display_reg_defs.h"
+#define _SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
+ _PLANE((plane), _PIPE((pipe), (reg_1_a), (reg_1_b)), _PIPE((pipe), (reg_2_a), (reg_2_b)))
+#define _SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
+ (_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)) + (dw) * 4)
+#define _MMIO_SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
+ _MMIO(_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))
+#define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
+ _MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))
+
#define _PLANE_CTL_1_A 0x70180
#define PLANE_CTL_ENABLE REG_BIT(31)
#define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
@@ -75,9 +84,9 @@
#define _PLANE_CTL_2_A 0x70280
#define _PLANE_CTL_1_B 0x71180
#define _PLANE_CTL_2_B 0x71280
-#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
-#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
-#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
+#define PLANE_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_CTL_1_A, _PLANE_CTL_1_B, \
+ _PLANE_CTL_2_A, _PLANE_CTL_2_B)
#define _PLANE_STRIDE_1_A 0x70188
#define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
@@ -85,10 +94,9 @@
#define _PLANE_STRIDE_2_A 0x70288
#define _PLANE_STRIDE_1_B 0x71188
#define _PLANE_STRIDE_2_B 0x71288
-#define _PLANE_STRIDE_1(pipe) _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
-#define _PLANE_STRIDE_2(pipe) _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
-#define PLANE_STRIDE(pipe, plane) _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
-
+#define PLANE_STRIDE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B, \
+ _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
#define _PLANE_POS_1_A 0x7018c
#define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
#define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
@@ -97,9 +105,9 @@
#define _PLANE_POS_2_A 0x7028c
#define _PLANE_POS_1_B 0x7118c
#define _PLANE_POS_2_B 0x7128c
-#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
-#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
-#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
+#define PLANE_POS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_POS_1_A, _PLANE_POS_1_B, \
+ _PLANE_POS_2_A, _PLANE_POS_2_B)
#define _PLANE_SIZE_1_A 0x70190
#define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
@@ -109,26 +117,26 @@
#define _PLANE_SIZE_2_A 0x70290
#define _PLANE_SIZE_1_B 0x71190
#define _PLANE_SIZE_2_B 0x71290
-#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
-#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
-#define PLANE_SIZE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
+#define PLANE_SIZE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_SIZE_1_A, _PLANE_SIZE_1_B, \
+ _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
#define _PLANE_KEYVAL_1_A 0x70194
#define _PLANE_KEYVAL_2_A 0x70294
#define _PLANE_KEYVAL_1_B 0x71194
#define _PLANE_KEYVAL_2_B 0x71294
-#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
-#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
-#define PLANE_KEYVAL(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
+#define PLANE_KEYVAL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane),\
+ _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B, \
+ _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
#define _PLANE_KEYMSK_1_A 0x70198
#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31)
#define _PLANE_KEYMSK_2_A 0x70298
#define _PLANE_KEYMSK_1_B 0x71198
#define _PLANE_KEYMSK_2_B 0x71298
-#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
-#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
-#define PLANE_KEYMSK(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
+#define PLANE_KEYMSK(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B, \
+ _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
#define _PLANE_SURF_1_A 0x7019c
#define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
@@ -136,9 +144,9 @@
#define _PLANE_SURF_2_A 0x7029c
#define _PLANE_SURF_1_B 0x7119c
#define _PLANE_SURF_2_B 0x7129c
-#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
-#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
-#define PLANE_SURF(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+#define PLANE_SURF(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_SURF_1_A, _PLANE_SURF_1_B, \
+ _PLANE_SURF_2_A, _PLANE_SURF_2_B)
#define _PLANE_KEYMAX_1_A 0x701a0
#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24)
@@ -146,9 +154,9 @@
#define _PLANE_KEYMAX_2_A 0x702a0
#define _PLANE_KEYMAX_1_B 0x711a0
#define _PLANE_KEYMAX_2_B 0x712a0
-#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
-#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
-#define PLANE_KEYMAX(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
+#define PLANE_KEYMAX(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B, \
+ _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
#define _PLANE_OFFSET_1_A 0x701a4
#define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
@@ -158,25 +166,25 @@
#define _PLANE_OFFSET_2_A 0x702a4
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
-#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
-#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
-#define PLANE_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
+#define PLANE_OFFSET(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B, \
+ _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
#define _PLANE_SURFLIVE_1_A 0x701ac
#define _PLANE_SURFLIVE_2_A 0x702ac
#define _PLANE_SURFLIVE_1_B 0x711ac
#define _PLANE_SURFLIVE_2_B 0x712ac
-#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B)
-#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
-#define PLANE_SURFLIVE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
+#define PLANE_SURFLIVE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B, \
+ _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
#define _PLANE_CC_VAL_1_A 0x701b4
#define _PLANE_CC_VAL_2_A 0x702b4
#define _PLANE_CC_VAL_1_B 0x711b4
#define _PLANE_CC_VAL_2_B 0x712b4
-#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
-#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
-#define PLANE_CC_VAL(pipe, plane, dw) _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
+#define PLANE_CC_VAL(pipe, plane, dw) _MMIO_SKL_PLANE_DW((pipe), (plane), (dw), \
+ _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B, \
+ _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
#define _PLANE_AUX_DIST_1_A 0x701c0
#define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
@@ -185,17 +193,17 @@
#define _PLANE_AUX_DIST_2_A 0x702c0
#define _PLANE_AUX_DIST_1_B 0x711c0
#define _PLANE_AUX_DIST_2_B 0x712c0
-#define _PLANE_AUX_DIST_1(pipe) _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
-#define _PLANE_AUX_DIST_2(pipe) _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
-#define PLANE_AUX_DIST(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
+#define PLANE_AUX_DIST(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B, \
+ _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
#define _PLANE_AUX_OFFSET_1_A 0x701c4
#define _PLANE_AUX_OFFSET_2_A 0x702c4
#define _PLANE_AUX_OFFSET_1_B 0x711c4
#define _PLANE_AUX_OFFSET_2_B 0x712c4
-#define _PLANE_AUX_OFFSET_1(pipe) _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
-#define _PLANE_AUX_OFFSET_2(pipe) _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
-#define PLANE_AUX_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
+#define PLANE_AUX_OFFSET(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B, \
+ _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
#define _PLANE_CUS_CTL_1_A 0x701c8
#define PLANE_CUS_ENABLE REG_BIT(31)
@@ -217,9 +225,9 @@
#define _PLANE_CUS_CTL_2_A 0x702c8
#define _PLANE_CUS_CTL_1_B 0x711c8
#define _PLANE_CUS_CTL_2_B 0x712c8
-#define _PLANE_CUS_CTL_1(pipe) _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
-#define _PLANE_CUS_CTL_2(pipe) _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
-#define PLANE_CUS_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
+#define PLANE_CUS_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B, \
+ _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
#define _PLANE_COLOR_CTL_1_A 0x701cc /* GLK+ */
#define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
@@ -241,64 +249,57 @@
#define _PLANE_COLOR_CTL_2_A 0x702cc
#define _PLANE_COLOR_CTL_1_B 0x711cc
#define _PLANE_COLOR_CTL_2_B 0x712cc
-#define _PLANE_COLOR_CTL_1(pipe) _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
-#define _PLANE_COLOR_CTL_2(pipe) _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
-#define PLANE_COLOR_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
+#define PLANE_COLOR_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B, \
+ _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701e0
#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702e0
#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711e0
#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712e0
-#define _PLANE_INPUT_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, _PLANE_INPUT_CSC_RY_GY_1_B)
-#define _PLANE_INPUT_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, _PLANE_INPUT_CSC_RY_GY_2_B)
-#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
+#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
+ _PLANE_INPUT_CSC_RY_GY_1_A, _PLANE_INPUT_CSC_RY_GY_1_B, \
+ _PLANE_INPUT_CSC_RY_GY_2_A, _PLANE_INPUT_CSC_RY_GY_2_B)
#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701f8
#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702f8
#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711f8
#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712f8
-#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, _PLANE_INPUT_CSC_PREOFF_HI_1_B)
-#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, _PLANE_INPUT_CSC_PREOFF_HI_2_B)
-#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
+#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
+ _PLANE_INPUT_CSC_PREOFF_HI_1_A, _PLANE_INPUT_CSC_PREOFF_HI_1_B, \
+ _PLANE_INPUT_CSC_PREOFF_HI_2_A, _PLANE_INPUT_CSC_PREOFF_HI_2_B)
#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
-#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
-#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
-#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
+#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
+ _PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B, \
+ _PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
#define _PLANE_CSC_RY_GY_1_A 0x70210
#define _PLANE_CSC_RY_GY_2_A 0x70310
#define _PLANE_CSC_RY_GY_1_B 0x71210
#define _PLANE_CSC_RY_GY_2_B 0x71310
-#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, _PLANE_CSC_RY_GY_1_B)
-#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, _PLANE_CSC_RY_GY_2_B)
-#define PLANE_CSC_COEFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
+#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
+ _PLANE_CSC_RY_GY_1_A, _PLANE_CSC_RY_GY_1_B, \
+ _PLANE_CSC_RY_GY_2_A, _PLANE_CSC_RY_GY_2_B)
#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
-#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, _PLANE_CSC_PREOFF_HI_1_B)
-#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, _PLANE_CSC_PREOFF_HI_2_B)
-#define PLANE_CSC_PREOFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + (index) * 4)
+#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
+ _PLANE_CSC_PREOFF_HI_1_A, _PLANE_CSC_PREOFF_HI_1_B, \
+ _PLANE_CSC_PREOFF_HI_2_A, _PLANE_CSC_PREOFF_HI_2_B)
#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
-#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, _PLANE_CSC_POSTOFF_HI_1_B)
-#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, _PLANE_CSC_POSTOFF_HI_2_B)
-#define PLANE_CSC_POSTOFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
-
+#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
+ _PLANE_CSC_POSTOFF_HI_1_A, _PLANE_CSC_POSTOFF_HI_1_B, \
+ _PLANE_CSC_POSTOFF_HI_2_A, _PLANE_CSC_POSTOFF_HI_2_B)
#define _PLANE_WM_1_A_0 0x70240
#define PLANE_WM_EN REG_BIT(31)
#define PLANE_WM_IGNORE_LINES REG_BIT(30)
@@ -307,51 +308,50 @@
#define _PLANE_WM_1_B_0 0x71240
#define _PLANE_WM_2_A_0 0x70340
#define _PLANE_WM_2_B_0 0x71340
-#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
-#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
-#define _PLANE_WM_BASE(pipe, plane) _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
-#define PLANE_WM(pipe, plane, level) _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
+#define PLANE_WM(pipe, plane, level) _MMIO_SKL_PLANE_DW((pipe), (plane), (level), \
+ _PLANE_WM_1_A_0, _PLANE_WM_1_B_0, \
+ _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
#define _PLANE_WM_SAGV_1_A 0x70258
#define _PLANE_WM_SAGV_1_B 0x71258
#define _PLANE_WM_SAGV_2_A 0x70358
#define _PLANE_WM_SAGV_2_B 0x71358
-#define _PLANE_WM_SAGV_1(pipe) _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
-#define _PLANE_WM_SAGV_2(pipe) _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
-#define PLANE_WM_SAGV(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
+#define PLANE_WM_SAGV(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B, \
+ _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
#define _PLANE_WM_SAGV_TRANS_1_A 0x7025c
#define _PLANE_WM_SAGV_TRANS_1_B 0x7125c
#define _PLANE_WM_SAGV_TRANS_2_A 0x7035c
#define _PLANE_WM_SAGV_TRANS_2_B 0x7135c
-#define _PLANE_WM_SAGV_TRANS_1(pipe) _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
-#define _PLANE_WM_SAGV_TRANS_2(pipe) _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
-#define PLANE_WM_SAGV_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
+#define PLANE_WM_SAGV_TRANS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B, \
+ _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
#define _PLANE_WM_TRANS_1_A 0x70268
#define _PLANE_WM_TRANS_1_B 0x71268
#define _PLANE_WM_TRANS_2_A 0x70368
#define _PLANE_WM_TRANS_2_B 0x71368
-#define _PLANE_WM_TRANS_1(pipe) _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
-#define _PLANE_WM_TRANS_2(pipe) _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
-#define PLANE_WM_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
+#define PLANE_WM_TRANS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B, \
+ _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
#define _PLANE_CHICKEN_1_A 0x7026c /* tgl+ */
#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
#define _PLANE_CHICKEN_2_A 0x7036c
#define _PLANE_CHICKEN_1_B 0x7126c
#define _PLANE_CHICKEN_2_B 0x7136c
-#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B)
-#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
-#define PLANE_CHICKEN(pipe, plane) _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
+#define PLANE_CHICKEN(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B, \
+ _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
#define _PLANE_NV12_BUF_CFG_1_A 0x70278
#define _PLANE_NV12_BUF_CFG_2_A 0x70378
#define _PLANE_NV12_BUF_CFG_1_B 0x71278
#define _PLANE_NV12_BUF_CFG_2_B 0x71378
-#define _PLANE_NV12_BUF_CFG_1(pipe) _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
-#define _PLANE_NV12_BUF_CFG_2(pipe) _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
-#define PLANE_NV12_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
+#define PLANE_NV12_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B, \
+ _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
#define _PLANE_BUF_CFG_1_A 0x7027c
#define _PLANE_BUF_CFG_2_A 0x7037c
@@ -362,8 +362,8 @@
#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
#define _PLANE_BUF_CFG_1_B 0x7127c
#define _PLANE_BUF_CFG_2_B 0x7137c
-#define _PLANE_BUF_CFG_1(pipe) _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
-#define _PLANE_BUF_CFG_2(pipe) _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
-#define PLANE_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
+#define PLANE_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B, \
+ _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
#endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* [PATCH v2 13/16] drm/i915: Refactor skl+ plane register offset calculations
2024-05-10 15:23 ` [PATCH 13/16] drm/i915: Refactor skl+ plane register offset calculations Ville Syrjala
@ 2024-05-13 17:00 ` Ville Syrjala
2024-05-13 20:41 ` Jani Nikula
0 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2024-05-13 17:00 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Currentluy every skl+ plane register defines some intermediate
macros to calculate the final register offset. Pull all of that
into common macros, simplifying the final register offset stuff
into just five defines:
- raw register offsets for the planes 1 and 2 on pipes A and B
- the final parametrized macro
v2: Rebase
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../i915/display/skl_universal_plane_regs.h | 185 +++++++++---------
1 file changed, 93 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 0b4f97059479..cb3bdd71b6b2 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -8,13 +8,22 @@
#include "intel_display_reg_defs.h"
+#define _SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
+ _PLANE((plane), _PIPE((pipe), (reg_1_a), (reg_1_b)), _PIPE((pipe), (reg_2_a), (reg_2_b)))
+#define _SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
+ (_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)) + (dw) * 4)
+#define _MMIO_SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
+ _MMIO(_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))
+#define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
+ _MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))
+
#define _PLANE_CTL_1_A 0x70180
#define _PLANE_CTL_2_A 0x70280
#define _PLANE_CTL_1_B 0x71180
#define _PLANE_CTL_2_B 0x71280
-#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
-#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
-#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
+#define PLANE_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_CTL_1_A, _PLANE_CTL_1_B, \
+ _PLANE_CTL_2_A, _PLANE_CTL_2_B)
#define PLANE_CTL_ENABLE REG_BIT(31)
#define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
#define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
@@ -83,9 +92,9 @@
#define _PLANE_STRIDE_2_A 0x70288
#define _PLANE_STRIDE_1_B 0x71188
#define _PLANE_STRIDE_2_B 0x71288
-#define _PLANE_STRIDE_1(pipe) _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
-#define _PLANE_STRIDE_2(pipe) _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
-#define PLANE_STRIDE(pipe, plane) _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
+#define PLANE_STRIDE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B, \
+ _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
#define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
#define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
@@ -93,9 +102,9 @@
#define _PLANE_POS_2_A 0x7028c
#define _PLANE_POS_1_B 0x7118c
#define _PLANE_POS_2_B 0x7128c
-#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
-#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
-#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
+#define PLANE_POS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_POS_1_A, _PLANE_POS_1_B, \
+ _PLANE_POS_2_A, _PLANE_POS_2_B)
#define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
#define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
#define PLANE_POS_X_MASK REG_GENMASK(15, 0)
@@ -105,9 +114,9 @@
#define _PLANE_SIZE_2_A 0x70290
#define _PLANE_SIZE_1_B 0x71190
#define _PLANE_SIZE_2_B 0x71290
-#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
-#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
-#define PLANE_SIZE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
+#define PLANE_SIZE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_SIZE_1_A, _PLANE_SIZE_1_B, \
+ _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
#define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
#define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
#define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
@@ -117,26 +126,26 @@
#define _PLANE_KEYVAL_2_A 0x70294
#define _PLANE_KEYVAL_1_B 0x71194
#define _PLANE_KEYVAL_2_B 0x71294
-#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
-#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
-#define PLANE_KEYVAL(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
+#define PLANE_KEYVAL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane),\
+ _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B, \
+ _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
#define _PLANE_KEYMSK_1_A 0x70198
#define _PLANE_KEYMSK_2_A 0x70298
#define _PLANE_KEYMSK_1_B 0x71198
#define _PLANE_KEYMSK_2_B 0x71298
-#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
-#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
-#define PLANE_KEYMSK(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
+#define PLANE_KEYMSK(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B, \
+ _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31)
#define _PLANE_SURF_1_A 0x7019c
#define _PLANE_SURF_2_A 0x7029c
#define _PLANE_SURF_1_B 0x7119c
#define _PLANE_SURF_2_B 0x7129c
-#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
-#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
-#define PLANE_SURF(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+#define PLANE_SURF(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_SURF_1_A, _PLANE_SURF_1_B, \
+ _PLANE_SURF_2_A, _PLANE_SURF_2_B)
#define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
#define PLANE_SURF_DECRYPT REG_BIT(2)
@@ -144,9 +153,9 @@
#define _PLANE_KEYMAX_2_A 0x702a0
#define _PLANE_KEYMAX_1_B 0x711a0
#define _PLANE_KEYMAX_2_B 0x712a0
-#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
-#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
-#define PLANE_KEYMAX(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
+#define PLANE_KEYMAX(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B, \
+ _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24)
#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a))
@@ -154,9 +163,9 @@
#define _PLANE_OFFSET_2_A 0x702a4
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
-#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
-#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
-#define PLANE_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
+#define PLANE_OFFSET(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B, \
+ _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
#define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
#define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
#define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
@@ -166,25 +175,25 @@
#define _PLANE_SURFLIVE_2_A 0x702ac
#define _PLANE_SURFLIVE_1_B 0x711ac
#define _PLANE_SURFLIVE_2_B 0x712ac
-#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B)
-#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
-#define PLANE_SURFLIVE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
+#define PLANE_SURFLIVE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B, \
+ _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
#define _PLANE_CC_VAL_1_A 0x701b4
#define _PLANE_CC_VAL_2_A 0x702b4
#define _PLANE_CC_VAL_1_B 0x711b4
#define _PLANE_CC_VAL_2_B 0x712b4
-#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
-#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
-#define PLANE_CC_VAL(pipe, plane, dw) _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
+#define PLANE_CC_VAL(pipe, plane, dw) _MMIO_SKL_PLANE_DW((pipe), (plane), (dw), \
+ _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B, \
+ _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
#define _PLANE_AUX_DIST_1_A 0x701c0
#define _PLANE_AUX_DIST_2_A 0x702c0
#define _PLANE_AUX_DIST_1_B 0x711c0
#define _PLANE_AUX_DIST_2_B 0x712c0
-#define _PLANE_AUX_DIST_1(pipe) _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
-#define _PLANE_AUX_DIST_2(pipe) _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
-#define PLANE_AUX_DIST(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
+#define PLANE_AUX_DIST(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B, \
+ _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
#define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
#define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
#define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
@@ -193,17 +202,17 @@
#define _PLANE_AUX_OFFSET_2_A 0x702c4
#define _PLANE_AUX_OFFSET_1_B 0x711c4
#define _PLANE_AUX_OFFSET_2_B 0x712c4
-#define _PLANE_AUX_OFFSET_1(pipe) _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
-#define _PLANE_AUX_OFFSET_2(pipe) _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
-#define PLANE_AUX_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
+#define PLANE_AUX_OFFSET(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B, \
+ _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
#define _PLANE_CUS_CTL_1_A 0x701c8
#define _PLANE_CUS_CTL_2_A 0x702c8
#define _PLANE_CUS_CTL_1_B 0x711c8
#define _PLANE_CUS_CTL_2_B 0x712c8
-#define _PLANE_CUS_CTL_1(pipe) _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
-#define _PLANE_CUS_CTL_2(pipe) _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
-#define PLANE_CUS_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
+#define PLANE_CUS_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B, \
+ _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
#define PLANE_CUS_ENABLE REG_BIT(31)
#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
#define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
@@ -225,9 +234,9 @@
#define _PLANE_COLOR_CTL_2_A 0x702cc
#define _PLANE_COLOR_CTL_1_B 0x711cc
#define _PLANE_COLOR_CTL_2_B 0x712cc
-#define _PLANE_COLOR_CTL_1(pipe) _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
-#define _PLANE_COLOR_CTL_2(pipe) _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
-#define PLANE_COLOR_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
+#define PLANE_COLOR_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B, \
+ _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
#define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
@@ -249,64 +258,56 @@
#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702e0
#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711e0
#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712e0
-#define _PLANE_INPUT_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, _PLANE_INPUT_CSC_RY_GY_1_B)
-#define _PLANE_INPUT_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, _PLANE_INPUT_CSC_RY_GY_2_B)
-#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
+#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
+ _PLANE_INPUT_CSC_RY_GY_1_A, _PLANE_INPUT_CSC_RY_GY_1_B, \
+ _PLANE_INPUT_CSC_RY_GY_2_A, _PLANE_INPUT_CSC_RY_GY_2_B)
#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701f8
#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702f8
#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711f8
#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712f8
-#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, _PLANE_INPUT_CSC_PREOFF_HI_1_B)
-#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, _PLANE_INPUT_CSC_PREOFF_HI_2_B)
-#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
+#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
+ _PLANE_INPUT_CSC_PREOFF_HI_1_A, _PLANE_INPUT_CSC_PREOFF_HI_1_B, \
+ _PLANE_INPUT_CSC_PREOFF_HI_2_A, _PLANE_INPUT_CSC_PREOFF_HI_2_B)
#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
-#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
-#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
-#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
+#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
+ _PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B, \
+ _PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
#define _PLANE_CSC_RY_GY_1_A 0x70210
#define _PLANE_CSC_RY_GY_2_A 0x70310
#define _PLANE_CSC_RY_GY_1_B 0x71210
#define _PLANE_CSC_RY_GY_2_B 0x71310
-#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, _PLANE_CSC_RY_GY_1_B)
-#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, _PLANE_CSC_RY_GY_2_B)
-#define PLANE_CSC_COEFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
+#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
+ _PLANE_CSC_RY_GY_1_A, _PLANE_CSC_RY_GY_1_B, \
+ _PLANE_CSC_RY_GY_2_A, _PLANE_CSC_RY_GY_2_B)
#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
-#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, _PLANE_CSC_PREOFF_HI_1_B)
-#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, _PLANE_CSC_PREOFF_HI_2_B)
-#define PLANE_CSC_PREOFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + (index) * 4)
+#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
+ _PLANE_CSC_PREOFF_HI_1_A, _PLANE_CSC_PREOFF_HI_1_B, \
+ _PLANE_CSC_PREOFF_HI_2_A, _PLANE_CSC_PREOFF_HI_2_B)
#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
-#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, _PLANE_CSC_POSTOFF_HI_1_B)
-#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, _PLANE_CSC_POSTOFF_HI_2_B)
-#define PLANE_CSC_POSTOFF(pipe, plane, index) \
- _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
-
+#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
+ _PLANE_CSC_POSTOFF_HI_1_A, _PLANE_CSC_POSTOFF_HI_1_B, \
+ _PLANE_CSC_POSTOFF_HI_2_A, _PLANE_CSC_POSTOFF_HI_2_B)
#define _PLANE_WM_1_A_0 0x70240
#define _PLANE_WM_1_B_0 0x71240
#define _PLANE_WM_2_A_0 0x70340
#define _PLANE_WM_2_B_0 0x71340
-#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
-#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
-#define _PLANE_WM_BASE(pipe, plane) _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
-#define PLANE_WM(pipe, plane, level) _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
+#define PLANE_WM(pipe, plane, level) _MMIO_SKL_PLANE_DW((pipe), (plane), (level), \
+ _PLANE_WM_1_A_0, _PLANE_WM_1_B_0, \
+ _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
#define PLANE_WM_EN REG_BIT(31)
#define PLANE_WM_IGNORE_LINES REG_BIT(30)
#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
@@ -316,50 +317,50 @@
#define _PLANE_WM_SAGV_1_B 0x71258
#define _PLANE_WM_SAGV_2_A 0x70358
#define _PLANE_WM_SAGV_2_B 0x71358
-#define _PLANE_WM_SAGV_1(pipe) _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
-#define _PLANE_WM_SAGV_2(pipe) _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
-#define PLANE_WM_SAGV(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
+#define PLANE_WM_SAGV(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B, \
+ _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
#define _PLANE_WM_SAGV_TRANS_1_A 0x7025c
#define _PLANE_WM_SAGV_TRANS_1_B 0x7125c
#define _PLANE_WM_SAGV_TRANS_2_A 0x7035c
#define _PLANE_WM_SAGV_TRANS_2_B 0x7135c
-#define _PLANE_WM_SAGV_TRANS_1(pipe) _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
-#define _PLANE_WM_SAGV_TRANS_2(pipe) _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
-#define PLANE_WM_SAGV_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
+#define PLANE_WM_SAGV_TRANS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B, \
+ _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
#define _PLANE_WM_TRANS_1_A 0x70268
#define _PLANE_WM_TRANS_1_B 0x71268
#define _PLANE_WM_TRANS_2_A 0x70368
#define _PLANE_WM_TRANS_2_B 0x71368
-#define _PLANE_WM_TRANS_1(pipe) _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
-#define _PLANE_WM_TRANS_2(pipe) _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
-#define PLANE_WM_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
+#define PLANE_WM_TRANS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B, \
+ _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
#define _PLANE_CHICKEN_1_A 0x7026c /* tgl+ */
#define _PLANE_CHICKEN_2_A 0x7036c
#define _PLANE_CHICKEN_1_B 0x7126c
#define _PLANE_CHICKEN_2_B 0x7136c
-#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B)
-#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
-#define PLANE_CHICKEN(pipe, plane) _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
+#define PLANE_CHICKEN(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B, \
+ _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
#define _PLANE_NV12_BUF_CFG_1_A 0x70278
#define _PLANE_NV12_BUF_CFG_2_A 0x70378
#define _PLANE_NV12_BUF_CFG_1_B 0x71278
#define _PLANE_NV12_BUF_CFG_2_B 0x71378
-#define _PLANE_NV12_BUF_CFG_1(pipe) _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
-#define _PLANE_NV12_BUF_CFG_2(pipe) _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
-#define PLANE_NV12_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
+#define PLANE_NV12_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B, \
+ _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
#define _PLANE_BUF_CFG_1_A 0x7027c
#define _PLANE_BUF_CFG_2_A 0x7037c
#define _PLANE_BUF_CFG_1_B 0x7127c
#define _PLANE_BUF_CFG_2_B 0x7137c
-#define _PLANE_BUF_CFG_1(pipe) _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
-#define _PLANE_BUF_CFG_2(pipe) _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
-#define PLANE_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
+#define PLANE_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
+ _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B, \
+ _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* Re: [PATCH v2 13/16] drm/i915: Refactor skl+ plane register offset calculations
2024-05-13 17:00 ` [PATCH v2 " Ville Syrjala
@ 2024-05-13 20:41 ` Jani Nikula
2024-05-13 20:43 ` Jani Nikula
0 siblings, 1 reply; 48+ messages in thread
From: Jani Nikula @ 2024-05-13 20:41 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Mon, 13 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currentluy every skl+ plane register defines some intermediate
> macros to calculate the final register offset. Pull all of that
> into common macros, simplifying the final register offset stuff
> into just five defines:
> - raw register offsets for the planes 1 and 2 on pipes A and B
> - the final parametrized macro
>
> v2: Rebase
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Nice cleanup,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../i915/display/skl_universal_plane_regs.h | 185 +++++++++---------
> 1 file changed, 93 insertions(+), 92 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> index 0b4f97059479..cb3bdd71b6b2 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> @@ -8,13 +8,22 @@
>
> #include "intel_display_reg_defs.h"
>
> +#define _SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
> + _PLANE((plane), _PIPE((pipe), (reg_1_a), (reg_1_b)), _PIPE((pipe), (reg_2_a), (reg_2_b)))
> +#define _SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
> + (_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)) + (dw) * 4)
> +#define _MMIO_SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
> + _MMIO(_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))
> +#define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
> + _MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))
> +
> #define _PLANE_CTL_1_A 0x70180
> #define _PLANE_CTL_2_A 0x70280
> #define _PLANE_CTL_1_B 0x71180
> #define _PLANE_CTL_2_B 0x71280
> -#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
> -#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
> -#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
> +#define PLANE_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
> + _PLANE_CTL_1_A, _PLANE_CTL_1_B, \
> + _PLANE_CTL_2_A, _PLANE_CTL_2_B)
> #define PLANE_CTL_ENABLE REG_BIT(31)
> #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
> #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
> @@ -83,9 +92,9 @@
> #define _PLANE_STRIDE_2_A 0x70288
> #define _PLANE_STRIDE_1_B 0x71188
> #define _PLANE_STRIDE_2_B 0x71288
> -#define _PLANE_STRIDE_1(pipe) _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
> -#define _PLANE_STRIDE_2(pipe) _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
> -#define PLANE_STRIDE(pipe, plane) _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
> +#define PLANE_STRIDE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
> + _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B, \
> + _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
> #define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
> #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
>
> @@ -93,9 +102,9 @@
> #define _PLANE_POS_2_A 0x7028c
> #define _PLANE_POS_1_B 0x7118c
> #define _PLANE_POS_2_B 0x7128c
> -#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
> -#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
> -#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
> +#define PLANE_POS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
> + _PLANE_POS_1_A, _PLANE_POS_1_B, \
> + _PLANE_POS_2_A, _PLANE_POS_2_B)
> #define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
> #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
> #define PLANE_POS_X_MASK REG_GENMASK(15, 0)
> @@ -105,9 +114,9 @@
> #define _PLANE_SIZE_2_A 0x70290
> #define _PLANE_SIZE_1_B 0x71190
> #define _PLANE_SIZE_2_B 0x71290
> -#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
> -#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
> -#define PLANE_SIZE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
> +#define PLANE_SIZE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
> + _PLANE_SIZE_1_A, _PLANE_SIZE_1_B, \
> + _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
> #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
> #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
> #define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
> @@ -117,26 +126,26 @@
> #define _PLANE_KEYVAL_2_A 0x70294
> #define _PLANE_KEYVAL_1_B 0x71194
> #define _PLANE_KEYVAL_2_B 0x71294
> -#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
> -#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
> -#define PLANE_KEYVAL(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
> +#define PLANE_KEYVAL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane),\
> + _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B, \
> + _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
>
> #define _PLANE_KEYMSK_1_A 0x70198
> #define _PLANE_KEYMSK_2_A 0x70298
> #define _PLANE_KEYMSK_1_B 0x71198
> #define _PLANE_KEYMSK_2_B 0x71298
> -#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
> -#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
> -#define PLANE_KEYMSK(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
> +#define PLANE_KEYMSK(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
> + _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B, \
> + _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
> #define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31)
>
> #define _PLANE_SURF_1_A 0x7019c
> #define _PLANE_SURF_2_A 0x7029c
> #define _PLANE_SURF_1_B 0x7119c
> #define _PLANE_SURF_2_B 0x7129c
> -#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
> -#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
> -#define PLANE_SURF(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
> +#define PLANE_SURF(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
> + _PLANE_SURF_1_A, _PLANE_SURF_1_B, \
> + _PLANE_SURF_2_A, _PLANE_SURF_2_B)
> #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
> #define PLANE_SURF_DECRYPT REG_BIT(2)
>
> @@ -144,9 +153,9 @@
> #define _PLANE_KEYMAX_2_A 0x702a0
> #define _PLANE_KEYMAX_1_B 0x711a0
> #define _PLANE_KEYMAX_2_B 0x712a0
> -#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
> -#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
> -#define PLANE_KEYMAX(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
> +#define PLANE_KEYMAX(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
> + _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B, \
> + _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
> #define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24)
> #define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a))
>
> @@ -154,9 +163,9 @@
> #define _PLANE_OFFSET_2_A 0x702a4
> #define _PLANE_OFFSET_1_B 0x711a4
> #define _PLANE_OFFSET_2_B 0x712a4
> -#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
> -#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
> -#define PLANE_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
> +#define PLANE_OFFSET(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
> + _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B, \
> + _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
> #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
> #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
> #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
> @@ -166,25 +175,25 @@
> #define _PLANE_SURFLIVE_2_A 0x702ac
> #define _PLANE_SURFLIVE_1_B 0x711ac
> #define _PLANE_SURFLIVE_2_B 0x712ac
> -#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B)
> -#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
> -#define PLANE_SURFLIVE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
> +#define PLANE_SURFLIVE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
> + _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B, \
> + _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
>
> #define _PLANE_CC_VAL_1_A 0x701b4
> #define _PLANE_CC_VAL_2_A 0x702b4
> #define _PLANE_CC_VAL_1_B 0x711b4
> #define _PLANE_CC_VAL_2_B 0x712b4
> -#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
> -#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
> -#define PLANE_CC_VAL(pipe, plane, dw) _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
> +#define PLANE_CC_VAL(pipe, plane, dw) _MMIO_SKL_PLANE_DW((pipe), (plane), (dw), \
> + _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B, \
> + _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B)
>
> #define _PLANE_AUX_DIST_1_A 0x701c0
> #define _PLANE_AUX_DIST_2_A 0x702c0
> #define _PLANE_AUX_DIST_1_B 0x711c0
> #define _PLANE_AUX_DIST_2_B 0x712c0
> -#define _PLANE_AUX_DIST_1(pipe) _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
> -#define _PLANE_AUX_DIST_2(pipe) _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
> -#define PLANE_AUX_DIST(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
> +#define PLANE_AUX_DIST(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
> + _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B, \
> + _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
> #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
> #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
> #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
> @@ -193,17 +202,17 @@
> #define _PLANE_AUX_OFFSET_2_A 0x702c4
> #define _PLANE_AUX_OFFSET_1_B 0x711c4
> #define _PLANE_AUX_OFFSET_2_B 0x712c4
> -#define _PLANE_AUX_OFFSET_1(pipe) _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
> -#define _PLANE_AUX_OFFSET_2(pipe) _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
> -#define PLANE_AUX_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
> +#define PLANE_AUX_OFFSET(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
> + _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B, \
> + _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
>
> #define _PLANE_CUS_CTL_1_A 0x701c8
> #define _PLANE_CUS_CTL_2_A 0x702c8
> #define _PLANE_CUS_CTL_1_B 0x711c8
> #define _PLANE_CUS_CTL_2_B 0x712c8
> -#define _PLANE_CUS_CTL_1(pipe) _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
> -#define _PLANE_CUS_CTL_2(pipe) _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
> -#define PLANE_CUS_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
> +#define PLANE_CUS_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
> + _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B, \
> + _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
> #define PLANE_CUS_ENABLE REG_BIT(31)
> #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
> #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
> @@ -225,9 +234,9 @@
> #define _PLANE_COLOR_CTL_2_A 0x702cc
> #define _PLANE_COLOR_CTL_1_B 0x711cc
> #define _PLANE_COLOR_CTL_2_B 0x712cc
> -#define _PLANE_COLOR_CTL_1(pipe) _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
> -#define _PLANE_COLOR_CTL_2(pipe) _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
> -#define PLANE_COLOR_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
> +#define PLANE_COLOR_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
> + _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B, \
> + _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
> #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
> #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
> #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
> @@ -249,64 +258,56 @@
> #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702e0
> #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711e0
> #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712e0
> -#define _PLANE_INPUT_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, _PLANE_INPUT_CSC_RY_GY_1_B)
> -#define _PLANE_INPUT_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, _PLANE_INPUT_CSC_RY_GY_2_B)
> -#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
> - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
> +#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
> + _PLANE_INPUT_CSC_RY_GY_1_A, _PLANE_INPUT_CSC_RY_GY_1_B, \
> + _PLANE_INPUT_CSC_RY_GY_2_A, _PLANE_INPUT_CSC_RY_GY_2_B)
>
> #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701f8
> #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702f8
> #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711f8
> #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712f8
> -#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, _PLANE_INPUT_CSC_PREOFF_HI_1_B)
> -#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, _PLANE_INPUT_CSC_PREOFF_HI_2_B)
> -#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
> - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
> +#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
> + _PLANE_INPUT_CSC_PREOFF_HI_1_A, _PLANE_INPUT_CSC_PREOFF_HI_1_B, \
> + _PLANE_INPUT_CSC_PREOFF_HI_2_A, _PLANE_INPUT_CSC_PREOFF_HI_2_B)
>
> #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
> #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
> #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
> #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
> -#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
> -#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
> -#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
> - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
> +#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
> + _PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B, \
> + _PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
>
> #define _PLANE_CSC_RY_GY_1_A 0x70210
> #define _PLANE_CSC_RY_GY_2_A 0x70310
> #define _PLANE_CSC_RY_GY_1_B 0x71210
> #define _PLANE_CSC_RY_GY_2_B 0x71310
> -#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, _PLANE_CSC_RY_GY_1_B)
> -#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, _PLANE_CSC_RY_GY_2_B)
> -#define PLANE_CSC_COEFF(pipe, plane, index) \
> - _MMIO_PLANE(plane, _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
> +#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
> + _PLANE_CSC_RY_GY_1_A, _PLANE_CSC_RY_GY_1_B, \
> + _PLANE_CSC_RY_GY_2_A, _PLANE_CSC_RY_GY_2_B)
>
> #define _PLANE_CSC_PREOFF_HI_1_A 0x70228
> #define _PLANE_CSC_PREOFF_HI_2_A 0x70328
> #define _PLANE_CSC_PREOFF_HI_1_B 0x71228
> #define _PLANE_CSC_PREOFF_HI_2_B 0x71328
> -#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, _PLANE_CSC_PREOFF_HI_1_B)
> -#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, _PLANE_CSC_PREOFF_HI_2_B)
> -#define PLANE_CSC_PREOFF(pipe, plane, index) \
> - _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + (index) * 4)
> +#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
> + _PLANE_CSC_PREOFF_HI_1_A, _PLANE_CSC_PREOFF_HI_1_B, \
> + _PLANE_CSC_PREOFF_HI_2_A, _PLANE_CSC_PREOFF_HI_2_B)
>
> #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
> #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
> #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
> #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
> -#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, _PLANE_CSC_POSTOFF_HI_1_B)
> -#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, _PLANE_CSC_POSTOFF_HI_2_B)
> -#define PLANE_CSC_POSTOFF(pipe, plane, index) \
> - _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
> -
> +#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
> + _PLANE_CSC_POSTOFF_HI_1_A, _PLANE_CSC_POSTOFF_HI_1_B, \
> + _PLANE_CSC_POSTOFF_HI_2_A, _PLANE_CSC_POSTOFF_HI_2_B)
> #define _PLANE_WM_1_A_0 0x70240
> #define _PLANE_WM_1_B_0 0x71240
> #define _PLANE_WM_2_A_0 0x70340
> #define _PLANE_WM_2_B_0 0x71340
> -#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
> -#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
> -#define _PLANE_WM_BASE(pipe, plane) _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
> -#define PLANE_WM(pipe, plane, level) _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
> +#define PLANE_WM(pipe, plane, level) _MMIO_SKL_PLANE_DW((pipe), (plane), (level), \
> + _PLANE_WM_1_A_0, _PLANE_WM_1_B_0, \
> + _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
> #define PLANE_WM_EN REG_BIT(31)
> #define PLANE_WM_IGNORE_LINES REG_BIT(30)
> #define PLANE_WM_LINES_MASK REG_GENMASK(26, 14)
> @@ -316,50 +317,50 @@
> #define _PLANE_WM_SAGV_1_B 0x71258
> #define _PLANE_WM_SAGV_2_A 0x70358
> #define _PLANE_WM_SAGV_2_B 0x71358
> -#define _PLANE_WM_SAGV_1(pipe) _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
> -#define _PLANE_WM_SAGV_2(pipe) _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
> -#define PLANE_WM_SAGV(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
> +#define PLANE_WM_SAGV(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
> + _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B, \
> + _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
>
> #define _PLANE_WM_SAGV_TRANS_1_A 0x7025c
> #define _PLANE_WM_SAGV_TRANS_1_B 0x7125c
> #define _PLANE_WM_SAGV_TRANS_2_A 0x7035c
> #define _PLANE_WM_SAGV_TRANS_2_B 0x7135c
> -#define _PLANE_WM_SAGV_TRANS_1(pipe) _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
> -#define _PLANE_WM_SAGV_TRANS_2(pipe) _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
> -#define PLANE_WM_SAGV_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
> +#define PLANE_WM_SAGV_TRANS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
> + _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B, \
> + _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
>
> #define _PLANE_WM_TRANS_1_A 0x70268
> #define _PLANE_WM_TRANS_1_B 0x71268
> #define _PLANE_WM_TRANS_2_A 0x70368
> #define _PLANE_WM_TRANS_2_B 0x71368
> -#define _PLANE_WM_TRANS_1(pipe) _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
> -#define _PLANE_WM_TRANS_2(pipe) _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
> -#define PLANE_WM_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
> +#define PLANE_WM_TRANS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
> + _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B, \
> + _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
>
> #define _PLANE_CHICKEN_1_A 0x7026c /* tgl+ */
> #define _PLANE_CHICKEN_2_A 0x7036c
> #define _PLANE_CHICKEN_1_B 0x7126c
> #define _PLANE_CHICKEN_2_B 0x7136c
> -#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B)
> -#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
> -#define PLANE_CHICKEN(pipe, plane) _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
> +#define PLANE_CHICKEN(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
> + _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B, \
> + _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
> #define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
>
> #define _PLANE_NV12_BUF_CFG_1_A 0x70278
> #define _PLANE_NV12_BUF_CFG_2_A 0x70378
> #define _PLANE_NV12_BUF_CFG_1_B 0x71278
> #define _PLANE_NV12_BUF_CFG_2_B 0x71378
> -#define _PLANE_NV12_BUF_CFG_1(pipe) _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
> -#define _PLANE_NV12_BUF_CFG_2(pipe) _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
> -#define PLANE_NV12_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
> +#define PLANE_NV12_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
> + _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B, \
> + _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
>
> #define _PLANE_BUF_CFG_1_A 0x7027c
> #define _PLANE_BUF_CFG_2_A 0x7037c
> #define _PLANE_BUF_CFG_1_B 0x7127c
> #define _PLANE_BUF_CFG_2_B 0x7137c
> -#define _PLANE_BUF_CFG_1(pipe) _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
> -#define _PLANE_BUF_CFG_2(pipe) _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
> -#define PLANE_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
> +#define PLANE_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \
> + _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B, \
> + _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
> /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
> #define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
> #define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v2 13/16] drm/i915: Refactor skl+ plane register offset calculations
2024-05-13 20:41 ` Jani Nikula
@ 2024-05-13 20:43 ` Jani Nikula
0 siblings, 0 replies; 48+ messages in thread
From: Jani Nikula @ 2024-05-13 20:43 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Mon, 13 May 2024, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Mon, 13 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Currentluy every skl+ plane register defines some intermediate
*Currently
>> macros to calculate the final register offset. Pull all of that
>> into common macros, simplifying the final register offset stuff
>> into just five defines:
>> - raw register offsets for the planes 1 and 2 on pipes A and B
>> - the final parametrized macro
>>
>> v2: Rebase
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Nice cleanup,
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 14/16] drm/i915: Extract skl_plane_{wm,ddb}_reg_val()
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
` (12 preceding siblings ...)
2024-05-10 15:23 ` [PATCH 13/16] drm/i915: Refactor skl+ plane register offset calculations Ville Syrjala
@ 2024-05-10 15:23 ` Ville Syrjala
2024-05-13 20:43 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 15/16] drm/i915: Nuke skl_write_wm_level() and skl_ddb_entry_write() Ville Syrjala
` (7 subsequent siblings)
21 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2024-05-10 15:23 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Extract helpers to calculate the final wm/ddb register
values for skl+. Will allow me to more cleanly remove the
register write wrappers for these registers.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/skl_watermark.c | 29 +++++++++++++-------
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 2a2073bf3aca..8a0a26ab8e6a 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2365,21 +2365,23 @@ static int skl_build_pipe_wm(struct intel_atomic_state *state,
return skl_wm_check_vblank(crtc_state);
}
+static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
+{
+ if (!entry->end)
+ return 0;
+
+ return PLANE_BUF_END(entry->end - 1) |
+ PLANE_BUF_START(entry->start);
+}
+
static void skl_ddb_entry_write(struct drm_i915_private *i915,
i915_reg_t reg,
const struct skl_ddb_entry *entry)
{
- if (entry->end)
- intel_de_write_fw(i915, reg,
- PLANE_BUF_END(entry->end - 1) |
- PLANE_BUF_START(entry->start));
- else
- intel_de_write_fw(i915, reg, 0);
+ intel_de_write_fw(i915, reg, skl_plane_ddb_reg_val(entry));
}
-static void skl_write_wm_level(struct drm_i915_private *i915,
- i915_reg_t reg,
- const struct skl_wm_level *level)
+static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
{
u32 val = 0;
@@ -2390,7 +2392,14 @@ static void skl_write_wm_level(struct drm_i915_private *i915,
val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks);
val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
- intel_de_write_fw(i915, reg, val);
+ return val;
+}
+
+static void skl_write_wm_level(struct drm_i915_private *i915,
+ i915_reg_t reg,
+ const struct skl_wm_level *level)
+{
+ intel_de_write_fw(i915, reg, skl_plane_wm_reg_val(level));
}
void skl_write_plane_wm(struct intel_plane *plane,
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 14/16] drm/i915: Extract skl_plane_{wm,ddb}_reg_val()
2024-05-10 15:23 ` [PATCH 14/16] drm/i915: Extract skl_plane_{wm,ddb}_reg_val() Ville Syrjala
@ 2024-05-13 20:43 ` Jani Nikula
0 siblings, 0 replies; 48+ messages in thread
From: Jani Nikula @ 2024-05-13 20:43 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract helpers to calculate the final wm/ddb register
> values for skl+. Will allow me to more cleanly remove the
> register write wrappers for these registers.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c | 29 +++++++++++++-------
> 1 file changed, 19 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 2a2073bf3aca..8a0a26ab8e6a 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2365,21 +2365,23 @@ static int skl_build_pipe_wm(struct intel_atomic_state *state,
> return skl_wm_check_vblank(crtc_state);
> }
>
> +static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
> +{
> + if (!entry->end)
> + return 0;
> +
> + return PLANE_BUF_END(entry->end - 1) |
> + PLANE_BUF_START(entry->start);
> +}
> +
> static void skl_ddb_entry_write(struct drm_i915_private *i915,
> i915_reg_t reg,
> const struct skl_ddb_entry *entry)
> {
> - if (entry->end)
> - intel_de_write_fw(i915, reg,
> - PLANE_BUF_END(entry->end - 1) |
> - PLANE_BUF_START(entry->start));
> - else
> - intel_de_write_fw(i915, reg, 0);
> + intel_de_write_fw(i915, reg, skl_plane_ddb_reg_val(entry));
> }
>
> -static void skl_write_wm_level(struct drm_i915_private *i915,
> - i915_reg_t reg,
> - const struct skl_wm_level *level)
> +static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
> {
> u32 val = 0;
>
> @@ -2390,7 +2392,14 @@ static void skl_write_wm_level(struct drm_i915_private *i915,
> val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks);
> val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
>
> - intel_de_write_fw(i915, reg, val);
> + return val;
> +}
> +
> +static void skl_write_wm_level(struct drm_i915_private *i915,
> + i915_reg_t reg,
> + const struct skl_wm_level *level)
> +{
> + intel_de_write_fw(i915, reg, skl_plane_wm_reg_val(level));
> }
>
> void skl_write_plane_wm(struct intel_plane *plane,
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 15/16] drm/i915: Nuke skl_write_wm_level() and skl_ddb_entry_write()
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
` (13 preceding siblings ...)
2024-05-10 15:23 ` [PATCH 14/16] drm/i915: Extract skl_plane_{wm,ddb}_reg_val() Ville Syrjala
@ 2024-05-10 15:23 ` Ville Syrjala
2024-05-13 20:46 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 16/16] drm/i915: Handle SKL+ WM/DDB registers next to all other plane registers Ville Syrjala
` (6 subsequent siblings)
21 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2024-05-10 15:23 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Get rid of skl_ddb_entry_write() and skl_write_wm_level() and
just call intel_de_write_fw() directly.
This is prep work towards DSB based plane updates where these
wrappers are more of a hinderance.
Done with cocci mostly:
@@
expression D, R, L;
@@
- skl_write_wm_level(D, R, L)
+ intel_de_write_fw(D, R, skl_plane_wm_reg_val(L))
@@
expression D, R, B;
@@
- skl_ddb_entry_write(D, R, B)
+ intel_de_write_fw(D, R, skl_plane_ddb_reg_val(B))
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/skl_watermark.c | 57 ++++++++------------
1 file changed, 22 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 8a0a26ab8e6a..1daceb8ef9de 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2374,13 +2374,6 @@ static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
PLANE_BUF_START(entry->start);
}
-static void skl_ddb_entry_write(struct drm_i915_private *i915,
- i915_reg_t reg,
- const struct skl_ddb_entry *entry)
-{
- intel_de_write_fw(i915, reg, skl_plane_ddb_reg_val(entry));
-}
-
static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
{
u32 val = 0;
@@ -2395,13 +2388,6 @@ static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
return val;
}
-static void skl_write_wm_level(struct drm_i915_private *i915,
- i915_reg_t reg,
- const struct skl_wm_level *level)
-{
- intel_de_write_fw(i915, reg, skl_plane_wm_reg_val(level));
-}
-
void skl_write_plane_wm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
{
@@ -2416,27 +2402,27 @@ void skl_write_plane_wm(struct intel_plane *plane,
int level;
for (level = 0; level < i915->display.wm.num_levels; level++)
- skl_write_wm_level(i915, PLANE_WM(pipe, plane_id, level),
- skl_plane_wm_level(pipe_wm, plane_id, level));
+ intel_de_write_fw(i915, PLANE_WM(pipe, plane_id, level),
+ skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
- skl_write_wm_level(i915, PLANE_WM_TRANS(pipe, plane_id),
- skl_plane_trans_wm(pipe_wm, plane_id));
+ intel_de_write_fw(i915, PLANE_WM_TRANS(pipe, plane_id),
+ skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
if (HAS_HW_SAGV_WM(i915)) {
const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
- skl_write_wm_level(i915, PLANE_WM_SAGV(pipe, plane_id),
- &wm->sagv.wm0);
- skl_write_wm_level(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id),
- &wm->sagv.trans_wm);
+ intel_de_write_fw(i915, PLANE_WM_SAGV(pipe, plane_id),
+ skl_plane_wm_reg_val(&wm->sagv.wm0));
+ intel_de_write_fw(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id),
+ skl_plane_wm_reg_val(&wm->sagv.trans_wm));
}
- skl_ddb_entry_write(i915,
- PLANE_BUF_CFG(pipe, plane_id), ddb);
+ intel_de_write_fw(i915, PLANE_BUF_CFG(pipe, plane_id),
+ skl_plane_ddb_reg_val(ddb));
if (DISPLAY_VER(i915) < 11)
- skl_ddb_entry_write(i915,
- PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_y);
+ intel_de_write_fw(i915, PLANE_NV12_BUF_CFG(pipe, plane_id),
+ skl_plane_ddb_reg_val(ddb_y));
}
void skl_write_cursor_wm(struct intel_plane *plane,
@@ -2451,22 +2437,23 @@ void skl_write_cursor_wm(struct intel_plane *plane,
int level;
for (level = 0; level < i915->display.wm.num_levels; level++)
- skl_write_wm_level(i915, CUR_WM(pipe, level),
- skl_plane_wm_level(pipe_wm, plane_id, level));
+ intel_de_write_fw(i915, CUR_WM(pipe, level),
+ skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
- skl_write_wm_level(i915, CUR_WM_TRANS(pipe),
- skl_plane_trans_wm(pipe_wm, plane_id));
+ intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
+ skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
if (HAS_HW_SAGV_WM(i915)) {
const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
- skl_write_wm_level(i915, CUR_WM_SAGV(pipe),
- &wm->sagv.wm0);
- skl_write_wm_level(i915, CUR_WM_SAGV_TRANS(pipe),
- &wm->sagv.trans_wm);
+ intel_de_write_fw(i915, CUR_WM_SAGV(pipe),
+ skl_plane_wm_reg_val(&wm->sagv.wm0));
+ intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe),
+ skl_plane_wm_reg_val(&wm->sagv.trans_wm));
}
- skl_ddb_entry_write(i915, CUR_BUF_CFG(pipe), ddb);
+ intel_de_write_fw(i915, CUR_BUF_CFG(pipe),
+ skl_plane_ddb_reg_val(ddb));
}
static bool skl_wm_level_equals(const struct skl_wm_level *l1,
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 15/16] drm/i915: Nuke skl_write_wm_level() and skl_ddb_entry_write()
2024-05-10 15:23 ` [PATCH 15/16] drm/i915: Nuke skl_write_wm_level() and skl_ddb_entry_write() Ville Syrjala
@ 2024-05-13 20:46 ` Jani Nikula
0 siblings, 0 replies; 48+ messages in thread
From: Jani Nikula @ 2024-05-13 20:46 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Get rid of skl_ddb_entry_write() and skl_write_wm_level() and
> just call intel_de_write_fw() directly.
>
> This is prep work towards DSB based plane updates where these
> wrappers are more of a hinderance.
>
> Done with cocci mostly:
> @@
> expression D, R, L;
> @@
> - skl_write_wm_level(D, R, L)
> + intel_de_write_fw(D, R, skl_plane_wm_reg_val(L))
>
> @@
> expression D, R, B;
> @@
> - skl_ddb_entry_write(D, R, B)
> + intel_de_write_fw(D, R, skl_plane_ddb_reg_val(B))
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c | 57 ++++++++------------
> 1 file changed, 22 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 8a0a26ab8e6a..1daceb8ef9de 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2374,13 +2374,6 @@ static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
> PLANE_BUF_START(entry->start);
> }
>
> -static void skl_ddb_entry_write(struct drm_i915_private *i915,
> - i915_reg_t reg,
> - const struct skl_ddb_entry *entry)
> -{
> - intel_de_write_fw(i915, reg, skl_plane_ddb_reg_val(entry));
> -}
> -
> static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
> {
> u32 val = 0;
> @@ -2395,13 +2388,6 @@ static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
> return val;
> }
>
> -static void skl_write_wm_level(struct drm_i915_private *i915,
> - i915_reg_t reg,
> - const struct skl_wm_level *level)
> -{
> - intel_de_write_fw(i915, reg, skl_plane_wm_reg_val(level));
> -}
> -
> void skl_write_plane_wm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state)
> {
> @@ -2416,27 +2402,27 @@ void skl_write_plane_wm(struct intel_plane *plane,
> int level;
>
> for (level = 0; level < i915->display.wm.num_levels; level++)
> - skl_write_wm_level(i915, PLANE_WM(pipe, plane_id, level),
> - skl_plane_wm_level(pipe_wm, plane_id, level));
> + intel_de_write_fw(i915, PLANE_WM(pipe, plane_id, level),
> + skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
>
> - skl_write_wm_level(i915, PLANE_WM_TRANS(pipe, plane_id),
> - skl_plane_trans_wm(pipe_wm, plane_id));
> + intel_de_write_fw(i915, PLANE_WM_TRANS(pipe, plane_id),
> + skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
>
> if (HAS_HW_SAGV_WM(i915)) {
> const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
>
> - skl_write_wm_level(i915, PLANE_WM_SAGV(pipe, plane_id),
> - &wm->sagv.wm0);
> - skl_write_wm_level(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id),
> - &wm->sagv.trans_wm);
> + intel_de_write_fw(i915, PLANE_WM_SAGV(pipe, plane_id),
> + skl_plane_wm_reg_val(&wm->sagv.wm0));
> + intel_de_write_fw(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id),
> + skl_plane_wm_reg_val(&wm->sagv.trans_wm));
> }
>
> - skl_ddb_entry_write(i915,
> - PLANE_BUF_CFG(pipe, plane_id), ddb);
> + intel_de_write_fw(i915, PLANE_BUF_CFG(pipe, plane_id),
> + skl_plane_ddb_reg_val(ddb));
>
> if (DISPLAY_VER(i915) < 11)
> - skl_ddb_entry_write(i915,
> - PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_y);
> + intel_de_write_fw(i915, PLANE_NV12_BUF_CFG(pipe, plane_id),
> + skl_plane_ddb_reg_val(ddb_y));
> }
>
> void skl_write_cursor_wm(struct intel_plane *plane,
> @@ -2451,22 +2437,23 @@ void skl_write_cursor_wm(struct intel_plane *plane,
> int level;
>
> for (level = 0; level < i915->display.wm.num_levels; level++)
> - skl_write_wm_level(i915, CUR_WM(pipe, level),
> - skl_plane_wm_level(pipe_wm, plane_id, level));
> + intel_de_write_fw(i915, CUR_WM(pipe, level),
> + skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
>
> - skl_write_wm_level(i915, CUR_WM_TRANS(pipe),
> - skl_plane_trans_wm(pipe_wm, plane_id));
> + intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
> + skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
>
> if (HAS_HW_SAGV_WM(i915)) {
> const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
>
> - skl_write_wm_level(i915, CUR_WM_SAGV(pipe),
> - &wm->sagv.wm0);
> - skl_write_wm_level(i915, CUR_WM_SAGV_TRANS(pipe),
> - &wm->sagv.trans_wm);
> + intel_de_write_fw(i915, CUR_WM_SAGV(pipe),
> + skl_plane_wm_reg_val(&wm->sagv.wm0));
> + intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe),
> + skl_plane_wm_reg_val(&wm->sagv.trans_wm));
> }
>
> - skl_ddb_entry_write(i915, CUR_BUF_CFG(pipe), ddb);
> + intel_de_write_fw(i915, CUR_BUF_CFG(pipe),
> + skl_plane_ddb_reg_val(ddb));
> }
>
> static bool skl_wm_level_equals(const struct skl_wm_level *l1,
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 16/16] drm/i915: Handle SKL+ WM/DDB registers next to all other plane registers
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
` (14 preceding siblings ...)
2024-05-10 15:23 ` [PATCH 15/16] drm/i915: Nuke skl_write_wm_level() and skl_ddb_entry_write() Ville Syrjala
@ 2024-05-10 15:23 ` Ville Syrjala
2024-05-13 20:52 ` Jani Nikula
2024-05-10 16:28 ` ✓ Fi.CI.BAT: success for drm/i915: skl+ plane register stuff Patchwork
` (5 subsequent siblings)
21 siblings, 1 reply; 48+ messages in thread
From: Ville Syrjala @ 2024-05-10 15:23 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Having the plane WM/DDB regitster write functions in skl_watermarks.c
is rather annoying when trying to implement DSB based plane updates.
Move them into the respective files that handle all other plane
register writes. Less places where I need to worry about the DSB
vs. MMIO decisions.
The downside is that we spread the wm struct details a bit further
afield. But if that becomes too annoying we can probably abstract
things a bit more with a few extra functions.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cursor.c | 32 +++++++
.../drm/i915/display/skl_universal_plane.c | 60 ++++++++++++
.../drm/i915/display/skl_universal_plane.h | 5 +
drivers/gpu/drm/i915/display/skl_watermark.c | 95 +------------------
drivers/gpu/drm/i915/display/skl_watermark.h | 13 ++-
5 files changed, 107 insertions(+), 98 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index d2b459634732..3ecab15d1431 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -24,6 +24,7 @@
#include "intel_psr.h"
#include "intel_psr_regs.h"
#include "intel_vblank.h"
+#include "skl_universal_plane.h"
#include "skl_watermark.h"
#include "gem/i915_gem_object.h"
@@ -556,6 +557,37 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,
}
}
+static void skl_write_cursor_wm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+ enum plane_id plane_id = plane->id;
+ enum pipe pipe = plane->pipe;
+ const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
+ const struct skl_ddb_entry *ddb =
+ &crtc_state->wm.skl.plane_ddb[plane_id];
+ int level;
+
+ for (level = 0; level < i915->display.wm.num_levels; level++)
+ intel_de_write_fw(i915, CUR_WM(pipe, level),
+ skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
+
+ intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
+ skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
+
+ if (HAS_HW_SAGV_WM(i915)) {
+ const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
+
+ intel_de_write_fw(i915, CUR_WM_SAGV(pipe),
+ skl_plane_wm_reg_val(&wm->sagv.wm0));
+ intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe),
+ skl_plane_wm_reg_val(&wm->sagv.trans_wm));
+ }
+
+ intel_de_write_fw(i915, CUR_BUF_CFG(pipe),
+ skl_plane_ddb_reg_val(ddb));
+}
+
/* TODO: split into noarm+arm pair */
static void i9xx_cursor_update_arm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index ab560820bb23..a9914cb31631 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -617,6 +617,66 @@ static u32 skl_plane_stride(const struct intel_plane_state *plane_state,
return stride / skl_plane_stride_mult(fb, color_plane, rotation);
}
+u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
+{
+ if (!entry->end)
+ return 0;
+
+ return PLANE_BUF_END(entry->end - 1) |
+ PLANE_BUF_START(entry->start);
+}
+
+u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
+{
+ u32 val = 0;
+
+ if (level->enable)
+ val |= PLANE_WM_EN;
+ if (level->ignore_lines)
+ val |= PLANE_WM_IGNORE_LINES;
+ val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks);
+ val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
+
+ return val;
+}
+
+static void skl_write_plane_wm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+ enum plane_id plane_id = plane->id;
+ enum pipe pipe = plane->pipe;
+ const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
+ const struct skl_ddb_entry *ddb =
+ &crtc_state->wm.skl.plane_ddb[plane_id];
+ const struct skl_ddb_entry *ddb_y =
+ &crtc_state->wm.skl.plane_ddb_y[plane_id];
+ int level;
+
+ for (level = 0; level < i915->display.wm.num_levels; level++)
+ intel_de_write_fw(i915, PLANE_WM(pipe, plane_id, level),
+ skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
+
+ intel_de_write_fw(i915, PLANE_WM_TRANS(pipe, plane_id),
+ skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
+
+ if (HAS_HW_SAGV_WM(i915)) {
+ const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
+
+ intel_de_write_fw(i915, PLANE_WM_SAGV(pipe, plane_id),
+ skl_plane_wm_reg_val(&wm->sagv.wm0));
+ intel_de_write_fw(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id),
+ skl_plane_wm_reg_val(&wm->sagv.trans_wm));
+ }
+
+ intel_de_write_fw(i915, PLANE_BUF_CFG(pipe, plane_id),
+ skl_plane_ddb_reg_val(ddb));
+
+ if (DISPLAY_VER(i915) < 11)
+ intel_de_write_fw(i915, PLANE_NV12_BUF_CFG(pipe, plane_id),
+ skl_plane_ddb_reg_val(ddb_y));
+}
+
static void
skl_plane_disable_arm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.h b/drivers/gpu/drm/i915/display/skl_universal_plane.h
index e92e00c01b29..8eb4521ee851 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.h
@@ -12,6 +12,8 @@ struct drm_i915_private;
struct intel_crtc;
struct intel_initial_plane_config;
struct intel_plane_state;
+struct skl_ddb_entry;
+struct skl_wm_level;
enum pipe;
enum plane_id;
@@ -35,4 +37,7 @@ bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
u8 icl_hdr_plane_mask(void);
bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
+u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry);
+u32 skl_plane_wm_reg_val(const struct skl_wm_level *level);
+
#endif
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 1daceb8ef9de..2064f72da675 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -1396,7 +1396,7 @@ skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)
return data_rate;
}
-static const struct skl_wm_level *
+const struct skl_wm_level *
skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
enum plane_id plane_id,
int level)
@@ -1409,7 +1409,7 @@ skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
return &wm->wm[level];
}
-static const struct skl_wm_level *
+const struct skl_wm_level *
skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
enum plane_id plane_id)
{
@@ -2365,97 +2365,6 @@ static int skl_build_pipe_wm(struct intel_atomic_state *state,
return skl_wm_check_vblank(crtc_state);
}
-static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
-{
- if (!entry->end)
- return 0;
-
- return PLANE_BUF_END(entry->end - 1) |
- PLANE_BUF_START(entry->start);
-}
-
-static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
-{
- u32 val = 0;
-
- if (level->enable)
- val |= PLANE_WM_EN;
- if (level->ignore_lines)
- val |= PLANE_WM_IGNORE_LINES;
- val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks);
- val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
-
- return val;
-}
-
-void skl_write_plane_wm(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state)
-{
- struct drm_i915_private *i915 = to_i915(plane->base.dev);
- enum plane_id plane_id = plane->id;
- enum pipe pipe = plane->pipe;
- const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
- const struct skl_ddb_entry *ddb =
- &crtc_state->wm.skl.plane_ddb[plane_id];
- const struct skl_ddb_entry *ddb_y =
- &crtc_state->wm.skl.plane_ddb_y[plane_id];
- int level;
-
- for (level = 0; level < i915->display.wm.num_levels; level++)
- intel_de_write_fw(i915, PLANE_WM(pipe, plane_id, level),
- skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
-
- intel_de_write_fw(i915, PLANE_WM_TRANS(pipe, plane_id),
- skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
-
- if (HAS_HW_SAGV_WM(i915)) {
- const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
-
- intel_de_write_fw(i915, PLANE_WM_SAGV(pipe, plane_id),
- skl_plane_wm_reg_val(&wm->sagv.wm0));
- intel_de_write_fw(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id),
- skl_plane_wm_reg_val(&wm->sagv.trans_wm));
- }
-
- intel_de_write_fw(i915, PLANE_BUF_CFG(pipe, plane_id),
- skl_plane_ddb_reg_val(ddb));
-
- if (DISPLAY_VER(i915) < 11)
- intel_de_write_fw(i915, PLANE_NV12_BUF_CFG(pipe, plane_id),
- skl_plane_ddb_reg_val(ddb_y));
-}
-
-void skl_write_cursor_wm(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state)
-{
- struct drm_i915_private *i915 = to_i915(plane->base.dev);
- enum plane_id plane_id = plane->id;
- enum pipe pipe = plane->pipe;
- const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
- const struct skl_ddb_entry *ddb =
- &crtc_state->wm.skl.plane_ddb[plane_id];
- int level;
-
- for (level = 0; level < i915->display.wm.num_levels; level++)
- intel_de_write_fw(i915, CUR_WM(pipe, level),
- skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
-
- intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
- skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
-
- if (HAS_HW_SAGV_WM(i915)) {
- const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
-
- intel_de_write_fw(i915, CUR_WM_SAGV(pipe),
- skl_plane_wm_reg_val(&wm->sagv.wm0));
- intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe),
- skl_plane_wm_reg_val(&wm->sagv.trans_wm));
- }
-
- intel_de_write_fw(i915, CUR_BUF_CFG(pipe),
- skl_plane_ddb_reg_val(ddb));
-}
-
static bool skl_wm_level_equals(const struct skl_wm_level *l1,
const struct skl_wm_level *l2)
{
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index 91f92c0e706e..78b121941237 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -18,6 +18,8 @@ struct intel_bw_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_plane;
+struct skl_pipe_wm;
+struct skl_wm_level;
u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915);
@@ -30,11 +32,6 @@ bool intel_has_sagv(struct drm_i915_private *i915);
u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915,
const struct skl_ddb_entry *entry);
-void skl_write_plane_wm(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state);
-void skl_write_cursor_wm(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state);
-
bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
const struct skl_ddb_entry *entries,
int num_entries, int ignore_idx);
@@ -51,6 +48,12 @@ unsigned int skl_watermark_max_latency(struct drm_i915_private *i915,
int initial_wm_level);
void skl_wm_init(struct drm_i915_private *i915);
+const struct skl_wm_level *skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
+ enum plane_id plane_id,
+ int level);
+const struct skl_wm_level *skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
+ enum plane_id plane_id);
+
struct intel_dbuf_state {
struct intel_global_state base;
--
2.43.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 16/16] drm/i915: Handle SKL+ WM/DDB registers next to all other plane registers
2024-05-10 15:23 ` [PATCH 16/16] drm/i915: Handle SKL+ WM/DDB registers next to all other plane registers Ville Syrjala
@ 2024-05-13 20:52 ` Jani Nikula
2024-05-15 11:17 ` Ville Syrjälä
0 siblings, 1 reply; 48+ messages in thread
From: Jani Nikula @ 2024-05-13 20:52 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Having the plane WM/DDB regitster write functions in skl_watermarks.c
> is rather annoying when trying to implement DSB based plane updates.
> Move them into the respective files that handle all other plane
> register writes. Less places where I need to worry about the DSB
> vs. MMIO decisions.
>
> The downside is that we spread the wm struct details a bit further
> afield. But if that becomes too annoying we can probably abstract
> things a bit more with a few extra functions.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[snip]
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.h b/drivers/gpu/drm/i915/display/skl_universal_plane.h
> index e92e00c01b29..8eb4521ee851 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.h
> @@ -12,6 +12,8 @@ struct drm_i915_private;
> struct intel_crtc;
> struct intel_initial_plane_config;
> struct intel_plane_state;
> +struct skl_ddb_entry;
> +struct skl_wm_level;
>
> enum pipe;
> enum plane_id;
> @@ -35,4 +37,7 @@ bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
> u8 icl_hdr_plane_mask(void);
> bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
>
> +u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry);
> +u32 skl_plane_wm_reg_val(const struct skl_wm_level *level);
Yeah, I don't much like interfaces that return register values for
registers that aren't even known... but let's see how this pans out. It
does what it says on the box.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> +
> #endif
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 1daceb8ef9de..2064f72da675 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -1396,7 +1396,7 @@ skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)
> return data_rate;
> }
>
> -static const struct skl_wm_level *
> +const struct skl_wm_level *
> skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
> enum plane_id plane_id,
> int level)
> @@ -1409,7 +1409,7 @@ skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
> return &wm->wm[level];
> }
>
> -static const struct skl_wm_level *
> +const struct skl_wm_level *
> skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
> enum plane_id plane_id)
> {
> @@ -2365,97 +2365,6 @@ static int skl_build_pipe_wm(struct intel_atomic_state *state,
> return skl_wm_check_vblank(crtc_state);
> }
>
> -static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
> -{
> - if (!entry->end)
> - return 0;
> -
> - return PLANE_BUF_END(entry->end - 1) |
> - PLANE_BUF_START(entry->start);
> -}
> -
> -static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
> -{
> - u32 val = 0;
> -
> - if (level->enable)
> - val |= PLANE_WM_EN;
> - if (level->ignore_lines)
> - val |= PLANE_WM_IGNORE_LINES;
> - val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks);
> - val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
> -
> - return val;
> -}
> -
> -void skl_write_plane_wm(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> -{
> - struct drm_i915_private *i915 = to_i915(plane->base.dev);
> - enum plane_id plane_id = plane->id;
> - enum pipe pipe = plane->pipe;
> - const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> - const struct skl_ddb_entry *ddb =
> - &crtc_state->wm.skl.plane_ddb[plane_id];
> - const struct skl_ddb_entry *ddb_y =
> - &crtc_state->wm.skl.plane_ddb_y[plane_id];
> - int level;
> -
> - for (level = 0; level < i915->display.wm.num_levels; level++)
> - intel_de_write_fw(i915, PLANE_WM(pipe, plane_id, level),
> - skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
> -
> - intel_de_write_fw(i915, PLANE_WM_TRANS(pipe, plane_id),
> - skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
> -
> - if (HAS_HW_SAGV_WM(i915)) {
> - const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> -
> - intel_de_write_fw(i915, PLANE_WM_SAGV(pipe, plane_id),
> - skl_plane_wm_reg_val(&wm->sagv.wm0));
> - intel_de_write_fw(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id),
> - skl_plane_wm_reg_val(&wm->sagv.trans_wm));
> - }
> -
> - intel_de_write_fw(i915, PLANE_BUF_CFG(pipe, plane_id),
> - skl_plane_ddb_reg_val(ddb));
> -
> - if (DISPLAY_VER(i915) < 11)
> - intel_de_write_fw(i915, PLANE_NV12_BUF_CFG(pipe, plane_id),
> - skl_plane_ddb_reg_val(ddb_y));
> -}
> -
> -void skl_write_cursor_wm(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> -{
> - struct drm_i915_private *i915 = to_i915(plane->base.dev);
> - enum plane_id plane_id = plane->id;
> - enum pipe pipe = plane->pipe;
> - const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> - const struct skl_ddb_entry *ddb =
> - &crtc_state->wm.skl.plane_ddb[plane_id];
> - int level;
> -
> - for (level = 0; level < i915->display.wm.num_levels; level++)
> - intel_de_write_fw(i915, CUR_WM(pipe, level),
> - skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
> -
> - intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
> - skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
> -
> - if (HAS_HW_SAGV_WM(i915)) {
> - const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> -
> - intel_de_write_fw(i915, CUR_WM_SAGV(pipe),
> - skl_plane_wm_reg_val(&wm->sagv.wm0));
> - intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe),
> - skl_plane_wm_reg_val(&wm->sagv.trans_wm));
> - }
> -
> - intel_de_write_fw(i915, CUR_BUF_CFG(pipe),
> - skl_plane_ddb_reg_val(ddb));
> -}
> -
> static bool skl_wm_level_equals(const struct skl_wm_level *l1,
> const struct skl_wm_level *l2)
> {
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
> index 91f92c0e706e..78b121941237 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.h
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.h
> @@ -18,6 +18,8 @@ struct intel_bw_state;
> struct intel_crtc;
> struct intel_crtc_state;
> struct intel_plane;
> +struct skl_pipe_wm;
> +struct skl_wm_level;
>
> u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915);
>
> @@ -30,11 +32,6 @@ bool intel_has_sagv(struct drm_i915_private *i915);
> u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915,
> const struct skl_ddb_entry *entry);
>
> -void skl_write_plane_wm(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state);
> -void skl_write_cursor_wm(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state);
> -
> bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
> const struct skl_ddb_entry *entries,
> int num_entries, int ignore_idx);
> @@ -51,6 +48,12 @@ unsigned int skl_watermark_max_latency(struct drm_i915_private *i915,
> int initial_wm_level);
> void skl_wm_init(struct drm_i915_private *i915);
>
> +const struct skl_wm_level *skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
> + enum plane_id plane_id,
> + int level);
> +const struct skl_wm_level *skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
> + enum plane_id plane_id);
> +
> struct intel_dbuf_state {
> struct intel_global_state base;
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [PATCH 16/16] drm/i915: Handle SKL+ WM/DDB registers next to all other plane registers
2024-05-13 20:52 ` Jani Nikula
@ 2024-05-15 11:17 ` Ville Syrjälä
0 siblings, 0 replies; 48+ messages in thread
From: Ville Syrjälä @ 2024-05-15 11:17 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Mon, May 13, 2024 at 11:52:08PM +0300, Jani Nikula wrote:
> On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Having the plane WM/DDB regitster write functions in skl_watermarks.c
> > is rather annoying when trying to implement DSB based plane updates.
> > Move them into the respective files that handle all other plane
> > register writes. Less places where I need to worry about the DSB
> > vs. MMIO decisions.
> >
> > The downside is that we spread the wm struct details a bit further
> > afield. But if that becomes too annoying we can probably abstract
> > things a bit more with a few extra functions.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> [snip]
>
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.h b/drivers/gpu/drm/i915/display/skl_universal_plane.h
> > index e92e00c01b29..8eb4521ee851 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.h
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.h
> > @@ -12,6 +12,8 @@ struct drm_i915_private;
> > struct intel_crtc;
> > struct intel_initial_plane_config;
> > struct intel_plane_state;
> > +struct skl_ddb_entry;
> > +struct skl_wm_level;
> >
> > enum pipe;
> > enum plane_id;
> > @@ -35,4 +37,7 @@ bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
> > u8 icl_hdr_plane_mask(void);
> > bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
> >
> > +u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry);
> > +u32 skl_plane_wm_reg_val(const struct skl_wm_level *level);
>
> Yeah, I don't much like interfaces that return register values for
> registers that aren't even known... but let's see how this pans out. It
> does what it says on the box.
Yeah, I was mulling over whether to just define the register bits
separately for the cursor registers as well and have its own versions
of these. Might be what I'll end up doing.
I think there are also still some other PSR related plane registers
that are defined in a non-standard way, so those might need similar
treatment as well.
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Thanks. Pushed the lot.
>
> > +
> > #endif
> > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> > index 1daceb8ef9de..2064f72da675 100644
> > --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> > @@ -1396,7 +1396,7 @@ skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)
> > return data_rate;
> > }
> >
> > -static const struct skl_wm_level *
> > +const struct skl_wm_level *
> > skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
> > enum plane_id plane_id,
> > int level)
> > @@ -1409,7 +1409,7 @@ skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
> > return &wm->wm[level];
> > }
> >
> > -static const struct skl_wm_level *
> > +const struct skl_wm_level *
> > skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
> > enum plane_id plane_id)
> > {
> > @@ -2365,97 +2365,6 @@ static int skl_build_pipe_wm(struct intel_atomic_state *state,
> > return skl_wm_check_vblank(crtc_state);
> > }
> >
> > -static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
> > -{
> > - if (!entry->end)
> > - return 0;
> > -
> > - return PLANE_BUF_END(entry->end - 1) |
> > - PLANE_BUF_START(entry->start);
> > -}
> > -
> > -static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
> > -{
> > - u32 val = 0;
> > -
> > - if (level->enable)
> > - val |= PLANE_WM_EN;
> > - if (level->ignore_lines)
> > - val |= PLANE_WM_IGNORE_LINES;
> > - val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks);
> > - val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
> > -
> > - return val;
> > -}
> > -
> > -void skl_write_plane_wm(struct intel_plane *plane,
> > - const struct intel_crtc_state *crtc_state)
> > -{
> > - struct drm_i915_private *i915 = to_i915(plane->base.dev);
> > - enum plane_id plane_id = plane->id;
> > - enum pipe pipe = plane->pipe;
> > - const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> > - const struct skl_ddb_entry *ddb =
> > - &crtc_state->wm.skl.plane_ddb[plane_id];
> > - const struct skl_ddb_entry *ddb_y =
> > - &crtc_state->wm.skl.plane_ddb_y[plane_id];
> > - int level;
> > -
> > - for (level = 0; level < i915->display.wm.num_levels; level++)
> > - intel_de_write_fw(i915, PLANE_WM(pipe, plane_id, level),
> > - skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
> > -
> > - intel_de_write_fw(i915, PLANE_WM_TRANS(pipe, plane_id),
> > - skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
> > -
> > - if (HAS_HW_SAGV_WM(i915)) {
> > - const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> > -
> > - intel_de_write_fw(i915, PLANE_WM_SAGV(pipe, plane_id),
> > - skl_plane_wm_reg_val(&wm->sagv.wm0));
> > - intel_de_write_fw(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id),
> > - skl_plane_wm_reg_val(&wm->sagv.trans_wm));
> > - }
> > -
> > - intel_de_write_fw(i915, PLANE_BUF_CFG(pipe, plane_id),
> > - skl_plane_ddb_reg_val(ddb));
> > -
> > - if (DISPLAY_VER(i915) < 11)
> > - intel_de_write_fw(i915, PLANE_NV12_BUF_CFG(pipe, plane_id),
> > - skl_plane_ddb_reg_val(ddb_y));
> > -}
> > -
> > -void skl_write_cursor_wm(struct intel_plane *plane,
> > - const struct intel_crtc_state *crtc_state)
> > -{
> > - struct drm_i915_private *i915 = to_i915(plane->base.dev);
> > - enum plane_id plane_id = plane->id;
> > - enum pipe pipe = plane->pipe;
> > - const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> > - const struct skl_ddb_entry *ddb =
> > - &crtc_state->wm.skl.plane_ddb[plane_id];
> > - int level;
> > -
> > - for (level = 0; level < i915->display.wm.num_levels; level++)
> > - intel_de_write_fw(i915, CUR_WM(pipe, level),
> > - skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
> > -
> > - intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
> > - skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
> > -
> > - if (HAS_HW_SAGV_WM(i915)) {
> > - const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> > -
> > - intel_de_write_fw(i915, CUR_WM_SAGV(pipe),
> > - skl_plane_wm_reg_val(&wm->sagv.wm0));
> > - intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe),
> > - skl_plane_wm_reg_val(&wm->sagv.trans_wm));
> > - }
> > -
> > - intel_de_write_fw(i915, CUR_BUF_CFG(pipe),
> > - skl_plane_ddb_reg_val(ddb));
> > -}
> > -
> > static bool skl_wm_level_equals(const struct skl_wm_level *l1,
> > const struct skl_wm_level *l2)
> > {
> > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
> > index 91f92c0e706e..78b121941237 100644
> > --- a/drivers/gpu/drm/i915/display/skl_watermark.h
> > +++ b/drivers/gpu/drm/i915/display/skl_watermark.h
> > @@ -18,6 +18,8 @@ struct intel_bw_state;
> > struct intel_crtc;
> > struct intel_crtc_state;
> > struct intel_plane;
> > +struct skl_pipe_wm;
> > +struct skl_wm_level;
> >
> > u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915);
> >
> > @@ -30,11 +32,6 @@ bool intel_has_sagv(struct drm_i915_private *i915);
> > u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915,
> > const struct skl_ddb_entry *entry);
> >
> > -void skl_write_plane_wm(struct intel_plane *plane,
> > - const struct intel_crtc_state *crtc_state);
> > -void skl_write_cursor_wm(struct intel_plane *plane,
> > - const struct intel_crtc_state *crtc_state);
> > -
> > bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
> > const struct skl_ddb_entry *entries,
> > int num_entries, int ignore_idx);
> > @@ -51,6 +48,12 @@ unsigned int skl_watermark_max_latency(struct drm_i915_private *i915,
> > int initial_wm_level);
> > void skl_wm_init(struct drm_i915_private *i915);
> >
> > +const struct skl_wm_level *skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
> > + enum plane_id plane_id,
> > + int level);
> > +const struct skl_wm_level *skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
> > + enum plane_id plane_id);
> > +
> > struct intel_dbuf_state {
> > struct intel_global_state base;
>
> --
> Jani Nikula, Intel
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 48+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: skl+ plane register stuff
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
` (15 preceding siblings ...)
2024-05-10 15:23 ` [PATCH 16/16] drm/i915: Handle SKL+ WM/DDB registers next to all other plane registers Ville Syrjala
@ 2024-05-10 16:28 ` Patchwork
2024-05-11 20:02 ` ✗ Fi.CI.IGT: failure " Patchwork
` (4 subsequent siblings)
21 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2024-05-10 16:28 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 12899 bytes --]
== Series Details ==
Series: drm/i915: skl+ plane register stuff
URL : https://patchwork.freedesktop.org/series/133458/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14747 -> Patchwork_133458v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/index.html
Participating hosts (42 -> 42)
------------------------------
Additional (2): fi-glk-j4005 bat-mtlp-8
Missing (2): bat-dg2-11 fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_133458v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-arls-3: NOTRUN -> [SKIP][1] ([i915#9318])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@debugfs_test@basic-hwmon.html
- bat-mtlp-8: NOTRUN -> [SKIP][2] ([i915#9318])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@debugfs_test@basic-hwmon.html
* igt@gem_huc_copy@huc-copy:
- fi-glk-j4005: NOTRUN -> [SKIP][3] ([i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/fi-glk-j4005/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-arls-3: NOTRUN -> [SKIP][4] ([i915#10213]) +3 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@gem_lmem_swapping@parallel-random-engines.html
- bat-mtlp-8: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@gem_lmem_swapping@parallel-random-engines.html
- fi-glk-j4005: NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/fi-glk-j4005/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_mmap@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][7] ([i915#4083])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@gem_mmap@basic.html
- bat-arls-3: NOTRUN -> [SKIP][8] ([i915#4083])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@gem_mmap@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][9] ([i915#4079]) +1 other test skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@gem_render_tiled_blits@basic.html
- bat-arls-3: NOTRUN -> [SKIP][10] ([i915#10197] / [i915#10211] / [i915#4079])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@gem_render_tiled_blits@basic.html
* igt@gem_tiled_blits@basic:
- bat-arls-3: NOTRUN -> [SKIP][11] ([i915#10196] / [i915#4077]) +2 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@gem_tiled_blits@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#4077]) +2 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@gem_tiled_fence_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-arls-3: NOTRUN -> [SKIP][13] ([i915#10206] / [i915#4079])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#6621])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@i915_pm_rps@basic-api.html
- bat-arls-3: NOTRUN -> [SKIP][15] ([i915#10209])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@i915_pm_rps@basic-api.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#5190])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][17] ([i915#4212]) +8 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
- bat-arls-3: NOTRUN -> [SKIP][18] ([i915#10200]) +9 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-arls-3: NOTRUN -> [SKIP][19] ([i915#10202]) +1 other test skip
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][20] ([i915#4213]) +1 other test skip
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-arls-3: NOTRUN -> [SKIP][21] ([i915#9886])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@kms_dsc@dsc-basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][22] ([i915#3555] / [i915#3840] / [i915#9159])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-arls-3: NOTRUN -> [SKIP][23] ([i915#10207])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@kms_force_connector_basic@force-load-detect.html
- bat-mtlp-8: NOTRUN -> [SKIP][24]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-mtlp-8: NOTRUN -> [SKIP][25] ([i915#5274])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_pm_backlight@basic-brightness:
- bat-arls-3: NOTRUN -> [SKIP][26] ([i915#9812])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_psr@psr-primary-mmap-gtt:
- bat-arls-3: NOTRUN -> [SKIP][27] ([i915#9732]) +3 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@kms_psr@psr-primary-mmap-gtt.html
* igt@kms_psr@psr-primary-mmap-gtt@edp-1:
- bat-mtlp-8: NOTRUN -> [SKIP][28] ([i915#4077] / [i915#9688])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@kms_psr@psr-primary-mmap-gtt@edp-1.html
* igt@kms_psr@psr-primary-page-flip:
- fi-glk-j4005: NOTRUN -> [SKIP][29] +10 other tests skip
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/fi-glk-j4005/igt@kms_psr@psr-primary-page-flip.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-mtlp-8: NOTRUN -> [SKIP][30] ([i915#3555] / [i915#8809])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@kms_setmode@basic-clone-single-crtc.html
- bat-arls-3: NOTRUN -> [SKIP][31] ([i915#10208] / [i915#8809])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-read:
- bat-mtlp-8: NOTRUN -> [SKIP][32] ([i915#3708]) +1 other test skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@prime_vgem@basic-fence-read.html
- bat-arls-3: NOTRUN -> [SKIP][33] ([i915#10212] / [i915#3708])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-gtt:
- bat-arls-3: NOTRUN -> [SKIP][34] ([i915#10196] / [i915#3708] / [i915#4077]) +1 other test skip
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@prime_vgem@basic-gtt.html
- bat-mtlp-8: NOTRUN -> [SKIP][35] ([i915#3708] / [i915#4077]) +1 other test skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-read:
- bat-arls-3: NOTRUN -> [SKIP][36] ([i915#10214] / [i915#3708])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-write:
- bat-mtlp-8: NOTRUN -> [SKIP][37] ([i915#10216] / [i915#3708])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@prime_vgem@basic-write.html
- bat-arls-3: NOTRUN -> [SKIP][38] ([i915#10216] / [i915#3708])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@i915_module_load@load:
- bat-arls-3: [ABORT][39] ([i915#11041]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/bat-arls-3/igt@i915_module_load@load.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@i915_module_load@load.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10196
[i915#10197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10197
[i915#10200]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10200
[i915#10202]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10202
[i915#10206]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10206
[i915#10207]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10207
[i915#10208]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10208
[i915#10209]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10209
[i915#10211]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10211
[i915#10212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10212
[i915#10213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10213
[i915#10214]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10214
[i915#10216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10216
[i915#10436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10436
[i915#10911]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10911
[i915#11041]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11041
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274
[i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
[i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
[i915#9159]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9159
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
[i915#9886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886
Build changes
-------------
* Linux: CI_DRM_14747 -> Patchwork_133458v1
CI-20190529: 20190529
CI_DRM_14747: b885b00e7fc01fc109887d59ce2d1283714b07c6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7846: 4a5fd4e7cb2798636f6464e2bd61399f3242b322 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_133458v1: b885b00e7fc01fc109887d59ce2d1283714b07c6 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/index.html
[-- Attachment #2: Type: text/html, Size: 15431 bytes --]
^ permalink raw reply [flat|nested] 48+ messages in thread* ✗ Fi.CI.IGT: failure for drm/i915: skl+ plane register stuff
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
` (16 preceding siblings ...)
2024-05-10 16:28 ` ✓ Fi.CI.BAT: success for drm/i915: skl+ plane register stuff Patchwork
@ 2024-05-11 20:02 ` Patchwork
2024-05-13 18:39 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: skl+ plane register stuff (rev6) Patchwork
` (3 subsequent siblings)
21 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2024-05-11 20:02 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 88224 bytes --]
== Series Details ==
Series: drm/i915: skl+ plane register stuff
URL : https://patchwork.freedesktop.org/series/133458/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14747_full -> Patchwork_133458v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_133458v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_133458v1_full, please notify your bug team ('I915-ci-infra@lists.freedesktop.org') to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_133458v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@api_intel_bb@render-ccs:
- shard-dg2: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@api_intel_bb@render-ccs.html
Known issues
------------
Here are the changes found in Patchwork_133458v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-keep-cache:
- shard-mtlp: NOTRUN -> [SKIP][2] ([i915#8411])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@api_intel_bb@blit-reloc-keep-cache.html
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-dg1: NOTRUN -> [SKIP][3] ([i915#8411]) +1 other test skip
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-15/igt@api_intel_bb@blit-reloc-purge-cache.html
* igt@api_intel_bb@crc32:
- shard-dg1: NOTRUN -> [SKIP][4] ([i915#6230])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-13/igt@api_intel_bb@crc32.html
* igt@core_getversion@basic:
- shard-rkl: NOTRUN -> [CRASH][5] ([i915#11072])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@core_getversion@basic.html
* igt@device_reset@unbind-cold-reset-rebind:
- shard-dg2: NOTRUN -> [SKIP][6] ([i915#11078])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-2/igt@device_reset@unbind-cold-reset-rebind.html
* igt@drm_fdinfo@busy-hang@rcs0:
- shard-mtlp: NOTRUN -> [SKIP][7] ([i915#8414]) +6 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@drm_fdinfo@busy-hang@rcs0.html
* igt@drm_fdinfo@busy-idle@bcs0:
- shard-dg2: NOTRUN -> [SKIP][8] ([i915#8414]) +14 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-11/igt@drm_fdinfo@busy-idle@bcs0.html
* igt@drm_fdinfo@busy-idle@vcs1:
- shard-dg1: NOTRUN -> [SKIP][9] ([i915#8414]) +9 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@drm_fdinfo@busy-idle@vcs1.html
* igt@gem_busy@semaphore:
- shard-dg2: NOTRUN -> [SKIP][10] ([i915#3936])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@gem_busy@semaphore.html
* igt@gem_ccs@ctrl-surf-copy:
- shard-dg1: NOTRUN -> [SKIP][11] ([i915#3555] / [i915#9323])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-13/igt@gem_ccs@ctrl-surf-copy.html
* igt@gem_ccs@suspend-resume:
- shard-dg1: NOTRUN -> [SKIP][12] ([i915#9323])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@gem_ccs@suspend-resume.html
* igt@gem_close_race@multigpu-basic-process:
- shard-mtlp: NOTRUN -> [SKIP][13] ([i915#7697])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_close_race@multigpu-basic-threads:
- shard-rkl: NOTRUN -> [SKIP][14] ([i915#7697])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@gem_close_race@multigpu-basic-threads.html
* igt@gem_create@create-ext-set-pat:
- shard-dg2: NOTRUN -> [SKIP][15] ([i915#8562])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglu: [PASS][16] -> [FAIL][17] ([i915#6268])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-tglu-4/igt@gem_ctx_exec@basic-nohangcheck.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-8/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_persistence@hang:
- shard-mtlp: NOTRUN -> [SKIP][18] ([i915#8555])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-6/igt@gem_ctx_persistence@hang.html
* igt@gem_ctx_persistence@heartbeat-close:
- shard-dg1: NOTRUN -> [SKIP][19] ([i915#8555]) +1 other test skip
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@gem_ctx_persistence@heartbeat-close.html
- shard-dg2: NOTRUN -> [SKIP][20] ([i915#8555])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-11/igt@gem_ctx_persistence@heartbeat-close.html
* igt@gem_ctx_sseu@engines:
- shard-rkl: NOTRUN -> [SKIP][21] ([i915#280])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-5/igt@gem_ctx_sseu@engines.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-dg1: NOTRUN -> [SKIP][22] ([i915#280])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-15/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_eio@kms:
- shard-dg2: NOTRUN -> [INCOMPLETE][23] ([i915#10513])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@gem_eio@kms.html
* igt@gem_eio@reset-stress:
- shard-dg1: [PASS][24] -> [FAIL][25] ([i915#5784])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-dg1-18/igt@gem_eio@reset-stress.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-16/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@bonded-false-hang:
- shard-dg2: NOTRUN -> [SKIP][26] ([i915#4812])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-2/igt@gem_exec_balancer@bonded-false-hang.html
* igt@gem_exec_balancer@bonded-sync:
- shard-dg2: NOTRUN -> [SKIP][27] ([i915#4771])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-11/igt@gem_exec_balancer@bonded-sync.html
- shard-dg1: NOTRUN -> [SKIP][28] ([i915#4771])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@gem_exec_balancer@bonded-sync.html
* igt@gem_exec_balancer@invalid-bonds:
- shard-dg1: NOTRUN -> [SKIP][29] ([i915#4036])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-16/igt@gem_exec_balancer@invalid-bonds.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-rkl: NOTRUN -> [SKIP][30] ([i915#4525])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_capture@many-4k-incremental:
- shard-rkl: NOTRUN -> [FAIL][31] ([i915#9606])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@gem_exec_capture@many-4k-incremental.html
* igt@gem_exec_capture@many-4k-zero:
- shard-dg1: NOTRUN -> [FAIL][32] ([i915#9606])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-15/igt@gem_exec_capture@many-4k-zero.html
* igt@gem_exec_fair@basic-flow:
- shard-mtlp: NOTRUN -> [SKIP][33] ([i915#4473] / [i915#4771])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@gem_exec_fair@basic-flow.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-tglu: NOTRUN -> [FAIL][34] ([i915#2842])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-8/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-vip:
- shard-dg2: NOTRUN -> [SKIP][35] ([i915#3539] / [i915#4852])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-2/igt@gem_exec_fair@basic-none-vip.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-rkl: [PASS][36] -> [FAIL][37] ([i915#2842]) +1 other test fail
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-rkl-6/igt@gem_exec_fair@basic-none@rcs0.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-6/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-pace:
- shard-dg1: NOTRUN -> [SKIP][38] ([i915#3539]) +1 other test skip
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@gem_exec_fair@basic-pace.html
* igt@gem_exec_fair@basic-pace-solo:
- shard-dg2: NOTRUN -> [SKIP][39] ([i915#3539]) +3 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@gem_exec_fair@basic-pace-solo.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][40] -> [FAIL][41] ([i915#2842])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_flush@basic-uc-rw-default:
- shard-dg1: NOTRUN -> [SKIP][42] ([i915#3539] / [i915#4852]) +4 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-13/igt@gem_exec_flush@basic-uc-rw-default.html
* igt@gem_exec_reloc@basic-cpu-read-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][43] ([i915#3281]) +8 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@gem_exec_reloc@basic-cpu-read-noreloc.html
* igt@gem_exec_reloc@basic-gtt-cpu:
- shard-dg1: NOTRUN -> [SKIP][44] ([i915#3281]) +4 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@gem_exec_reloc@basic-gtt-cpu.html
* igt@gem_exec_reloc@basic-gtt-read-active:
- shard-dg2: NOTRUN -> [SKIP][45] ([i915#3281]) +7 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-2/igt@gem_exec_reloc@basic-gtt-read-active.html
* igt@gem_exec_reloc@basic-gtt-wc:
- shard-rkl: NOTRUN -> [SKIP][46] ([i915#3281]) +5 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@gem_exec_reloc@basic-gtt-wc.html
* igt@gem_exec_schedule@preempt-queue:
- shard-dg2: NOTRUN -> [SKIP][47] ([i915#4537] / [i915#4812])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-2/igt@gem_exec_schedule@preempt-queue.html
* igt@gem_exec_schedule@preempt-queue-contexts:
- shard-mtlp: NOTRUN -> [SKIP][48] ([i915#4537] / [i915#4812]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@gem_exec_schedule@preempt-queue-contexts.html
* igt@gem_fence_thrash@bo-write-verify-none:
- shard-dg1: NOTRUN -> [SKIP][49] ([i915#4860]) +1 other test skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-13/igt@gem_fence_thrash@bo-write-verify-none.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][50] ([i915#4860])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html
* igt@gem_lmem_swapping@basic:
- shard-mtlp: NOTRUN -> [SKIP][51] ([i915#4613]) +2 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@basic@lmem0:
- shard-dg2: [PASS][52] -> [FAIL][53] ([i915#10378]) +1 other test fail
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-dg2-1/igt@gem_lmem_swapping@basic@lmem0.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-2/igt@gem_lmem_swapping@basic@lmem0.html
* igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0:
- shard-dg1: NOTRUN -> [SKIP][54] ([i915#4565]) +1 other test skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-13/igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-rkl: NOTRUN -> [SKIP][55] ([i915#4613]) +3 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@verify:
- shard-glk: NOTRUN -> [SKIP][56] ([i915#4613])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-glk7/igt@gem_lmem_swapping@verify.html
* igt@gem_madvise@dontneed-before-exec:
- shard-mtlp: NOTRUN -> [SKIP][57] ([i915#3282]) +2 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@gem_madvise@dontneed-before-exec.html
* igt@gem_mmap_gtt@big-copy:
- shard-dg2: NOTRUN -> [SKIP][58] ([i915#4077]) +7 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@gem_mmap_gtt@big-copy.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-xy:
- shard-mtlp: NOTRUN -> [SKIP][59] ([i915#4077])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
* igt@gem_mmap_gtt@flink-race:
- shard-dg1: NOTRUN -> [SKIP][60] ([i915#4077]) +10 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-13/igt@gem_mmap_gtt@flink-race.html
* igt@gem_mmap_wc@write-cpu-read-wc-unflushed:
- shard-mtlp: NOTRUN -> [SKIP][61] ([i915#4083]) +2 other tests skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@gem_mmap_wc@write-cpu-read-wc-unflushed.html
* igt@gem_mmap_wc@write-prefaulted:
- shard-dg2: NOTRUN -> [SKIP][62] ([i915#4083]) +7 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-2/igt@gem_mmap_wc@write-prefaulted.html
* igt@gem_mmap_wc@write-read:
- shard-dg1: NOTRUN -> [SKIP][63] ([i915#4083]) +6 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@gem_mmap_wc@write-read.html
* igt@gem_partial_pwrite_pread@reads:
- shard-dg1: NOTRUN -> [SKIP][64] ([i915#3282]) +5 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-16/igt@gem_partial_pwrite_pread@reads.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-rkl: NOTRUN -> [SKIP][65] ([i915#3282]) +5 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gem_pxp@create-regular-context-1:
- shard-tglu: NOTRUN -> [SKIP][66] ([i915#4270])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-8/igt@gem_pxp@create-regular-context-1.html
* igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-dg1: NOTRUN -> [SKIP][67] ([i915#4270]) +3 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-13/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
* igt@gem_pxp@protected-raw-src-copy-not-readible:
- shard-mtlp: NOTRUN -> [SKIP][68] ([i915#4270])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@gem_pxp@protected-raw-src-copy-not-readible.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-dg2: NOTRUN -> [SKIP][69] ([i915#4270]) +3 other tests skip
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-rkl: NOTRUN -> [SKIP][70] ([i915#4270]) +1 other test skip
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-5/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_readwrite@write-bad-handle:
- shard-dg2: NOTRUN -> [SKIP][71] ([i915#3282])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-11/igt@gem_readwrite@write-bad-handle.html
* igt@gem_render_copy@y-tiled-to-vebox-x-tiled:
- shard-dg2: NOTRUN -> [SKIP][72] ([i915#5190] / [i915#8428]) +1 other test skip
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-2/igt@gem_render_copy@y-tiled-to-vebox-x-tiled.html
* igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled:
- shard-mtlp: NOTRUN -> [SKIP][73] ([i915#8428]) +3 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-rkl: NOTRUN -> [SKIP][74] ([i915#8411])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-6/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gem_set_tiling_vs_gtt:
- shard-dg1: NOTRUN -> [SKIP][75] ([i915#4079]) +1 other test skip
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-16/igt@gem_set_tiling_vs_gtt.html
* igt@gem_softpin@evict-snoop-interruptible:
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#4885])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-2/igt@gem_softpin@evict-snoop-interruptible.html
* igt@gem_unfence_active_buffers:
- shard-dg1: NOTRUN -> [SKIP][77] ([i915#4879])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@gem_unfence_active_buffers.html
- shard-dg2: NOTRUN -> [SKIP][78] ([i915#4879])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-11/igt@gem_unfence_active_buffers.html
* igt@gem_userptr_blits@coherency-unsync:
- shard-rkl: NOTRUN -> [SKIP][79] ([i915#3297]) +1 other test skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@gem_userptr_blits@coherency-unsync.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-dg1: NOTRUN -> [SKIP][80] ([i915#3297]) +2 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-13/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-dg2: NOTRUN -> [SKIP][81] ([i915#3297]) +2 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-11/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gen9_exec_parse@batch-without-end:
- shard-tglu: NOTRUN -> [SKIP][82] ([i915#2527] / [i915#2856])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-8/igt@gen9_exec_parse@batch-without-end.html
* igt@gen9_exec_parse@bb-chained:
- shard-rkl: NOTRUN -> [SKIP][83] ([i915#2527]) +2 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@gen9_exec_parse@bb-chained.html
* igt@gen9_exec_parse@bb-secure:
- shard-dg1: NOTRUN -> [SKIP][84] ([i915#2527]) +2 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@gen9_exec_parse@bb-secure.html
* igt@gen9_exec_parse@bb-start-param:
- shard-mtlp: NOTRUN -> [SKIP][85] ([i915#2856]) +2 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@gen9_exec_parse@bb-start-param.html
* igt@gen9_exec_parse@unaligned-access:
- shard-dg2: NOTRUN -> [SKIP][86] ([i915#2856]) +4 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@gen9_exec_parse@unaligned-access.html
* igt@i915_module_load@load:
- shard-rkl: NOTRUN -> [SKIP][87] ([i915#6227])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@i915_module_load@load.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-mtlp: [PASS][88] -> [ABORT][89] ([i915#10131] / [i915#9820])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-mtlp-1/igt@i915_module_load@reload-with-fault-injection.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-7/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_module_load@resize-bar:
- shard-mtlp: NOTRUN -> [SKIP][90] ([i915#6412])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@i915_module_load@resize-bar.html
* igt@i915_pm_freq_mult@media-freq@gt0:
- shard-dg1: NOTRUN -> [SKIP][91] ([i915#6590])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-13/igt@i915_pm_freq_mult@media-freq@gt0.html
* igt@i915_pm_rps@min-max-config-idle:
- shard-mtlp: NOTRUN -> [SKIP][92] ([i915#6621])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@i915_pm_rps@min-max-config-idle.html
* igt@i915_pm_rps@waitboost:
- shard-mtlp: NOTRUN -> [FAIL][93] ([i915#8346])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@i915_pm_rps@waitboost.html
* igt@i915_pm_sseu@full-enable:
- shard-mtlp: NOTRUN -> [SKIP][94] ([i915#8437])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@i915_pm_sseu@full-enable.html
* igt@i915_query@query-topology-coherent-slice-mask:
- shard-dg2: NOTRUN -> [SKIP][95] ([i915#6188])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@i915_query@query-topology-coherent-slice-mask.html
* igt@i915_query@test-query-geometry-subslices:
- shard-dg1: NOTRUN -> [SKIP][96] ([i915#5723])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@i915_query@test-query-geometry-subslices.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- shard-mtlp: NOTRUN -> [SKIP][97] ([i915#4212])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@bo-too-small-due-to-tiling:
- shard-dg1: NOTRUN -> [SKIP][98] ([i915#4212])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-15/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
* igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
- shard-tglu: NOTRUN -> [SKIP][99] ([i915#3826])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-8/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc:
- shard-rkl: NOTRUN -> [SKIP][100] ([i915#8709]) +3 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-2/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][101] ([i915#8709]) +11 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-6/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-mtlp: NOTRUN -> [SKIP][102] ([i915#1769] / [i915#3555])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-rkl: NOTRUN -> [SKIP][103] ([i915#5286]) +3 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-tglu: NOTRUN -> [SKIP][104] ([i915#5286]) +1 other test skip
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-dg1: NOTRUN -> [SKIP][105] ([i915#4538] / [i915#5286]) +3 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][106] ([i915#3638]) +2 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-180:
- shard-mtlp: [PASS][107] -> [FAIL][108] ([i915#5138])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-mtlp-1/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-7/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][109] +12 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-dg1: NOTRUN -> [SKIP][110] ([i915#3638]) +1 other test skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-13/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-addfb:
- shard-dg2: NOTRUN -> [SKIP][111] ([i915#5190]) +2 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-2/igt@kms_big_fb@y-tiled-addfb.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-dg2: NOTRUN -> [SKIP][112] ([i915#4538] / [i915#5190]) +7 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180:
- shard-mtlp: NOTRUN -> [SKIP][113] +12 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-dg1: NOTRUN -> [SKIP][114] ([i915#4538]) +4 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-15/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_joiner@basic-force-joiner:
- shard-dg1: NOTRUN -> [SKIP][115] ([i915#10656])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@kms_big_joiner@basic-force-joiner.html
* igt@kms_big_joiner@invalid-modeset-force-joiner:
- shard-rkl: NOTRUN -> [SKIP][116] ([i915#10656])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@kms_big_joiner@invalid-modeset-force-joiner.html
* igt@kms_ccs@bad-aux-stride-y-tiled-ccs@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][117] ([i915#6095]) +87 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-16/igt@kms_ccs@bad-aux-stride-y-tiled-ccs@pipe-c-hdmi-a-4.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][118] ([i915#10307] / [i915#10434] / [i915#6095]) +4 other tests skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-8/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][119] ([i915#6095]) +7 other tests skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-8/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][120] ([i915#6095]) +87 other tests skip
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][121] ([i915#10307] / [i915#6095]) +190 other tests skip
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-6/igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs@pipe-a-hdmi-a-3.html
* igt@kms_ccs@crc-primary-basic-4-tiled-xe2-ccs:
- shard-dg1: NOTRUN -> [SKIP][122] ([i915#10278])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-16/igt@kms_ccs@crc-primary-basic-4-tiled-xe2-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2:
- shard-glk: NOTRUN -> [SKIP][123] +57 other tests skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-glk7/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-xe2-ccs:
- shard-rkl: NOTRUN -> [SKIP][124] ([i915#10278]) +1 other test skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-xe2-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-xe2-ccs:
- shard-mtlp: NOTRUN -> [SKIP][125] ([i915#10278])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-xe2-ccs.html
* igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][126] ([i915#6095]) +27 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-6/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-a-edp-1.html
* igt@kms_cdclk@mode-transition:
- shard-tglu: NOTRUN -> [SKIP][127] ([i915#3742])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-8/igt@kms_cdclk@mode-transition.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-dg1: NOTRUN -> [SKIP][128] ([i915#3742])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-15/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][129] ([i915#7213]) +3 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-8/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html
* igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][130] ([i915#4087]) +3 other tests skip
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3.html
* igt@kms_chamelium_audio@dp-audio:
- shard-mtlp: NOTRUN -> [SKIP][131] ([i915#7828]) +3 other tests skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_chamelium_audio@dp-audio.html
* igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k:
- shard-dg2: NOTRUN -> [SKIP][132] ([i915#7828]) +4 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-11/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html
* igt@kms_chamelium_frames@dp-crc-single:
- shard-dg1: NOTRUN -> [SKIP][133] ([i915#7828]) +7 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-15/igt@kms_chamelium_frames@dp-crc-single.html
* igt@kms_chamelium_frames@vga-frame-dump:
- shard-rkl: NOTRUN -> [SKIP][134] ([i915#7828]) +7 other tests skip
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@kms_chamelium_frames@vga-frame-dump.html
* igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode:
- shard-tglu: NOTRUN -> [SKIP][135] ([i915#7828]) +1 other test skip
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-8/igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode.html
* igt@kms_content_protection@content-type-change:
- shard-tglu: NOTRUN -> [SKIP][136] ([i915#6944] / [i915#9424])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-8/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-dg2: NOTRUN -> [SKIP][137] ([i915#3299])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-11/igt@kms_content_protection@dp-mst-lic-type-1.html
- shard-dg1: NOTRUN -> [SKIP][138] ([i915#3299])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@legacy:
- shard-rkl: NOTRUN -> [SKIP][139] ([i915#7118] / [i915#9424])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@lic-type-0:
- shard-dg2: NOTRUN -> [SKIP][140] ([i915#9424]) +1 other test skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-10/igt@kms_content_protection@lic-type-0.html
- shard-rkl: NOTRUN -> [SKIP][141] ([i915#9424])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@mei-interface:
- shard-mtlp: NOTRUN -> [SKIP][142] ([i915#8063] / [i915#9433])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@type1:
- shard-dg2: NOTRUN -> [SKIP][143] ([i915#7118] / [i915#9424]) +1 other test skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-2/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@cursor-offscreen-max-size:
- shard-tglu: NOTRUN -> [SKIP][144] ([i915#3555]) +2 other tests skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-8/igt@kms_cursor_crc@cursor-offscreen-max-size.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-dg2: NOTRUN -> [SKIP][145] ([i915#3359])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-11/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-rkl: NOTRUN -> [SKIP][146] ([i915#3359]) +1 other test skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-dg1: NOTRUN -> [SKIP][147] ([i915#3359]) +2 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-13/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_crc@cursor-rapid-movement-64x21:
- shard-mtlp: NOTRUN -> [SKIP][148] ([i915#8814]) +1 other test skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_cursor_crc@cursor-rapid-movement-64x21.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-mtlp: NOTRUN -> [SKIP][149] ([i915#3359])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- shard-rkl: NOTRUN -> [SKIP][150] ([i915#4103]) +1 other test skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
- shard-mtlp: NOTRUN -> [SKIP][151] ([i915#9809]) +1 other test skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
- shard-rkl: NOTRUN -> [SKIP][152] +44 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-mtlp: NOTRUN -> [SKIP][153] ([i915#4213])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-dg1: NOTRUN -> [SKIP][154] ([i915#4103] / [i915#4213]) +1 other test skip
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-16/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@torture-move@pipe-a:
- shard-tglu: [PASS][155] -> [DMESG-WARN][156] ([i915#10166] / [i915#1982])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-tglu-3/igt@kms_cursor_legacy@torture-move@pipe-a.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-3/igt@kms_cursor_legacy@torture-move@pipe-a.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-dp-4:
- shard-dg2: NOTRUN -> [SKIP][157] ([i915#9227])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-11/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-dp-4.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][158] ([i915#9723])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-1/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-2.html
* igt@kms_dirtyfb@psr-dirtyfb-ioctl:
- shard-dg1: NOTRUN -> [SKIP][159] ([i915#9723])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
- shard-dg2: NOTRUN -> [SKIP][160] ([i915#9833])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-11/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
* igt@kms_display_modes@extended-mode-basic:
- shard-dg2: NOTRUN -> [SKIP][161] ([i915#3555]) +3 other tests skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][162] ([i915#3804])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-8/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dp_aux_dev:
- shard-dg2: NOTRUN -> [SKIP][163] ([i915#1257])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-6/igt@kms_dp_aux_dev.html
* igt@kms_draw_crc@draw-method-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][164] ([i915#8812])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-13/igt@kms_draw_crc@draw-method-mmap-gtt.html
* igt@kms_dsc@dsc-basic:
- shard-dg2: NOTRUN -> [SKIP][165] ([i915#3555] / [i915#3840]) +1 other test skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-2/igt@kms_dsc@dsc-basic.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-rkl: NOTRUN -> [SKIP][166] ([i915#3840])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-with-formats:
- shard-mtlp: NOTRUN -> [SKIP][167] ([i915#3555] / [i915#3840])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_dsc@dsc-with-formats.html
* igt@kms_feature_discovery@display-3x:
- shard-rkl: NOTRUN -> [SKIP][168] ([i915#1839])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@kms_feature_discovery@display-3x.html
* igt@kms_feature_discovery@display-4x:
- shard-dg1: NOTRUN -> [SKIP][169] ([i915#1839])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-15/igt@kms_feature_discovery@display-4x.html
* igt@kms_feature_discovery@dp-mst:
- shard-mtlp: NOTRUN -> [SKIP][170] ([i915#9337])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_feature_discovery@dp-mst.html
* igt@kms_flip@2x-flip-vs-dpms:
- shard-mtlp: NOTRUN -> [SKIP][171] ([i915#3637]) +5 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_flip@2x-flip-vs-dpms.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-dg1: NOTRUN -> [SKIP][172] ([i915#8381]) +1 other test skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@kms_flip@2x-flip-vs-fences.html
- shard-dg2: NOTRUN -> [SKIP][173] ([i915#8381])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-11/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@2x-flip-vs-panning-interruptible:
- shard-tglu: NOTRUN -> [SKIP][174] ([i915#3637])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-8/igt@kms_flip@2x-flip-vs-panning-interruptible.html
* igt@kms_flip@2x-plain-flip:
- shard-dg1: NOTRUN -> [SKIP][175] ([i915#9934]) +5 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-13/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@flip-vs-panning-vs-hang@a-hdmi-a3:
- shard-dg2: NOTRUN -> [INCOMPLETE][176] ([i915#6113])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-6/igt@kms_flip@flip-vs-panning-vs-hang@a-hdmi-a3.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][177] ([i915#2587] / [i915#2672]) +3 other tests skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][178] ([i915#3555] / [i915#8810])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][179] ([i915#2672]) +4 other tests skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][180] ([i915#2672])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][181] ([i915#2672])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-11/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-valid-mode.html
* igt@kms_force_connector_basic@prune-stale-modes:
- shard-dg2: NOTRUN -> [SKIP][182] ([i915#5274])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][183] ([i915#8708]) +2 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt:
- shard-dg2: NOTRUN -> [SKIP][184] ([i915#5354]) +26 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
- shard-rkl: NOTRUN -> [SKIP][185] ([i915#1825]) +34 other tests skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render:
- shard-dg1: NOTRUN -> [SKIP][186] +41 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-15/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt:
- shard-tglu: NOTRUN -> [SKIP][187] +17 other tests skip
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu:
- shard-mtlp: NOTRUN -> [SKIP][188] ([i915#1825]) +16 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][189] ([i915#8708]) +18 other tests skip
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
- shard-dg1: NOTRUN -> [SKIP][190] ([i915#3458]) +15 other tests skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-15/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-dg1: NOTRUN -> [SKIP][191] ([i915#5439])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-rkl: NOTRUN -> [SKIP][192] ([i915#9766])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][193] ([i915#3023]) +24 other tests skip
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-rte:
- shard-dg2: NOTRUN -> [SKIP][194] ([i915#3458]) +13 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-1p-rte.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][195] ([i915#8708]) +16 other tests skip
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-dg2: NOTRUN -> [SKIP][196] ([i915#3555] / [i915#8228]) +1 other test skip
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-10/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_hdr@static-swap:
- shard-mtlp: NOTRUN -> [SKIP][197] ([i915#3555] / [i915#8228])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_hdr@static-swap.html
* igt@kms_hdr@static-toggle-dpms:
- shard-rkl: NOTRUN -> [SKIP][198] ([i915#3555] / [i915#8228])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-6/igt@kms_hdr@static-toggle-dpms.html
- shard-dg1: NOTRUN -> [SKIP][199] ([i915#3555] / [i915#8228])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-16/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_panel_fitting@legacy:
- shard-dg2: NOTRUN -> [SKIP][200] ([i915#6301])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-11/igt@kms_panel_fitting@legacy.html
- shard-dg1: NOTRUN -> [SKIP][201] ([i915#6301])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@kms_panel_fitting@legacy.html
* igt@kms_plane_multiple@tiling-yf:
- shard-rkl: NOTRUN -> [SKIP][202] ([i915#3555]) +4 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-5/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-dg2: NOTRUN -> [SKIP][203] ([i915#6953] / [i915#9423])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [FAIL][204] ([i915#8292])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [SKIP][205] ([i915#9423]) +7 other tests skip
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-11/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-a-dp-4.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][206] ([i915#9423]) +11 other tests skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-5/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-a-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][207] ([i915#9423]) +3 other tests skip
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-8/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][208] ([i915#5176] / [i915#9423]) +1 other test skip
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-2/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][209] ([i915#5235] / [i915#9423] / [i915#9728]) +3 other tests skip
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][210] ([i915#5235]) +7 other tests skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][211] ([i915#5235]) +11 other tests skip
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-13/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-3.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][212] ([i915#5235]) +5 other tests skip
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-b-edp-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][213] ([i915#3555] / [i915#5235]) +1 other test skip
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-d-edp-1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][214] ([i915#5235] / [i915#9423]) +15 other tests skip
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-4/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-hdmi-a-1.html
* igt@kms_pm_backlight@fade-with-dpms:
- shard-rkl: NOTRUN -> [SKIP][215] ([i915#5354]) +1 other test skip
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@kms_pm_backlight@fade-with-dpms.html
* igt@kms_pm_dc@dc6-psr:
- shard-mtlp: NOTRUN -> [SKIP][216] ([i915#10139]) +1 other test skip
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_dc@dc9-dpms:
- shard-rkl: NOTRUN -> [SKIP][217] ([i915#3361])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-6/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_lpsp@screens-disabled:
- shard-dg1: NOTRUN -> [SKIP][218] ([i915#8430])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@kms_pm_lpsp@screens-disabled.html
- shard-dg2: NOTRUN -> [SKIP][219] ([i915#8430])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-11/igt@kms_pm_lpsp@screens-disabled.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-dg2: [PASS][220] -> [SKIP][221] ([i915#9519]) +1 other test skip
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-dg2-7/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-8/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-tglu: NOTRUN -> [SKIP][222] ([i915#9519])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-8/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-rkl: [PASS][223] -> [SKIP][224] ([i915#9519]) +1 other test skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-rkl-3/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
- shard-mtlp: NOTRUN -> [SKIP][225] ([i915#9519])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_prime@basic-crc-hybrid:
- shard-rkl: NOTRUN -> [SKIP][226] ([i915#6524])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_prime@basic-modeset-hybrid:
- shard-dg1: NOTRUN -> [SKIP][227] ([i915#6524])
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-13/igt@kms_prime@basic-modeset-hybrid.html
* igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area@psr2-pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][228] ([i915#9808]) +1 other test skip
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area@psr2-pipe-a-edp-1.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-dg2: NOTRUN -> [SKIP][229] ([i915#9683])
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-rkl: NOTRUN -> [SKIP][230] ([i915#9683])
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-pr-cursor-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][231] ([i915#1072] / [i915#9673] / [i915#9732]) +5 other tests skip
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-11/igt@kms_psr@fbc-pr-cursor-mmap-gtt.html
* igt@kms_psr@fbc-pr-cursor-plane-onoff:
- shard-rkl: NOTRUN -> [SKIP][232] ([i915#1072] / [i915#9732]) +20 other tests skip
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-6/igt@kms_psr@fbc-pr-cursor-plane-onoff.html
* igt@kms_psr@fbc-pr-sprite-render:
- shard-tglu: NOTRUN -> [SKIP][233] ([i915#9732]) +5 other tests skip
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-8/igt@kms_psr@fbc-pr-sprite-render.html
* igt@kms_psr@pr-cursor-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][234] ([i915#1072] / [i915#9732]) +11 other tests skip
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@kms_psr@pr-cursor-mmap-cpu.html
* igt@kms_psr@pr-cursor-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][235] ([i915#9688]) +5 other tests skip
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_psr@pr-cursor-mmap-gtt.html
* igt@kms_psr@psr-sprite-mmap-gtt@edp-1:
- shard-mtlp: NOTRUN -> [SKIP][236] ([i915#4077] / [i915#9688])
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_psr@psr-sprite-mmap-gtt@edp-1.html
* igt@kms_psr@psr2-sprite-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][237] ([i915#1072] / [i915#9732]) +22 other tests skip
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-15/igt@kms_psr@psr2-sprite-mmap-gtt.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-dg2: NOTRUN -> [SKIP][238] ([i915#9685]) +1 other test skip
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_rotation_crc@primary-rotation-270:
- shard-mtlp: NOTRUN -> [SKIP][239] ([i915#4235])
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_rotation_crc@primary-rotation-270.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-mtlp: NOTRUN -> [SKIP][240] ([i915#5289])
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-rkl: NOTRUN -> [SKIP][241] ([i915#5289]) +2 other tests skip
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-dg2: NOTRUN -> [SKIP][242] ([i915#4235]) +1 other test skip
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@kms_setmode@basic-clone-single-crtc:
- shard-dg1: NOTRUN -> [SKIP][243] ([i915#3555]) +4 other tests skip
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-13/igt@kms_setmode@basic-clone-single-crtc.html
* igt@kms_setmode@invalid-clone-exclusive-crtc:
- shard-mtlp: NOTRUN -> [SKIP][244] ([i915#3555] / [i915#8823])
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_setmode@invalid-clone-exclusive-crtc.html
* igt@kms_sysfs_edid_timing:
- shard-dg1: NOTRUN -> [FAIL][245] ([IGT#2] / [i915#6493])
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-13/igt@kms_sysfs_edid_timing.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1:
- shard-tglu: [PASS][246] -> [FAIL][247] ([i915#9196])
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-tglu-6/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-5/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
* igt@kms_vrr@flip-basic-fastset:
- shard-tglu: NOTRUN -> [SKIP][248] ([i915#9906])
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-8/igt@kms_vrr@flip-basic-fastset.html
* igt@kms_vrr@flipline:
- shard-mtlp: NOTRUN -> [SKIP][249] ([i915#3555] / [i915#8808])
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@kms_vrr@flipline.html
* igt@kms_vrr@seamless-rr-switch-drrs:
- shard-dg2: NOTRUN -> [SKIP][250] ([i915#9906])
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@kms_vrr@seamless-rr-switch-drrs.html
* igt@kms_vrr@seamless-rr-switch-vrr:
- shard-dg1: NOTRUN -> [SKIP][251] ([i915#9906])
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-15/igt@kms_vrr@seamless-rr-switch-vrr.html
* igt@kms_writeback@writeback-check-output:
- shard-dg2: NOTRUN -> [SKIP][252] ([i915#2437])
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-2/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id:
- shard-rkl: NOTRUN -> [SKIP][253] ([i915#2437])
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-6/igt@kms_writeback@writeback-fb-id.html
- shard-dg1: NOTRUN -> [SKIP][254] ([i915#2437])
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-16/igt@kms_writeback@writeback-fb-id.html
* igt@perf@mi-rpc:
- shard-rkl: NOTRUN -> [SKIP][255] ([i915#2434])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@perf@mi-rpc.html
* igt@perf@per-context-mode-unprivileged:
- shard-rkl: NOTRUN -> [SKIP][256] ([i915#2435])
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-3/igt@perf@per-context-mode-unprivileged.html
* igt@perf_pmu@frequency@gt0:
- shard-dg2: NOTRUN -> [FAIL][257] ([i915#6806])
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-2/igt@perf_pmu@frequency@gt0.html
* igt@prime_vgem@basic-fence-read:
- shard-dg2: NOTRUN -> [SKIP][258] ([i915#3291] / [i915#3708]) +1 other test skip
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-gtt:
- shard-mtlp: NOTRUN -> [SKIP][259] ([i915#3708] / [i915#4077])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-read:
- shard-dg1: NOTRUN -> [SKIP][260] ([i915#3708])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-14/igt@prime_vgem@basic-read.html
* igt@prime_vgem@fence-flip-hang:
- shard-dg2: NOTRUN -> [SKIP][261] ([i915#3708]) +1 other test skip
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@prime_vgem@fence-flip-hang.html
* igt@prime_vgem@fence-read-hang:
- shard-mtlp: NOTRUN -> [SKIP][262] ([i915#3708])
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@prime_vgem@fence-read-hang.html
* igt@sriov_basic@bind-unbind-vf:
- shard-rkl: NOTRUN -> [SKIP][263] ([i915#9917])
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-5/igt@sriov_basic@bind-unbind-vf.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-dg1: NOTRUN -> [SKIP][264] ([i915#9917])
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-15/igt@sriov_basic@enable-vfs-autoprobe-on.html
* igt@syncobj_timeline@invalid-wait-zero-handles:
- shard-mtlp: NOTRUN -> [FAIL][265] ([i915#9781])
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@syncobj_timeline@invalid-wait-zero-handles.html
* igt@v3d/v3d_get_param@get-bad-param:
- shard-dg1: NOTRUN -> [SKIP][266] ([i915#2575]) +9 other tests skip
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-13/igt@v3d/v3d_get_param@get-bad-param.html
* igt@v3d/v3d_mmap@mmap-bo:
- shard-mtlp: NOTRUN -> [SKIP][267] ([i915#2575]) +4 other tests skip
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@v3d/v3d_mmap@mmap-bo.html
* igt@v3d/v3d_submit_cl@simple-flush-cache:
- shard-dg2: NOTRUN -> [SKIP][268] ([i915#2575]) +8 other tests skip
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@v3d/v3d_submit_cl@simple-flush-cache.html
* igt@vc4/vc4_dmabuf_poll@poll-write-waits-until-write-done:
- shard-dg1: NOTRUN -> [SKIP][269] ([i915#7711]) +8 other tests skip
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-16/igt@vc4/vc4_dmabuf_poll@poll-write-waits-until-write-done.html
* igt@vc4/vc4_label_bo@set-label:
- shard-rkl: NOTRUN -> [SKIP][270] ([i915#7711]) +6 other tests skip
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-6/igt@vc4/vc4_label_bo@set-label.html
* igt@vc4/vc4_perfmon@create-perfmon-exceed:
- shard-mtlp: NOTRUN -> [SKIP][271] ([i915#7711]) +5 other tests skip
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-8/igt@vc4/vc4_perfmon@create-perfmon-exceed.html
* igt@vc4/vc4_perfmon@get-values-invalid-perfmon:
- shard-dg2: NOTRUN -> [SKIP][272] ([i915#7711]) +5 other tests skip
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-2/igt@vc4/vc4_perfmon@get-values-invalid-perfmon.html
* igt@vc4/vc4_tiling@set-bad-flags:
- shard-tglu: NOTRUN -> [SKIP][273] ([i915#2575]) +5 other tests skip
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-8/igt@vc4/vc4_tiling@set-bad-flags.html
#### Possible fixes ####
* igt@gem_exec_endless@dispatch@bcs0:
- shard-dg2: [TIMEOUT][274] ([i915#3778] / [i915#7016]) -> [PASS][275]
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-dg2-8/igt@gem_exec_endless@dispatch@bcs0.html
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-6/igt@gem_exec_endless@dispatch@bcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglu: [FAIL][276] ([i915#2842]) -> [PASS][277] +1 other test pass
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-tglu-7/igt@gem_exec_fair@basic-none-share@rcs0.html
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-tglu-9/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-rkl: [FAIL][278] ([i915#2842]) -> [PASS][279] +1 other test pass
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-rkl-6/igt@gem_exec_fair@basic-none@vecs0.html
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-6/igt@gem_exec_fair@basic-none@vecs0.html
* igt@i915_power@sanity:
- shard-mtlp: [SKIP][280] ([i915#7984]) -> [PASS][281]
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-mtlp-1/igt@i915_power@sanity.html
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-7/igt@i915_power@sanity.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-180:
- shard-mtlp: [FAIL][282] ([i915#5138]) -> [PASS][283]
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-mtlp-2/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-6/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
* igt@kms_color@ctm-0-25@pipe-c:
- shard-dg2: [INCOMPLETE][284] -> [PASS][285]
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-dg2-1/igt@kms_color@ctm-0-25@pipe-c.html
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-2/igt@kms_color@ctm-0-25@pipe-c.html
* igt@kms_flip@flip-vs-panning-vs-hang@a-edp1:
- shard-mtlp: [INCOMPLETE][286] ([i915#6113]) -> [PASS][287]
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-mtlp-2/igt@kms_flip@flip-vs-panning-vs-hang@a-edp1.html
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-6/igt@kms_flip@flip-vs-panning-vs-hang@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a4:
- shard-dg1: [DMESG-WARN][288] ([i915#4423]) -> [PASS][289]
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-dg1-18/igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a4.html
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-18/igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a4.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-dg2: [SKIP][290] ([i915#9519]) -> [PASS][291] +1 other test pass
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-dg2-4/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-rkl: [SKIP][292] ([i915#9519]) -> [PASS][293]
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-rkl-1/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
- shard-snb: [FAIL][294] ([i915#9196]) -> [PASS][295] +1 other test pass
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-snb2/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-snb6/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
* igt@sysfs_timeslice_duration@timeout@ccs0:
- shard-mtlp: [ABORT][296] -> [PASS][297]
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-mtlp-1/igt@sysfs_timeslice_duration@timeout@ccs0.html
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-mtlp-6/igt@sysfs_timeslice_duration@timeout@ccs0.html
#### Warnings ####
* igt@gem_create@create-ext-cpu-access-big:
- shard-dg2: [INCOMPLETE][298] ([i915#9364]) -> [ABORT][299] ([i915#9846])
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-dg2-10/igt@gem_create@create-ext-cpu-access-big.html
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-7/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg1: [DMESG-WARN][300] ([i915#1982] / [i915#4936] / [i915#5493]) -> [TIMEOUT][301] ([i915#5493])
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-dg1-16/igt@gem_lmem_swapping@smem-oom@lmem0.html
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg1-15/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary:
- shard-dg2: [SKIP][302] ([i915#10433] / [i915#3458]) -> [SKIP][303] ([i915#3458]) +1 other test skip
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary.html
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-dg2: [SKIP][304] ([i915#3458]) -> [SKIP][305] ([i915#10433] / [i915#3458]) +3 other tests skip
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_psr@fbc-pr-primary-render:
- shard-dg2: [SKIP][306] ([i915#1072] / [i915#9732]) -> [SKIP][307] ([i915#1072] / [i915#9673] / [i915#9732]) +4 other tests skip
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-dg2-5/igt@kms_psr@fbc-pr-primary-render.html
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-11/igt@kms_psr@fbc-pr-primary-render.html
* igt@kms_psr@psr-cursor-render:
- shard-dg2: [SKIP][308] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][309] ([i915#1072] / [i915#9732]) +13 other tests skip
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-dg2-11/igt@kms_psr@psr-cursor-render.html
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-10/igt@kms_psr@psr-cursor-render.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: [CRASH][310] ([i915#9351]) -> [INCOMPLETE][311] ([i915#5493])
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/shard-dg2-5/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/shard-dg2-11/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
[i915#10139]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10139
[i915#10166]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10166
[i915#10278]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10278
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10513]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10513
[i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#11072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11072
[i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
[i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
[i915#2435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2435
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
[i915#3778]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3778
[i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
[i915#3826]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#3936]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3936
[i915#4036]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4036
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4087
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
[i915#4473]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4473
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4879]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4879
[i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
[i915#4936]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4936
[i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5235
[i915#5274]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
[i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
[i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6113]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6113
[i915#6188]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6188
[i915#6227]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6227
[i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
[i915#6268]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
[i915#6412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6412
[i915#6493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6493
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
[i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
[i915#6806]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6806
[i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
[i915#7016]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7016
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7213
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7711]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7711
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
[i915#8063]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8063
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8292]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8292
[i915#8346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8346
[i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
[i915#8437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8437
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
[i915#8808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8808
[i915#8810]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8810
[i915#8812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8812
[i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
[i915#8823]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8823
[i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
[i915#9227]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9227
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
[i915#9351]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9351
[i915#9364]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9364
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9606]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9606
[i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
[i915#9728]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9728
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
[i915#9781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9781
[i915#9808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9808
[i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9833]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9833
[i915#9846]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9846
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_14747 -> Patchwork_133458v1
CI-20190529: 20190529
CI_DRM_14747: b885b00e7fc01fc109887d59ce2d1283714b07c6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7846: 4a5fd4e7cb2798636f6464e2bd61399f3242b322 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_133458v1: b885b00e7fc01fc109887d59ce2d1283714b07c6 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/index.html
[-- Attachment #2: Type: text/html, Size: 109055 bytes --]
^ permalink raw reply [flat|nested] 48+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: skl+ plane register stuff (rev6)
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
` (17 preceding siblings ...)
2024-05-11 20:02 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2024-05-13 18:39 ` Patchwork
2024-05-13 18:39 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
21 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2024-05-13 18:39 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: skl+ plane register stuff (rev6)
URL : https://patchwork.freedesktop.org/series/133458/
State : warning
== Summary ==
Error: dim checkpatch failed
6783d48ac30b drm/i915: Nuke _MMIO_PLANE_GAMC()
6d5c913cfe2c drm/i915: Extract skl_universal_plane_regs.h
-:54: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
-:74: WARNING:LONG_LINE_COMMENT: line length of 104 exceeds 100 columns
#74: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:16:
+#define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
-:238: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#238: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:180:
+#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
-:239: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#239: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:181:
+#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
-:240: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#240: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:182:
+#define PLANE_CC_VAL(pipe, plane, dw) \
+ _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
-:240: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dw' - possible side-effects?
#240: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:182:
+#define PLANE_CC_VAL(pipe, plane, dw) \
+ _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
-:257: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#257: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:199:
+#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
-:257: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#257: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:199:
+#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
-:273: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#273: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:215:
+#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
-:273: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#273: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:215:
+#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
-:289: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#289: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:231:
+#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
-:289: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#289: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:231:
+#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
+ _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
-:299: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#299: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:241:
+#define PLANE_CTL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
-:311: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#311: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:253:
+#define PLANE_STRIDE(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
-:320: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#320: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:262:
+#define PLANE_POS(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
-:329: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#329: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:271:
+#define PLANE_SIZE(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
-:338: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#338: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:280:
+#define PLANE_SURF(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
-:345: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#345: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:287:
+#define PLANE_OFFSET(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
-:352: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#352: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:294:
+#define PLANE_KEYVAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
-:359: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#359: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:301:
+#define PLANE_KEYMSK(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
-:366: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#366: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:308:
+#define PLANE_KEYMAX(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
-:373: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#373: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:315:
+#define PLANE_SURFLIVE(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
-:380: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#380: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:322:
+#define PLANE_CHICKEN(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
-:389: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#389: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:331:
+#define PLANE_AUX_DIST(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
-:398: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#398: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:340:
+#define PLANE_AUX_OFFSET(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
-:407: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#407: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:349:
+#define PLANE_CUS_CTL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
-:417: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#417: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:359:
+#define PLANE_COLOR_CTL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
-:431: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#431: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:373:
+#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
+ _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
+ _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
-:431: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#431: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:373:
+#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
+ _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
+ _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
-:432: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#432: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:374:
+ _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
-:445: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#445: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:387:
+#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
+ (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
+ (index) * 4)
-:445: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#445: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:387:
+#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
+ (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
+ (index) * 4)
-:446: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#446: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:388:
+ (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
-:459: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#459: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:401:
+#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
+ (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
+ (index) * 4)
-:459: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#459: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:401:
+#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
+ (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
+ (index) * 4)
-:460: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#460: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:402:
+ (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
total: 0 errors, 7 warnings, 29 checks, 872 lines checked
eafee33357cc drm/i915: Extract intel_cursor_regs.h
-:30: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#30:
new file mode 100644
-:50: WARNING:LONG_LINE_COMMENT: line length of 103 exceeds 100 columns
#50: FILE: drivers/gpu/drm/i915/display/intel_cursor_regs.h:16:
+#define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */
total: 0 errors, 2 warnings, 0 checks, 202 lines checked
c62c87986903 drm/i915: Move skl+ wm/ddb registers to proper headers
-:77: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#77: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:428:
+#define _PLANE_WM_BASE(pipe, plane) \
+ _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
-:85: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#85: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:436:
+#define PLANE_WM_SAGV(pipe, plane) \
+ _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
-:91: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#91: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:442:
+#define PLANE_WM_SAGV_TRANS(pipe, plane) \
+ _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
-:97: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#97: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:448:
+#define PLANE_WM_TRANS(pipe, plane) \
+ _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
-:106: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#106: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:457:
+#define PLANE_BUF_CFG(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
-:115: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#115: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:466:
+#define PLANE_NV12_BUF_CFG(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
total: 0 errors, 0 warnings, 6 checks, 195 lines checked
b8ac7f29b1b5 drm/i915/gvt: Use the proper PLANE_AUX_DIST() define
cc20f9ed36df drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() define
73f3a653e90a drm/i915/gvt: Use the full PLANE_KEY*() defines
e817a8ace197 drm/i915/gvt: Use PLANE_CTL and PLANE_SURF defines
1ab9fe806f87 drm/i915: Drop useless PLANE_FOO_3 register defines
e748cd4971b8 drm/i915: Shuffle the skl+ plane register definitions
-:31: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#31: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:17:
+#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
-:46: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#46: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:88:
+#define PLANE_STRIDE(pipe, plane) _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
-:46: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#46: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:88:
+#define PLANE_STRIDE(pipe, plane) _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
-:56: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#56: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:98:
+#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
-:68: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#68: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:110:
+#define PLANE_SIZE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
-:80: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#80: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:122:
+#define PLANE_KEYVAL(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
-:80: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#80: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:122:
+#define PLANE_KEYVAL(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
-:88: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#88: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:130:
+#define PLANE_KEYMSK(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
-:88: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#88: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:130:
+#define PLANE_KEYMSK(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
-:97: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#97: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:139:
+#define PLANE_SURF(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
-:107: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#107: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:149:
+#define PLANE_KEYMAX(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
-:107: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#107: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:149:
+#define PLANE_KEYMAX(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
-:117: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#117: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:159:
+#define PLANE_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
-:117: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#117: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:159:
+#define PLANE_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
-:138: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#138: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:171:
+#define PLANE_SURFLIVE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
-:138: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#138: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:171:
+#define PLANE_SURFLIVE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
-:144: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#144: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:177:
+#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
-:145: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#145: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:178:
+#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
-:146: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#146: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:179:
+#define PLANE_CC_VAL(pipe, plane, dw) _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
-:146: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#146: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:179:
+#define PLANE_CC_VAL(pipe, plane, dw) _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
-:146: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dw' - possible side-effects?
#146: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:179:
+#define PLANE_CC_VAL(pipe, plane, dw) _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
-:154: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#154: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:187:
+#define PLANE_AUX_DIST(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
-:154: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#154: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:187:
+#define PLANE_AUX_DIST(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
-:166: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#166: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:198:
+#define PLANE_AUX_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
-:166: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#166: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:198:
+#define PLANE_AUX_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
-:174: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#174: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:206:
+#define PLANE_CUS_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
-:174: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#174: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:206:
+#define PLANE_CUS_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
-:191: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#191: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:230:
+#define PLANE_COLOR_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
-:191: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#191: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:230:
+#define PLANE_COLOR_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
-:256: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#256: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:252:
+#define _PLANE_INPUT_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, _PLANE_INPUT_CSC_RY_GY_1_B)
-:257: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#257: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:253:
+#define _PLANE_INPUT_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, _PLANE_INPUT_CSC_RY_GY_2_B)
-:258: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#258: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:254:
+#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
-:258: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#258: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:254:
+#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
-:259: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#259: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:255:
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
-:265: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#265: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:261:
+#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, _PLANE_INPUT_CSC_PREOFF_HI_1_B)
-:266: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#266: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:262:
+#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, _PLANE_INPUT_CSC_PREOFF_HI_2_B)
-:267: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#267: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:263:
+#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
-:267: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#267: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:263:
+#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
-:268: WARNING:LONG_LINE: line length of 126 exceeds 100 columns
#268: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:264:
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
-:415: WARNING:LONG_LINE: line length of 125 exceeds 100 columns
#415: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:270:
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
-:416: WARNING:LONG_LINE: line length of 125 exceeds 100 columns
#416: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:271:
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
-:417: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#417: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:272:
+#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
-:417: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#417: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:272:
+#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
-:418: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#418: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:273:
+ _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
-:426: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#426: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:281:
+#define PLANE_CSC_COEFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
-:426: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#426: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:281:
+#define PLANE_CSC_COEFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
-:427: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#427: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:282:
+ _MMIO_PLANE(plane, _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
-:442: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#442: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:288:
+#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, _PLANE_CSC_PREOFF_HI_1_B)
-:443: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#443: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:289:
+#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, _PLANE_CSC_PREOFF_HI_2_B)
-:444: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#444: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:290:
+#define PLANE_CSC_PREOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + (index) * 4)
-:444: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#444: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:290:
+#define PLANE_CSC_PREOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + (index) * 4)
-:445: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#445: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:291:
+ _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + (index) * 4)
-:452: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#452: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:297:
+#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, _PLANE_CSC_POSTOFF_HI_1_B)
-:453: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#453: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:298:
+#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, _PLANE_CSC_POSTOFF_HI_2_B)
-:454: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#454: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:299:
+#define PLANE_CSC_POSTOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
-:454: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#454: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:299:
+#define PLANE_CSC_POSTOFF(pipe, plane, index) \
+ _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
-:455: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#455: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:300:
+ _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
-:463: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#463: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:308:
+#define _PLANE_WM_BASE(pipe, plane) _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
-:476: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#476: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:321:
+#define PLANE_WM_SAGV(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
-:476: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#476: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:321:
+#define PLANE_WM_SAGV(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
-:482: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#482: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:327:
+#define _PLANE_WM_SAGV_TRANS_1(pipe) _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
-:483: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#483: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:328:
+#define _PLANE_WM_SAGV_TRANS_2(pipe) _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
-:484: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#484: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:329:
+#define PLANE_WM_SAGV_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
-:484: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#484: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:329:
+#define PLANE_WM_SAGV_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
-:492: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#492: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:337:
+#define PLANE_WM_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
-:492: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#492: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:337:
+#define PLANE_WM_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
-:500: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#500: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:345:
+#define PLANE_CHICKEN(pipe, plane) _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
-:500: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#500: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:345:
+#define PLANE_CHICKEN(pipe, plane) _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
-:560: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#560: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:352:
+#define _PLANE_NV12_BUF_CFG_1(pipe) _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
-:561: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#561: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:353:
+#define _PLANE_NV12_BUF_CFG_2(pipe) _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
-:562: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#562: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:354:
+#define PLANE_NV12_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
-:562: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#562: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:354:
+#define PLANE_NV12_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
-:585: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#585: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:362:
+#define PLANE_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
-:585: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#585: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:362:
+#define PLANE_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
total: 0 errors, 39 warnings, 35 checks, 566 lines checked
555bc9400e83 drm/i915: Use REG_BIT for PLANE_WM bits
5088edc8324a drm/i915: Drop a few unwanted tabs from skl+ plane reg defines
924eec4d89d3 drm/i915: Refactor skl+ plane register offset calculations
-:28: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#28: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:11:
+#define _SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
+ _PLANE((plane), _PIPE((pipe), (reg_1_a), (reg_1_b)), _PIPE((pipe), (reg_2_a), (reg_2_b)))
-:194: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#194: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:206:
+ _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B, \
-:195: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#195: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:207:
+ _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
-:218: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#218: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:238:
+ _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B, \
-:231: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#231: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:261:
+#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
-:232: WARNING:LONG_LINE: line length of 132 exceeds 100 columns
#232: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:262:
+ _PLANE_INPUT_CSC_RY_GY_1_A, _PLANE_INPUT_CSC_RY_GY_1_B, \
-:233: WARNING:LONG_LINE: line length of 130 exceeds 100 columns
#233: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:263:
+ _PLANE_INPUT_CSC_RY_GY_2_A, _PLANE_INPUT_CSC_RY_GY_2_B)
-:243: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#243: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:269:
+#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
-:244: WARNING:LONG_LINE: line length of 140 exceeds 100 columns
#244: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:270:
+ _PLANE_INPUT_CSC_PREOFF_HI_1_A, _PLANE_INPUT_CSC_PREOFF_HI_1_B, \
-:245: WARNING:LONG_LINE: line length of 138 exceeds 100 columns
#245: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:271:
+ _PLANE_INPUT_CSC_PREOFF_HI_2_A, _PLANE_INPUT_CSC_PREOFF_HI_2_B)
-:255: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#255: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:277:
+#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \
-:256: WARNING:LONG_LINE: line length of 142 exceeds 100 columns
#256: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:278:
+ _PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B, \
-:257: WARNING:LONG_LINE: line length of 140 exceeds 100 columns
#257: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:279:
+ _PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
-:268: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#268: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:286:
+ _PLANE_CSC_RY_GY_1_A, _PLANE_CSC_RY_GY_1_B, \
-:269: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#269: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:287:
+ _PLANE_CSC_RY_GY_2_A, _PLANE_CSC_RY_GY_2_B)
-:280: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#280: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:294:
+ _PLANE_CSC_PREOFF_HI_1_A, _PLANE_CSC_PREOFF_HI_1_B, \
-:281: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#281: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:295:
+ _PLANE_CSC_PREOFF_HI_2_A, _PLANE_CSC_PREOFF_HI_2_B)
-:293: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#293: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:302:
+ _PLANE_CSC_POSTOFF_HI_1_A, _PLANE_CSC_POSTOFF_HI_1_B, \
-:294: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#294: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:303:
+ _PLANE_CSC_POSTOFF_HI_2_A, _PLANE_CSC_POSTOFF_HI_2_B)
-:328: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#328: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:329:
+ _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B, \
-:329: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#329: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:330:
+ _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
-:362: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#362: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:354:
+ _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B, \
-:363: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#363: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:355:
+ _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
total: 0 errors, 22 warnings, 1 checks, 342 lines checked
8c6673e92204 drm/i915: Extract skl_plane_{wm,ddb}_reg_val()
27aad4ac3d37 drm/i915: Nuke skl_write_wm_level() and skl_ddb_entry_write()
-:69: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#69: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:2406:
+ skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
-:109: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#109: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:2441:
+ skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
total: 0 errors, 2 warnings, 0 checks, 97 lines checked
fe650503f642 drm/i915: Handle SKL+ WM/DDB registers next to all other plane registers
-:51: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#51: FILE: drivers/gpu/drm/i915/display/intel_cursor.c:573:
+ skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
-:118: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#118: FILE: drivers/gpu/drm/i915/display/skl_universal_plane.c:663:
+ skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
total: 0 errors, 2 warnings, 0 checks, 269 lines checked
^ permalink raw reply [flat|nested] 48+ messages in thread* ✗ Fi.CI.SPARSE: warning for drm/i915: skl+ plane register stuff (rev6)
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
` (18 preceding siblings ...)
2024-05-13 18:39 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: skl+ plane register stuff (rev6) Patchwork
@ 2024-05-13 18:39 ` Patchwork
2024-05-13 18:55 ` ✓ Fi.CI.BAT: success " Patchwork
2024-05-14 2:01 ` ✗ Fi.CI.IGT: failure " Patchwork
21 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2024-05-13 18:39 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: skl+ plane register stuff (rev6)
URL : https://patchwork.freedesktop.org/series/133458/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced
^ permalink raw reply [flat|nested] 48+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: skl+ plane register stuff (rev6)
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
` (19 preceding siblings ...)
2024-05-13 18:39 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2024-05-13 18:55 ` Patchwork
2024-05-14 2:01 ` ✗ Fi.CI.IGT: failure " Patchwork
21 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2024-05-13 18:55 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
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== Series Details ==
Series: drm/i915: skl+ plane register stuff (rev6)
URL : https://patchwork.freedesktop.org/series/133458/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14756 -> Patchwork_133458v6
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/index.html
Participating hosts (42 -> 40)
------------------------------
Additional (2): bat-dg2-11 fi-elk-e7500
Missing (4): bat-dg1-7 bat-kbl-2 fi-snb-2520m bat-mtlp-6
Known issues
------------
Here are the changes found in Patchwork_133458v6 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap@basic:
- bat-dg2-11: NOTRUN -> [SKIP][1] ([i915#4083])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@gem_mmap@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg2-11: NOTRUN -> [SKIP][2] ([i915#4077]) +2 other tests skip
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@gem_tiled_fence_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg2-11: NOTRUN -> [SKIP][3] ([i915#4079]) +1 other test skip
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-dg2-11: NOTRUN -> [SKIP][4] ([i915#6621])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@i915_pm_rps@basic-api.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#4212]) +7 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#5190])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#4215] / [i915#5190])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#4103] / [i915#4213]) +1 other test skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_dsc@dsc-basic:
- bat-dg2-11: NOTRUN -> [SKIP][9] ([i915#3555] / [i915#3840])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-11: NOTRUN -> [SKIP][10]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#5274])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_pm_backlight@basic-brightness:
- bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#5354])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_pm_rpm@basic-pci-d3-state:
- fi-elk-e7500: NOTRUN -> [SKIP][13] +24 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/fi-elk-e7500/igt@kms_pm_rpm@basic-pci-d3-state.html
* igt@kms_psr@psr-sprite-plane-onoff:
- bat-dg2-11: NOTRUN -> [SKIP][14] ([i915#1072] / [i915#9732]) +3 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@kms_psr@psr-sprite-plane-onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg2-11: NOTRUN -> [SKIP][15] ([i915#3555])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-dg2-11: NOTRUN -> [SKIP][16] ([i915#3708])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-dg2-11: NOTRUN -> [SKIP][17] ([i915#3708] / [i915#4077]) +1 other test skip
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-read:
- bat-dg2-11: NOTRUN -> [SKIP][18] ([i915#3291] / [i915#3708]) +2 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@prime_vgem@basic-read.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [ABORT][19] ([i915#10594]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
[i915#10594]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10594
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4215
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
Build changes
-------------
* Linux: CI_DRM_14756 -> Patchwork_133458v6
CI-20190529: 20190529
CI_DRM_14756: 3d00e04692d45ab076e9e493252361bb18373a0e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7849: c09431db6f7d5a2ddeb42e10a119d1cb7fa071d0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_133458v6: 3d00e04692d45ab076e9e493252361bb18373a0e @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/index.html
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^ permalink raw reply [flat|nested] 48+ messages in thread* ✗ Fi.CI.IGT: failure for drm/i915: skl+ plane register stuff (rev6)
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
` (20 preceding siblings ...)
2024-05-13 18:55 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2024-05-14 2:01 ` Patchwork
21 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2024-05-14 2:01 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
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== Series Details ==
Series: drm/i915: skl+ plane register stuff (rev6)
URL : https://patchwork.freedesktop.org/series/133458/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14756_full -> Patchwork_133458v6_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_133458v6_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_133458v6_full, please notify your bug team ('I915-ci-infra@lists.freedesktop.org') to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_133458v6_full:
### IGT changes ###
#### Possible regressions ####
* igt@drm_read@short-buffer-wakeup:
- shard-dg2: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-2/igt@drm_read@short-buffer-wakeup.html
Known issues
------------
Here are the changes found in Patchwork_133458v6_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@drm_fdinfo@virtual-busy-all:
- shard-mtlp: NOTRUN -> [SKIP][2] ([i915#8414])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@drm_fdinfo@virtual-busy-all.html
* igt@drm_fdinfo@virtual-busy-hang-all:
- shard-dg2: NOTRUN -> [SKIP][3] ([i915#8414])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@drm_fdinfo@virtual-busy-hang-all.html
* igt@gem_busy@close-race:
- shard-mtlp: [PASS][4] -> [ABORT][5] ([i915#10182])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-mtlp-2/igt@gem_busy@close-race.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-3/igt@gem_busy@close-race.html
* igt@gem_ccs@ctrl-surf-copy:
- shard-mtlp: NOTRUN -> [SKIP][6] ([i915#3555] / [i915#9323])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@gem_ccs@ctrl-surf-copy.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-dg2: NOTRUN -> [INCOMPLETE][7] ([i915#9364])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglu: [PASS][8] -> [FAIL][9] ([i915#6268])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-tglu-4/igt@gem_ctx_exec@basic-nohangcheck.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-tglu-7/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_persistence@engines-mixed-process:
- shard-snb: NOTRUN -> [SKIP][10] ([i915#1099]) +1 other test skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-snb2/igt@gem_ctx_persistence@engines-mixed-process.html
* igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0:
- shard-dg2: NOTRUN -> [SKIP][11] ([i915#5882]) +6 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0.html
* igt@gem_exec_balancer@bonded-false-hang:
- shard-mtlp: NOTRUN -> [SKIP][12] ([i915#4812])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@gem_exec_balancer@bonded-false-hang.html
* igt@gem_exec_balancer@bonded-semaphore:
- shard-dg2: NOTRUN -> [SKIP][13] ([i915#4812])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@gem_exec_balancer@bonded-semaphore.html
* igt@gem_exec_balancer@invalid-bonds:
- shard-dg2: NOTRUN -> [SKIP][14] ([i915#4036])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@gem_exec_balancer@invalid-bonds.html
* igt@gem_exec_balancer@noheartbeat:
- shard-mtlp: NOTRUN -> [SKIP][15] ([i915#8555])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@gem_exec_balancer@noheartbeat.html
* igt@gem_exec_capture@capture-invisible@smem0:
- shard-glk: NOTRUN -> [SKIP][16] ([i915#6334])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-glk3/igt@gem_exec_capture@capture-invisible@smem0.html
* igt@gem_exec_capture@many-4k-zero:
- shard-glk: NOTRUN -> [FAIL][17] ([i915#9606])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-glk1/igt@gem_exec_capture@many-4k-zero.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: NOTRUN -> [FAIL][18] ([i915#2842])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-rkl: [PASS][19] -> [FAIL][20] ([i915#2842])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-rkl-6/igt@gem_exec_fair@basic-none-solo@rcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-rkl-3/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglu: [PASS][21] -> [FAIL][22] ([i915#2842])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-tglu-8/igt@gem_exec_fair@basic-pace-share@rcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-tglu-8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_flush@basic-batch-kernel-default-wb:
- shard-dg2: NOTRUN -> [SKIP][23] ([i915#3539] / [i915#4852])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@gem_exec_flush@basic-batch-kernel-default-wb.html
* igt@gem_exec_reloc@basic-cpu-wc-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][24] ([i915#3281]) +3 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@gem_exec_reloc@basic-cpu-wc-noreloc.html
* igt@gem_exec_reloc@basic-gtt-cpu-noreloc:
- shard-dg2: NOTRUN -> [SKIP][25] ([i915#3281]) +3 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@gem_exec_reloc@basic-gtt-cpu-noreloc.html
* igt@gem_exec_schedule@reorder-wide:
- shard-dg2: NOTRUN -> [SKIP][26] ([i915#4537] / [i915#4812]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@gem_exec_schedule@reorder-wide.html
* igt@gem_fenced_exec_thrash@too-many-fences:
- shard-mtlp: NOTRUN -> [SKIP][27] ([i915#4860])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@gem_fenced_exec_thrash@too-many-fences.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0:
- shard-dg2: [PASS][28] -> [FAIL][29] ([i915#10378]) +1 other test fail
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-dg2-2/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-4/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
* igt@gem_lmem_swapping@smem-oom:
- shard-glk: NOTRUN -> [SKIP][30] ([i915#4613]) +3 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-glk3/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_mmap_gtt@basic-small-bo-tiledx:
- shard-mtlp: NOTRUN -> [SKIP][31] ([i915#4077]) +5 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@gem_mmap_gtt@basic-small-bo-tiledx.html
* igt@gem_mmap_wc@fault-concurrent:
- shard-dg2: NOTRUN -> [SKIP][32] ([i915#4083])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@gem_mmap_wc@fault-concurrent.html
* igt@gem_mmap_wc@read:
- shard-mtlp: NOTRUN -> [SKIP][33] ([i915#4083]) +1 other test skip
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@gem_mmap_wc@read.html
* igt@gem_pread@exhaustion:
- shard-dg2: NOTRUN -> [SKIP][34] ([i915#3282])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@gem_pread@exhaustion.html
* igt@gem_pxp@create-valid-protected-context:
- shard-mtlp: NOTRUN -> [SKIP][35] ([i915#4270]) +1 other test skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@gem_pxp@create-valid-protected-context.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs:
- shard-mtlp: NOTRUN -> [SKIP][36] ([i915#8428])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
- shard-dg2: NOTRUN -> [SKIP][37] ([i915#5190] / [i915#8428]) +1 other test skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-2/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@gem_softpin@evict-snoop:
- shard-mtlp: NOTRUN -> [SKIP][38] ([i915#4885])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@gem_softpin@evict-snoop.html
* igt@gem_softpin@evict-snoop-interruptible:
- shard-dg2: NOTRUN -> [SKIP][39] ([i915#4885])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@gem_softpin@evict-snoop-interruptible.html
* igt@gem_tiled_pread_pwrite:
- shard-dg2: NOTRUN -> [SKIP][40] ([i915#4079])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-2/igt@gem_tiled_pread_pwrite.html
* igt@gem_tiling_max_stride:
- shard-dg2: NOTRUN -> [SKIP][41] ([i915#4077]) +1 other test skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@gem_tiling_max_stride.html
* igt@gem_userptr_blits@forbidden-operations:
- shard-dg2: NOTRUN -> [SKIP][42] ([i915#3282] / [i915#3297])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@gem_userptr_blits@forbidden-operations.html
* igt@gem_userptr_blits@readonly-unsync:
- shard-mtlp: NOTRUN -> [SKIP][43] ([i915#3297])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@gem_userptr_blits@readonly-unsync.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-mtlp: NOTRUN -> [SKIP][44] ([i915#2856])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@gen9_exec_parse@batch-invalid-length.html
* igt@gen9_exec_parse@unaligned-jump:
- shard-dg2: NOTRUN -> [SKIP][45] ([i915#2856])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@gen9_exec_parse@unaligned-jump.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-mtlp: [PASS][46] -> [ABORT][47] ([i915#10131] / [i915#10887] / [i915#9820])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-mtlp-7/igt@i915_module_load@reload-with-fault-injection.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_power@sanity:
- shard-mtlp: [PASS][48] -> [SKIP][49] ([i915#7984])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-mtlp-4/igt@i915_power@sanity.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-6/igt@i915_power@sanity.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-mtlp: NOTRUN -> [SKIP][50] ([i915#6645])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- shard-dg2: NOTRUN -> [SKIP][51] ([i915#5190])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][52] ([i915#8709]) +11 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-dg2: NOTRUN -> [SKIP][53] ([i915#4538] / [i915#5190]) +2 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180:
- shard-mtlp: NOTRUN -> [SKIP][54] +2 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-snb: NOTRUN -> [SKIP][55] +54 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-snb2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_joiner@basic-force-joiner:
- shard-dg2: NOTRUN -> [SKIP][56] ([i915#10656])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-3/igt@kms_big_joiner@basic-force-joiner.html
* igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][57] ([i915#6095]) +3 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-b-edp-1.html
* igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-b-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][58] ([i915#10307] / [i915#6095]) +126 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-b-hdmi-a-3.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][59] ([i915#10307] / [i915#10434] / [i915#6095])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-4/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][60] ([i915#6095]) +79 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg1-13/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-a-hdmi-a-3.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][61] ([i915#6095]) +29 other tests skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-rkl-1/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [SKIP][62] +185 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-glk3/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-1.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][63] ([i915#7213]) +3 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-5/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html
* igt@kms_chamelium_audio@dp-audio-edid:
- shard-dg2: NOTRUN -> [SKIP][64] ([i915#7828]) +2 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@kms_chamelium_audio@dp-audio-edid.html
* igt@kms_chamelium_audio@hdmi-audio:
- shard-mtlp: NOTRUN -> [SKIP][65] ([i915#7828]) +2 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@kms_chamelium_audio@hdmi-audio.html
* igt@kms_content_protection@legacy@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [TIMEOUT][66] ([i915#7173])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-11/igt@kms_content_protection@legacy@pipe-a-dp-4.html
* igt@kms_content_protection@srm:
- shard-dg2: NOTRUN -> [SKIP][67] ([i915#7118])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@kms_content_protection@srm.html
* igt@kms_content_protection@type1:
- shard-mtlp: NOTRUN -> [SKIP][68] ([i915#3555] / [i915#6944] / [i915#9424])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-mtlp: NOTRUN -> [SKIP][69] ([i915#3359])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
- shard-mtlp: NOTRUN -> [SKIP][70] ([i915#9809])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: NOTRUN -> [FAIL][71] ([i915#2346])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][72] ([i915#9723])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-rkl-6/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-2.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][73] ([i915#9723])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg1-16/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-4.html
* igt@kms_dp_aux_dev:
- shard-dg2: [PASS][74] -> [SKIP][75] ([i915#1257])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-dg2-11/igt@kms_dp_aux_dev.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-3/igt@kms_dp_aux_dev.html
* igt@kms_dsc@dsc-basic:
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#3555] / [i915#3840])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-2/igt@kms_dsc@dsc-basic.html
* igt@kms_feature_discovery@display-2x:
- shard-mtlp: NOTRUN -> [SKIP][77] ([i915#1839])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@kms_feature_discovery@display-2x.html
* igt@kms_feature_discovery@dp-mst:
- shard-dg2: NOTRUN -> [SKIP][78] ([i915#9337])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@kms_feature_discovery@dp-mst.html
* igt@kms_flip@2x-flip-vs-panning-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][79] ([i915#3637]) +1 other test skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@kms_flip@2x-flip-vs-panning-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][80] ([i915#2672])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][81] ([i915#2672] / [i915#3555])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][82] ([i915#8708]) +2 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-rte:
- shard-dg2: NOTRUN -> [SKIP][83] ([i915#5354]) +12 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-2p-rte.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][84] ([i915#8708]) +3 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu:
- shard-mtlp: NOTRUN -> [SKIP][85] ([i915#1825]) +6 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt:
- shard-dg2: NOTRUN -> [SKIP][86] ([i915#3458]) +3 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-dg2: NOTRUN -> [SKIP][87] ([i915#3555] / [i915#8228]) +1 other test skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [FAIL][88] ([i915#10647]) +1 other test fail
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-glk5/igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-dg2: NOTRUN -> [SKIP][89] ([i915#6953] / [i915#9423])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-5/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][90] ([i915#9423]) +5 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-rkl-1/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][91] ([i915#9423]) +15 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg1-15/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-hdmi-a-4.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][92] ([i915#5176] / [i915#9423]) +1 other test skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-rkl-1/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][93] ([i915#5176] / [i915#9423]) +3 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg1-16/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][94] ([i915#5235]) +7 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg1-15/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][95] ([i915#5235] / [i915#9423]) +3 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-7/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][96] ([i915#5235]) +2 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-edp-1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][97] ([i915#3555] / [i915#5235])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d-edp-1.html
* igt@kms_pm_dc@dc6-dpms:
- shard-tglu: [PASS][98] -> [FAIL][99] ([i915#9295])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-tglu-2/igt@kms_pm_dc@dc6-dpms.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-tglu-9/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-rkl: NOTRUN -> [SKIP][100] ([i915#9340])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-rkl-1/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-dg2: NOTRUN -> [SKIP][101] ([i915#9519])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@kms_pm_rpm@modeset-lpsp-stress.html
- shard-rkl: [PASS][102] -> [SKIP][103] ([i915#9519])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-rkl-2/igt@kms_pm_rpm@modeset-lpsp-stress.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-rkl-6/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-mtlp: NOTRUN -> [SKIP][104] ([i915#9519])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_prime@basic-modeset-hybrid:
- shard-mtlp: NOTRUN -> [SKIP][105] ([i915#6524])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@kms_prime@basic-modeset-hybrid.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-dg2: NOTRUN -> [SKIP][106] +5 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr2_sf@fbc-primary-plane-update-sf-dmg-area@psr2-pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][107] ([i915#9808]) +1 other test skip
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@kms_psr2_sf@fbc-primary-plane-update-sf-dmg-area@psr2-pipe-a-edp-1.html
* igt@kms_psr@fbc-psr-primary-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][108] ([i915#1072] / [i915#9732]) +3 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-2/igt@kms_psr@fbc-psr-primary-mmap-cpu.html
* igt@kms_psr@pr-sprite-plane-onoff:
- shard-mtlp: NOTRUN -> [SKIP][109] ([i915#9688]) +2 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@kms_psr@pr-sprite-plane-onoff.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-mtlp: NOTRUN -> [SKIP][110] ([i915#4235]) +1 other test skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_rotation_crc@sprite-rotation-270:
- shard-dg2: NOTRUN -> [SKIP][111] ([i915#4235])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@kms_rotation_crc@sprite-rotation-270.html
* igt@kms_setmode@basic-clone-single-crtc:
- shard-dg2: NOTRUN -> [SKIP][112] ([i915#3555]) +2 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@kms_setmode@basic-clone-single-crtc.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-glk: NOTRUN -> [FAIL][113] ([i915#10959])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-glk5/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
- shard-snb: [PASS][114] -> [FAIL][115] ([i915#9196])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-snb6/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-snb4/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
- shard-rkl: [PASS][116] -> [FAIL][117] ([i915#9196])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-rkl-2/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-rkl-4/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1:
- shard-mtlp: [PASS][118] -> [FAIL][119] ([i915#9196])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-mtlp-4/igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-6/igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1:
- shard-tglu: [PASS][120] -> [FAIL][121] ([i915#9196]) +1 other test fail
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-tglu-7/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-tglu-5/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-1.html
* igt@kms_vrr@flip-basic-fastset:
- shard-dg2: NOTRUN -> [SKIP][122] ([i915#9906])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-2/igt@kms_vrr@flip-basic-fastset.html
* igt@kms_writeback@writeback-check-output-xrgb2101010:
- shard-dg2: NOTRUN -> [SKIP][123] ([i915#2437] / [i915#9412])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-2/igt@kms_writeback@writeback-check-output-xrgb2101010.html
* igt@kms_writeback@writeback-fb-id:
- shard-mtlp: NOTRUN -> [SKIP][124] ([i915#2437])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-glk: NOTRUN -> [SKIP][125] ([i915#2437])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-glk3/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@perf_pmu@busy-double-start@vecs1:
- shard-dg2: [PASS][126] -> [FAIL][127] ([i915#4349]) +3 other tests fail
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-dg2-11/igt@perf_pmu@busy-double-start@vecs1.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-7/igt@perf_pmu@busy-double-start@vecs1.html
* igt@prime_vgem@fence-write-hang:
- shard-dg2: NOTRUN -> [SKIP][128] ([i915#3708])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-2/igt@prime_vgem@fence-write-hang.html
* igt@v3d/v3d_perfmon@get-values-invalid-pad:
- shard-mtlp: NOTRUN -> [SKIP][129] ([i915#2575]) +2 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@v3d/v3d_perfmon@get-values-invalid-pad.html
* igt@v3d/v3d_submit_cl@bad-multisync-out-sync:
- shard-dg2: NOTRUN -> [SKIP][130] ([i915#2575]) +2 other tests skip
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@v3d/v3d_submit_cl@bad-multisync-out-sync.html
* igt@vc4/vc4_perfmon@get-values-invalid-perfmon:
- shard-dg2: NOTRUN -> [SKIP][131] ([i915#7711]) +1 other test skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@vc4/vc4_perfmon@get-values-invalid-perfmon.html
* igt@vc4/vc4_perfmon@get-values-invalid-pointer:
- shard-mtlp: NOTRUN -> [SKIP][132] ([i915#7711]) +1 other test skip
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@vc4/vc4_perfmon@get-values-invalid-pointer.html
#### Possible fixes ####
* igt@gem_ctx_freq@sysfs@gt0:
- shard-dg2: [FAIL][133] ([i915#9561]) -> [PASS][134]
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-dg2-2/igt@gem_ctx_freq@sysfs@gt0.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-2/igt@gem_ctx_freq@sysfs@gt0.html
* igt@gem_eio@kms:
- shard-tglu: [INCOMPLETE][135] ([i915#10513]) -> [PASS][136]
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-tglu-8/igt@gem_eio@kms.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-tglu-3/igt@gem_eio@kms.html
- shard-dg2: [INCOMPLETE][137] ([i915#10513]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-dg2-5/igt@gem_eio@kms.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-11/igt@gem_eio@kms.html
* igt@gem_eio@reset-stress:
- shard-dg1: [FAIL][139] ([i915#5784]) -> [PASS][140]
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-dg1-17/igt@gem_eio@reset-stress.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg1-17/igt@gem_eio@reset-stress.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglu: [FAIL][141] ([i915#2842]) -> [PASS][142]
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-tglu-4/igt@gem_exec_fair@basic-none-share@rcs0.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-tglu-9/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-rkl: [FAIL][143] ([i915#2842]) -> [PASS][144] +1 other test pass
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-rkl-2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-rkl-4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_lmem_swapping@heavy-verify-random@lmem0:
- shard-dg2: [FAIL][145] ([i915#10378]) -> [PASS][146] +1 other test pass
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-dg2-1/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-1/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg2: [INCOMPLETE][147] ([i915#1982] / [i915#9820] / [i915#9849]) -> [PASS][148]
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-dg2-6/igt@i915_module_load@reload-with-fault-injection.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-2/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0:
- shard-dg1: [FAIL][149] ([i915#3591]) -> [PASS][150] +1 other test pass
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
* igt@i915_pm_rps@reset:
- shard-snb: [INCOMPLETE][151] ([i915#7790]) -> [PASS][152]
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-snb2/igt@i915_pm_rps@reset.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-snb2/igt@i915_pm_rps@reset.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-rkl: [FAIL][153] ([i915#10031]) -> [PASS][154]
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-rkl-4/igt@i915_suspend@basic-s3-without-i915.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-rkl-4/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_flip@basic-flip-vs-wf_vblank@a-hdmi-a4:
- shard-dg1: [FAIL][155] -> [PASS][156]
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-dg1-15/igt@kms_flip@basic-flip-vs-wf_vblank@a-hdmi-a4.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg1-18/igt@kms_flip@basic-flip-vs-wf_vblank@a-hdmi-a4.html
* igt@kms_flip@wf_vblank-ts-check@b-vga1:
- shard-snb: [INCOMPLETE][157] -> [PASS][158]
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-snb6/igt@kms_flip@wf_vblank-ts-check@b-vga1.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-snb4/igt@kms_flip@wf_vblank-ts-check@b-vga1.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-rkl: [SKIP][159] ([i915#9519]) -> [PASS][160] +1 other test pass
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-rkl-5/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-rkl-1/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-dg2: [SKIP][161] ([i915#9519]) -> [PASS][162]
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-dg2-2/igt@kms_pm_rpm@modeset-lpsp.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
- shard-tglu: [FAIL][163] ([i915#9196]) -> [PASS][164]
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-tglu-7/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-tglu-5/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
* igt@syncobj_timeline@signal-point-0:
- shard-dg1: [DMESG-WARN][165] ([i915#4423]) -> [PASS][166]
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-dg1-13/igt@syncobj_timeline@signal-point-0.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg1-16/igt@syncobj_timeline@signal-point-0.html
#### Warnings ####
* igt@gem_eio@kms:
- shard-dg1: [INCOMPLETE][167] ([i915#10513]) -> [INCOMPLETE][168] ([i915#10513] / [i915#1982])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-dg1-17/igt@gem_eio@kms.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg1-17/igt@gem_eio@kms.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0:
- shard-tglu: [FAIL][169] ([i915#3591]) -> [WARN][170] ([i915#2681])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-tglu-8/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-tglu-3/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render:
- shard-dg2: [SKIP][171] ([i915#3458]) -> [SKIP][172] ([i915#10433] / [i915#3458]) +2 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render.html
* igt@kms_pm_dc@dc9-dpms:
- shard-rkl: [SKIP][173] ([i915#4281]) -> [SKIP][174] ([i915#3361])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-rkl-5/igt@kms_pm_dc@dc9-dpms.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-rkl-4/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_psr@fbc-pr-primary-render:
- shard-dg2: [SKIP][175] ([i915#1072] / [i915#9732]) -> [SKIP][176] ([i915#1072] / [i915#9673] / [i915#9732]) +5 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-dg2-5/igt@kms_psr@fbc-pr-primary-render.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-11/igt@kms_psr@fbc-pr-primary-render.html
* igt@kms_psr@fbc-psr2-cursor-render:
- shard-dg2: [SKIP][177] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][178] ([i915#1072] / [i915#9732]) +14 other tests skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-dg2-11/igt@kms_psr@fbc-psr2-cursor-render.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-7/igt@kms_psr@fbc-psr2-cursor-render.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [FAIL][179] ([i915#7484]) -> [FAIL][180] ([i915#9100])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-dg2-8/igt@perf@non-zero-reason@0-rcs0.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@perf@non-zero-reason@0-rcs0.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: [INCOMPLETE][181] ([i915#5493]) -> [CRASH][182] ([i915#9351])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-dg2-5/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-11/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[i915#10031]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10031
[i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
[i915#10182]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10182
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10513]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10513
[i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
[i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#10887]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10887
[i915#10959]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10959
[i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
[i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2681
[i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4036]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4036
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
[i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
[i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
[i915#5176]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5235
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
[i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
[i915#5882]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5882
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6268]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6268
[i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#6645]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6645
[i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
[i915#7213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7213
[i915#7484]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7484
[i915#7711]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7711
[i915#7790]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7790
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
[i915#9100]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9100
[i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
[i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9351]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9351
[i915#9364]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9364
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9561]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9561
[i915#9606]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9606
[i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9808
[i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9849
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
Build changes
-------------
* Linux: CI_DRM_14756 -> Patchwork_133458v6
CI-20190529: 20190529
CI_DRM_14756: 3d00e04692d45ab076e9e493252361bb18373a0e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7849: c09431db6f7d5a2ddeb42e10a119d1cb7fa071d0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_133458v6: 3d00e04692d45ab076e9e493252361bb18373a0e @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/index.html
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