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d="scan'208";a="28258679" Received: from lfiedoro-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.230]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2024 06:57:50 -0700 From: Jani Nikula To: Ville Syrjala , intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: Re: [PATCH 1/9] drm/i915: Split gen2 vs. gen3 .max_stride() In-Reply-To: <20240506125718.26001-2-ville.syrjala@linux.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20240506125718.26001-1-ville.syrjala@linux.intel.com> <20240506125718.26001-2-ville.syrjala@linux.intel.com> Date: Mon, 06 May 2024 16:57:47 +0300 Message-ID: <877cg7m49w.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Mon, 06 May 2024, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > Plane .max_stride() is alreayd a vfunc so having one made *already > up of two branches based on the display version is silly. > Split i9xx_plane_max_stride() into gen2 vs. gen3 variants > so that we get rid of said check. -' ' > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/i9xx_plane.c | 32 +++++++++++++---------- > 1 file changed, 18 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/= i915/display/i9xx_plane.c > index 3442264443e5..21303fa4f08f 100644 > --- a/drivers/gpu/drm/i915/display/i9xx_plane.c > +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c > @@ -741,23 +741,25 @@ i965_plane_max_stride(struct intel_plane *plane, > } >=20=20 > static unsigned int > -i9xx_plane_max_stride(struct intel_plane *plane, > +i915_plane_max_stride(struct intel_plane *plane, > u32 pixel_format, u64 modifier, > unsigned int rotation) > { > - struct drm_i915_private *dev_priv =3D to_i915(plane->base.dev); > + if (modifier =3D=3D I915_FORMAT_MOD_X_TILED) > + return 8 * 1024; > + else > + return 16 * 1024; > +} >=20=20 > - if (DISPLAY_VER(dev_priv) >=3D 3) { > - if (modifier =3D=3D I915_FORMAT_MOD_X_TILED) > - return 8*1024; > - else > - return 16*1024; > - } else { > - if (plane->i9xx_plane =3D=3D PLANE_C) > - return 4*1024; > - else > - return 8*1024; > - } > +static unsigned int > +i8xx_plane_max_stride(struct intel_plane *plane, > + u32 pixel_format, u64 modifier, > + unsigned int rotation) > +{ > + if (plane->i9xx_plane =3D=3D PLANE_C) > + return 4 * 1024; > + else > + return 8 * 1024; > } >=20=20 > static const struct drm_plane_funcs i965_plane_funcs =3D { > @@ -854,8 +856,10 @@ intel_primary_plane_create(struct drm_i915_private *= dev_priv, enum pipe pipe) > if (HAS_GMCH(dev_priv)) { > if (DISPLAY_VER(dev_priv) >=3D 4) > plane->max_stride =3D i965_plane_max_stride; > + else if (DISPLAY_VER(dev_priv) =3D=3D 3) > + plane->max_stride =3D i915_plane_max_stride; > else > - plane->max_stride =3D i9xx_plane_max_stride; > + plane->max_stride =3D i8xx_plane_max_stride; > } else { > if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) > plane->max_stride =3D hsw_primary_max_stride; --=20 Jani Nikula, Intel