From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C421CEB64D9 for ; Thu, 6 Jul 2023 08:22:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 517FC10E46E; Thu, 6 Jul 2023 08:22:57 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4176710E46E for ; Thu, 6 Jul 2023 08:22:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1688631775; x=1720167775; h=from:to:subject:in-reply-to:references:date:message-id: mime-version:content-transfer-encoding; bh=uHWLJyt81NgzpqhRqJcS5X3f0a7jZVYEFBck41Cd+VM=; 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charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Intel-gfx] [PATCH 07/13] drm/i915/sdvo: Fail gracefully if the TV dotclock is out of range X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, 05 Jul 2023, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > Instead of warning and continuing with bogus state when the > requested dotclock isn't acceptable just print some debug > spew and fail gracefully. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_sdvo.c | 18 +++++++++++++----- > 1 file changed, 13 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/= i915/display/intel_sdvo.c > index 75a8e5583358..fcf3a95393d9 100644 > --- a/drivers/gpu/drm/i915/display/intel_sdvo.c > +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c > @@ -1269,7 +1269,7 @@ intel_sdvo_get_preferred_input_mode(struct intel_sd= vo *intel_sdvo, > return true; > } >=20=20 > -static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_conf= ig) > +static int i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_confi= g) > { > struct drm_i915_private *dev_priv =3D to_i915(pipe_config->uapi.crtc->d= ev); > unsigned int dotclock =3D pipe_config->hw.adjusted_mode.crtc_clock; > @@ -1292,11 +1292,14 @@ static void i9xx_adjust_sdvo_tv_clock(struct inte= l_crtc_state *pipe_config) > clock->m1 =3D 12; > clock->m2 =3D 8; > } else { > - drm_WARN(&dev_priv->drm, 1, > - "SDVO TV clock out of range: %i\n", dotclock); > + drm_dbg_kms(&dev_priv->drm, > + "SDVO TV clock out of range: %i\n", dotclock); > + return -EINVAL; > } >=20=20 > pipe_config->clock_set =3D true; > + > + return 0; > } >=20=20 > static bool intel_has_hdmi_sink(struct intel_sdvo_connector *intel_sdvo_= connector, > @@ -1414,8 +1417,13 @@ static int intel_sdvo_compute_config(struct intel_= encoder *encoder, > conn_state); >=20=20 > /* Clock computation needs to happen after pixel multiplier. */ > - if (IS_TV(intel_sdvo_connector)) > - i9xx_adjust_sdvo_tv_clock(pipe_config); > + if (IS_TV(intel_sdvo_connector)) { > + int ret; > + > + ret =3D i9xx_adjust_sdvo_tv_clock(pipe_config); > + if (ret) > + return ret; > + } >=20=20 > if (conn_state->picture_aspect_ratio) > adjusted_mode->picture_aspect_ratio =3D --=20 Jani Nikula, Intel Open Source Graphics Center