From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB93BC77B7F for ; Sat, 13 May 2023 03:01:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C983610E09F; Sat, 13 May 2023 03:01:37 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id AC14610E09F for ; Sat, 13 May 2023 03:01:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683946894; x=1715482894; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=KK2FiuXw+RO1kvZQVz43kjharKqPt0xaz4HhzLKTwOo=; b=lDKZq1C1pszLHWVFJE2pfnY2p/V1iskgpzdpqvoo0bqmsQKq0ApIKFLs 6sVRiBCuUcudm9zb1frtDC1g5krlz/4xIaibKn0FQvJCIJS+v2cqCEboN DtFLRHubIenddSI26NY1h8uGOOox7WCjiiiwDpPJVsxbt+suc8nhLtlGE xUxKQZ6YMiEvCtU4bwEnOnDGBJHXOE8vdF4l7bX5zXOZh8MzyXQbVM3Ao FaCoLxK+3qXq2YBisYqXcCRI72oLkyQEZ6KxM3QgihqCv9qvHBsDUFF5E Kjyhcczp4fNaWIrB4zL9hcK8ZieFJlVKLEIqcUtNGq5J2UaYD3esKLCp5 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10708"; a="379064273" X-IronPort-AV: E=Sophos;i="5.99,271,1677571200"; d="scan'208";a="379064273" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2023 20:01:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10708"; a="650835181" X-IronPort-AV: E=Sophos;i="5.99,271,1677571200"; d="scan'208";a="650835181" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.239.47]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2023 20:01:32 -0700 Date: Fri, 12 May 2023 20:01:23 -0700 Message-ID: <877ctddjek.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Umesh Nerlige Ramappa In-Reply-To: <20230513015545.2807282-5-umesh.nerlige.ramappa@intel.com> References: <20230513015545.2807282-1-umesh.nerlige.ramappa@intel.com> <20230513015545.2807282-5-umesh.nerlige.ramappa@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, 12 May 2023 18:55:43 -0700, Umesh Nerlige Ramappa wrote: > > From: Tvrtko Ursulin > > We do not want to have timers per tile and waste CPU cycles and energy via > multiple wake-up sources, for a relatively un-important task of PMU > sampling, so keeping a single timer works well. But we also do not want > the first GT which goes idle to turn off the timer. > > Add some reference counting, via a mask of unparked GTs, to solve this. > > v2: Drop the check for unparked in i915_sample (Ashutosh) Reviewed-by: Ashutosh Dixit > > Signed-off-by: Tvrtko Ursulin > Reviewed-by: Umesh Nerlige Ramappa > Signed-off-by: Umesh Nerlige Ramappa > --- > drivers/gpu/drm/i915/i915_pmu.c | 9 +++++++-- > drivers/gpu/drm/i915/i915_pmu.h | 4 ++++ > 2 files changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c > index 2b63ee31e1b3..725b01b00775 100644 > --- a/drivers/gpu/drm/i915/i915_pmu.c > +++ b/drivers/gpu/drm/i915/i915_pmu.c > @@ -251,7 +251,9 @@ void i915_pmu_gt_parked(struct intel_gt *gt) > * Signal sampling timer to stop if only engine events are enabled and > * GPU went idle. > */ > - pmu->timer_enabled = pmu_needs_timer(pmu, false); > + pmu->unparked &= ~BIT(gt->info.id); > + if (pmu->unparked == 0) > + pmu->timer_enabled = pmu_needs_timer(pmu, false); > > spin_unlock_irq(&pmu->lock); > } > @@ -268,7 +270,10 @@ void i915_pmu_gt_unparked(struct intel_gt *gt) > /* > * Re-enable sampling timer when GPU goes active. > */ > - __i915_pmu_maybe_start_timer(pmu); > + if (pmu->unparked == 0) > + __i915_pmu_maybe_start_timer(pmu); > + > + pmu->unparked |= BIT(gt->info.id); > > spin_unlock_irq(&pmu->lock); > } > diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h > index a686fd7ccedf..3a811266ac6a 100644 > --- a/drivers/gpu/drm/i915/i915_pmu.h > +++ b/drivers/gpu/drm/i915/i915_pmu.h > @@ -76,6 +76,10 @@ struct i915_pmu { > * @lock: Lock protecting enable mask and ref count handling. > */ > spinlock_t lock; > + /** > + * @unparked: GT unparked mask. > + */ > + unsigned int unparked; > /** > * @timer: Timer for internal i915 PMU sampling. > */ > -- > 2.36.1 >