From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 26D21C64EC4 for ; Fri, 10 Mar 2023 01:03:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4CA3A10E926; Fri, 10 Mar 2023 01:03:24 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4A0AC10E920; Fri, 10 Mar 2023 01:03:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678410201; x=1709946201; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=eKRK0CqN8Xm4gnFwOxCqFie9S6Y6Jcxm5ql4eqT9pCw=; b=GsZ8hy90BF3ib0AqvE3Q4cvNuTvl07IzG26oG22iKPQQCi+H3PdzbF+X iq1sT44pK+MgIMO/YiqZ98Zf9bt+1uEvrwhSm9qfp8Usb2VinLP0OqsKH YqZeVOAcF6Z91sWgU9HyXQP3+ZRWTTPtW+PuNpfTT9fQ9mN5H/OYTsZhZ LQFHzDo3mjuBAGo1otGAs62o9Rbp/psW7DzFtgZA76NPuhZb71NxRUy5K 2oBrxSocQiZjzVznA1CFdzUuP+t7+QlZ6dkAj4zc6Q7Ja8wxw+SHO5leF d5Gr7hRhWA+2/SVUwlphJEtRK4wI6WTnwBK7mcVe9Q2em30p5+Ev4odAK A==; X-IronPort-AV: E=McAfee;i="6500,9779,10644"; a="324965280" X-IronPort-AV: E=Sophos;i="5.98,248,1673942400"; d="scan'208";a="324965280" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Mar 2023 17:03:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10644"; a="677618153" X-IronPort-AV: E=Sophos;i="5.98,248,1673942400"; d="scan'208";a="677618153" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.215.176]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Mar 2023 17:03:12 -0800 Date: Thu, 09 Mar 2023 17:03:12 -0800 Message-ID: <877cvpmn8v.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Tvrtko Ursulin In-Reply-To: References: <20230309034621.1008458-1-ashutosh.dixit@intel.com> <20230309034621.1008458-2-ashutosh.dixit@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/pmu: Use functions common with sysfs to read actual freq X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Rodrigo Vivi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, 09 Mar 2023 01:20:09 -0800, Tvrtko Ursulin wrote: > Hi Tvrtko, > On 09/03/2023 03:46, Ashutosh Dixit wrote: > > Expose intel_rps_read_actual_frequency_fw to read the actual freq without > > taking forcewake for use by PMU. The code is refactored to use a common set > > of functions across sysfs and PMU. Using common functions with sysfs in PMU > > solves the issues of missing support for MTL and missing support for older > > generations (prior to Gen6). It also future proofs the PMU where sometimes > > code has been updated for sysfs and PMU has been missed. > > > > Fixes: 22009b6dad66 ("drm/i915/mtl: Modify CAGF functions for MTL") > > So not DG1 and above? The issue for DG1+ happens if non-freq bits are non-zero but freq bits are zero. But we've already seen that during PMU freq sampling gt is unparked so freq bits being 0 is rare. Therefore IMO there is 0 practical impact of that bug, I don't think it's worth fixing it and Cc'ing stable etc. (also those platforms are under force probe). > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8280 > > Signed-off-by: Ashutosh Dixit > > --- > > drivers/gpu/drm/i915/gt/intel_rps.c | 46 +++++++++++++++++++---------- > > drivers/gpu/drm/i915/gt/intel_rps.h | 2 +- > > drivers/gpu/drm/i915/i915_pmu.c | 10 +++---- > > 3 files changed, 36 insertions(+), 22 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > > index 4d0dc9de23f9..3957c5ee5cba 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > > @@ -2046,16 +2046,6 @@ void intel_rps_sanitize(struct intel_rps *rps) > > rps_disable_interrupts(rps); > > } > > -u32 intel_rps_read_rpstat_fw(struct intel_rps *rps) > > -{ > > - struct drm_i915_private *i915 = rps_to_i915(rps); > > - i915_reg_t rpstat; > > - > > - rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1; > > - > > - return intel_uncore_read_fw(rps_to_gt(rps)->uncore, rpstat); > > -} > > - > > u32 intel_rps_read_rpstat(struct intel_rps *rps) > > { > > struct drm_i915_private *i915 = rps_to_i915(rps); > > @@ -2089,10 +2079,11 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) > > return cagf; > > } > > -static u32 read_cagf(struct intel_rps *rps) > > +static u32 __read_cagf(struct intel_rps *rps, bool take_fw) > > { > > struct drm_i915_private *i915 = rps_to_i915(rps); > > struct intel_uncore *uncore = rps_to_uncore(rps); > > + i915_reg_t r = INVALID_MMIO_REG; > > u32 freq; > > /* > > @@ -2100,22 +2091,30 @@ static u32 read_cagf(struct intel_rps *rps) > > * registers will return 0 freq when GT is in RC6 > > */ > > if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) { > > - freq = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1); > > + r = MTL_MIRROR_TARGET_WP1; > > } else if (GRAPHICS_VER(i915) >= 12) { > > - freq = intel_uncore_read(uncore, GEN12_RPSTAT1); > > + r = GEN12_RPSTAT1; > > } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { > > vlv_punit_get(i915); > > freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); > > vlv_punit_put(i915); > > + goto exit; > > } else if (GRAPHICS_VER(i915) >= 6) { > > - freq = intel_uncore_read(uncore, GEN6_RPSTAT1); > > + r = GEN6_RPSTAT1; > > } else { > > - freq = intel_uncore_read(uncore, MEMSTAT_ILK); > > + r = MEMSTAT_ILK; > > } > > + freq = take_fw ? intel_uncore_read(uncore, r) : > > intel_uncore_read_fw(uncore, r); > > +exit: > > return intel_rps_get_cagf(rps, freq); > > } > > +static u32 read_cagf(struct intel_rps *rps) > > +{ > > + return __read_cagf(rps, true); > > +} > > + > > u32 intel_rps_read_actual_frequency(struct intel_rps *rps) > > { > > struct intel_runtime_pm *rpm = rps_to_uncore(rps)->rpm; > > @@ -2128,6 +2127,23 @@ u32 intel_rps_read_actual_frequency(struct intel_rps *rps) > > return freq; > > } > > +static u32 read_cagf_fw(struct intel_rps *rps) > > +{ > > + return __read_cagf(rps, false); > > +} > > + > > +u32 intel_rps_read_actual_frequency_fw(struct intel_rps *rps) > > +{ > > + struct intel_runtime_pm *rpm = rps_to_uncore(rps)->rpm; > > + intel_wakeref_t wakeref; > > + u32 freq = 0; > > + > > + with_intel_runtime_pm_if_in_use(rpm, wakeref) > > When called from i915_pmu.c::frequency sample() above seems redundant since > there we already are under intel_gt_pm_get_if_awake. Perhaps it is not a > huge deal but it is nevertheless wasteful. > > Also, maybe I am a bit rusty, but more fundamentally, wouldn't this be > adding a _very_ atypical pattern of a _fw function which grabs rpm? I'd > expect they all assume it's already held since the forcewake is already > held. > > Am I missing the reason why it is needed? Thanks for catching this, you are right, it was just mindless copy paste, I've dropped it in the next version. Thanks. -- Ashutosh