From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D47BDECAAD8 for ; Fri, 23 Sep 2022 04:23:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B146310E30C; Fri, 23 Sep 2022 04:23:41 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5FCF410E30C; Fri, 23 Sep 2022 04:23:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663907019; x=1695443019; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=XeWyplBfU7ooubbg+lB1SZLGAb8Q4lLNFEaq3LMcn84=; b=mvyheus9c6YIkzbSVQvOhkMSpKiYxA6pbok7fgnK2KAypwipIsDoT+XA TP/Hfb9Xq+ldravmanoclOMshVr+153/GOwuje1OVWx0MoKT+VLoS2jDJ 0153MYMc3vrAOgVevRUPsE9X/UEFJvfK3YTupYWyPGMLbn0u4x/Bcg07A bUCJ9wpvK3P95lRIaAI0LErety2u3nBjqqa+eJIEeImGwkiGg25aa5u1b g39nPgLtSNiqGJ2QAkrKgDBmCREcHADlfxm3iK/3hDRnK5lmXmBLxglc8 TUuxZ3wY0tPn43/R8CjvOJ1pelZITshx+qetHLHcXH47HHIX+Ph2IBKS4 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10478"; a="362312672" X-IronPort-AV: E=Sophos;i="5.93,337,1654585200"; d="scan'208";a="362312672" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2022 21:23:38 -0700 X-IronPort-AV: E=Sophos;i="5.93,337,1654585200"; d="scan'208";a="615484247" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.209.57.84]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2022 21:23:38 -0700 Date: Thu, 22 Sep 2022 21:23:38 -0700 Message-ID: <877d1un2gl.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: "Gupta, Anshuman" In-Reply-To: <878rman6pq.wl-ashutosh.dixit@intel.com> References: <20220916150054.807590-1-badal.nilawar@intel.com> <20220916150054.807590-7-badal.nilawar@intel.com> <878rman6pq.wl-ashutosh.dixit@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 6/7] drm/i915/hwmon: Expose power1_max_interval X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-hwmon@vger.kernel.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, 22 Sep 2022 19:51:45 -0700, Dixit, Ashutosh wrote: > > On Thu, 22 Sep 2022 00:13:00 -0700, Gupta, Anshuman wrote: > > > > Hi Anshuman, > > > > +static ssize_t > > > +hwm_power1_max_interval_store(struct device *dev, > > > + struct device_attribute *attr, > > > + const char *buf, size_t count) > > > +{ > > > + struct hwm_drvdata *ddat = dev_get_drvdata(dev); > > > + struct i915_hwmon *hwmon = ddat->hwmon; > > > + long val, max_win, ret; > > > + u32 x, y, rxy, x_w = 2; /* 2 bits */ > > > + u64 tau4, r; > > > + > > > +#define PKG_MAX_WIN_DEFAULT 0x12ull > > > + > > > + ret = kstrtoul(buf, 0, &val); > > > + if (ret) > > > + return ret; > > > + > > > + /* > > > + * val must be < max in hwmon interface units. The steps below are > > > + * explained in i915_power1_max_interval_show() > > > + */ > > > + r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT); > > > > AFAIU we need to read r from PACKAGE_POWER_SKU reg untill unless it has > > some known issue? > > The platform on which I tried had an incorrect value (that is why I didn't > read it from PACKAGE_POWER_SKU) but let me investigate it some more for > other platforms and get back. I checked, the value is correct on DG1/DG2 which have a valid PACKAGE_POWER_SKU (XEHPSDV does not have a valid PACKAGE_POWER_SKU). Therefore the one line above should be replaced with the code below: if (i915_mmio_reg_valid(hwmon->rg.pkg_power_sku)) with_intel_runtime_pm(ddat->uncore->rpm, wakeref) r = intel_uncore_read64(ddat->uncore, hwmon->rg.pkg_power_sku); else r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT); > > > + x = REG_FIELD_GET(PKG_MAX_WIN_X, r); > > > + y = REG_FIELD_GET(PKG_MAX_WIN_Y, r); > > > + tau4 = ((1 << x_w) | x) << y; > > > + max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w); > > > + > > > + if (val > max_win) > > > + return -EINVAL; > > > + > > > + /* val in hw units */ > > > + val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME); > > > + /* Convert to 1.x * power(2,y) */ > > > + if (!val) > > > + return -EINVAL; > > > + y = ilog2(val); > > > + /* x = (val - (1 << y)) >> (y - 2); */ > > > + x = (val - (1ul << y)) << x_w >> y; > > > + > > > + rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y); > > > + > > > + hwm_locked_with_pm_intel_uncore_rmw(ddat, hwmon->rg.pkg_rapl_limit, > > > + PKG_PWR_LIM_1_TIME, rxy); > > > + return count; > > > +} > > > + > > /snip > > > if (IS_ERR(hwmon_dev)) { > > > mutex_destroy(&hwmon->hwmon_lock); > > > i915->hwmon = NULL; > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > > index 956e5298ef1e..68e7cc85dc53 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -1811,6 +1811,9 @@ > > > * *_PACKAGE_POWER_SKU - SKU power and timing parameters. > > > */ > > > #define PKG_PKG_TDP GENMASK_ULL(14, 0) > > > +#define PKG_MAX_WIN GENMASK_ULL(54, 48) > > > +#define PKG_MAX_WIN_X GENMASK_ULL(54, 53) > > > +#define PKG_MAX_WIN_Y GENMASK_ULL(52, 48) > > These GENMASK fields needs a reg definition. > > Yes this is the same _PACKAGE_POWER_SKU register so should get fixed when > we add it in Patch 3. Looks like PCU_PACKAGE_POWER_SKU for DG1/DG2 will need to be declared in intel_mchbar_regs.h so these fields will need to also move there (in Patch 3). Thanks. -- Ashutosh