From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA193C10DCE for ; Fri, 6 Mar 2020 14:07:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B28B9206CC for ; Fri, 6 Mar 2020 14:07:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B28B9206CC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D1EF6ED28; Fri, 6 Mar 2020 14:07:46 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id CDA286ED28 for ; Fri, 6 Mar 2020 14:07:44 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Mar 2020 06:07:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,522,1574150400"; d="scan'208";a="244622655" Received: from gaia.fi.intel.com ([10.237.72.192]) by orsmga006.jf.intel.com with ESMTP; 06 Mar 2020 06:07:42 -0800 Received: by gaia.fi.intel.com (Postfix, from userid 1000) id 8D12A5C1DD1; Fri, 6 Mar 2020 16:06:24 +0200 (EET) From: Mika Kuoppala To: Chris Wilson , intel-gfx@lists.freedesktop.org In-Reply-To: <20200306113012.3184606-1-chris@chris-wilson.co.uk> References: <20200306113012.3184606-1-chris@chris-wilson.co.uk> Date: Fri, 06 Mar 2020 16:06:24 +0200 Message-ID: <877dzx4ly7.fsf@gaia.fi.intel.com> MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915/execlists: Enable timeslice on partial virtual engine dequeue X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stable@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Chris Wilson writes: > If we stop filling the ELSP due to an incompatible virtual engine > request, check if we should enable the timeslice on behalf of the queue. > > This fixes the case where we are inspecting the last->next element when > we know that the last element is the last request in the execution queue, > and so decided we did not need to enable timeslicing despite the intent > to do so! > > Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing") > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala > Cc: Tvrtko Ursulin > Cc: # v5.4+ Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 29 ++++++++++++++++++----------- > 1 file changed, 18 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index 13941d1c0a4a..a1d268880cfe 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -1757,11 +1757,9 @@ need_timeslice(struct intel_engine_cs *engine, const struct i915_request *rq) > if (!intel_engine_has_timeslices(engine)) > return false; > > - if (list_is_last(&rq->sched.link, &engine->active.requests)) > - return false; > - > - hint = max(rq_prio(list_next_entry(rq, sched.link)), > - engine->execlists.queue_priority_hint); > + hint = engine->execlists.queue_priority_hint; > + if (!list_is_last(&rq->sched.link, &engine->active.requests)) > + hint = max(hint, rq_prio(list_next_entry(rq, sched.link))); > > return hint >= effective_prio(rq); > } > @@ -1803,6 +1801,18 @@ static void set_timeslice(struct intel_engine_cs *engine) > set_timer_ms(&engine->execlists.timer, active_timeslice(engine)); > } > > +static void start_timeslice(struct intel_engine_cs *engine) > +{ > + struct intel_engine_execlists *execlists = &engine->execlists; > + > + execlists->switch_priority_hint = execlists->queue_priority_hint; > + > + if (timer_pending(&execlists->timer)) > + return; > + > + set_timer_ms(&execlists->timer, timeslice(engine)); > +} > + > static void record_preemption(struct intel_engine_execlists *execlists) > { > (void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++); > @@ -1966,11 +1976,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) > * Even if ELSP[1] is occupied and not worthy > * of timeslices, our queue might be. > */ > - if (!execlists->timer.expires && > - need_timeslice(engine, last)) > - set_timer_ms(&execlists->timer, > - timeslice(engine)); > - > + start_timeslice(engine); > return; > } > } > @@ -2005,7 +2011,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) > > if (last && !can_merge_rq(last, rq)) { > spin_unlock(&ve->base.active.lock); > - return; /* leave this for another */ > + start_timeslice(engine); > + return; /* leave this for another sibling */ > } > > ENGINE_TRACE(engine, > -- > 2.25.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx