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From: Jani Nikula <jani.nikula@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jose Roberto de Souza <jose.souza@intel.com>,
	dri-devel@lists.freedesktop.org,
	Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>,
	stable@vger.kernel.org, Sean Paul <seanpaul@chromium.org>
Subject: Re: [PATCH 3/6] drm/psr: Fix missed entry in PSR setup time table.
Date: Thu, 24 May 2018 17:00:52 +0300	[thread overview]
Message-ID: <877entjgq3.fsf@intel.com> (raw)
In-Reply-To: <20180511195145.3829-3-dhinakaran.pandiyan@intel.com>

On Fri, 11 May 2018, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:
> Entry corresponding to 220 us setup time was missing. I am not aware of
> any specific bug this fixes, but this could potentially result in enabling
> PSR on a panel with a higher setup time requirement than supported by the
> hardware.
>
> I verified the value is present in eDP spec versions 1.3, 1.4 and 1.4a.
>
> Fixes: 6608804b3d7f ("drm/dp: Add drm_dp_psr_setup_time()")
> Cc: stable@vger.kernel.org
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Jose Roberto de Souza <jose.souza@intel.com>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Pushed to drm-misc-fixes with reviews picked up from the earlier posting
[1]. Doesn't look like the function is used by anyone other than i915,
so I didn't bother with further acks from non-Intel devs. Should be a
straightforward fix anyway.

BR,
Jani.


[1] http://mid.mail-archive.com/20180511005419.11199-1-dhinakaran.pandiyan@intel.com

> ---
>  drivers/gpu/drm/drm_dp_helper.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 36c7609a4bd5..a7ba602a43a8 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1159,6 +1159,7 @@ int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
>  	static const u16 psr_setup_time_us[] = {
>  		PSR_SETUP_TIME(330),
>  		PSR_SETUP_TIME(275),
> +		PSR_SETUP_TIME(220),
>  		PSR_SETUP_TIME(165),
>  		PSR_SETUP_TIME(110),
>  		PSR_SETUP_TIME(55),

-- 
Jani Nikula, Intel Open Source Graphics Center

  reply	other threads:[~2018-05-24 14:00 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-11 19:51 [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR Dhinakaran Pandiyan
2018-05-11 19:51 ` [PATCH 2/6] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time Dhinakaran Pandiyan
2018-05-11 22:14   ` Dhinakaran Pandiyan
2018-05-24 13:28     ` Jani Nikula
2018-05-11 19:51 ` [PATCH 3/6] drm/psr: Fix missed entry in PSR setup time table Dhinakaran Pandiyan
2018-05-24 14:00   ` Jani Nikula [this message]
2018-05-11 19:51 ` [PATCH 4/6] drm/i915/psr: Avoid unnecessary DPCD read of DP_PSR_CAPS Dhinakaran Pandiyan
2018-05-20 23:01   ` Tarun Vyas
2018-05-24 14:01     ` Jani Nikula
2018-05-22 12:32   ` Nagaraju, Vathsala
2018-05-11 19:51 ` [PATCH 5/6] drm/i915/psr: Fall back to max. synchronization latency if DPCD read fails Dhinakaran Pandiyan
2018-05-21 23:58   ` Souza, Jose
2018-05-11 19:51 ` [PATCH 6/6] drm/i915/psr: Fix ALPM cap check for PSR2 Dhinakaran Pandiyan
2018-05-22  9:33   ` Nagaraju, Vathsala
2018-05-22 14:37   ` Tarun Vyas
2018-05-22 20:21     ` Dhinakaran Pandiyan
2018-05-11 20:26 ` ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR Patchwork
2018-05-11 21:17 ` ✓ Fi.CI.IGT: " Patchwork
2018-05-18  0:27 ` [PATCH 1/6] " Tarun Vyas
2018-05-21 23:40   ` Dhinakaran Pandiyan
2018-05-24 13:29   ` Jani Nikula
2018-05-22 12:29 ` Nagaraju, Vathsala

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