From mboxrd@z Thu Jan 1 00:00:00 1970 From: Francisco Jerez Subject: Re: [PATCH 2/5] drm/i915: Use an array of register tables in command parser Date: Wed, 16 Mar 2016 16:33:38 -0700 Message-ID: <877fh22e25.fsf@riseup.net> References: <1457335830-30923-1-git-send-email-jordan.l.justen@intel.com> <1457335830-30923-3-git-send-email-jordan.l.justen@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1384604818==" Return-path: Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) by gabe.freedesktop.org (Postfix) with ESMTPS id 09ECC6EA33 for ; Wed, 16 Mar 2016 23:34:16 +0000 (UTC) In-Reply-To: <1457335830-30923-3-git-send-email-jordan.l.justen@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Jordan Justen , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============1384604818== Content-Type: multipart/signed; boundary="==-=-="; micalg=pgp-sha256; protocol="application/pgp-signature" --==-=-= Content-Type: multipart/mixed; boundary="=-=-=" --=-=-= Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Jordan Justen writes: > For Haswell, we will want another table of registers while retaining > the large common table of whitelisted registers shared by all gen7 > devices. > > Signed-off-by: Jordan Justen Reviewed-by: Francisco Jerez > --- > drivers/gpu/drm/i915/i915_cmd_parser.c | 101 +++++++++++++++++++++++---= ------ > drivers/gpu/drm/i915/intel_ringbuffer.h | 13 +--- > 2 files changed, 75 insertions(+), 39 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i91= 5/i915_cmd_parser.c > index 86d7cda..46ea40b 100644 > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c > @@ -501,6 +501,32 @@ static const struct drm_i915_reg_descriptor hsw_mast= er_regs[] =3D { > #undef REG64 > #undef REG32 >=20=20 > +struct drm_i915_reg_table { > + const struct drm_i915_reg_descriptor *regs; > + int num_regs; > + bool master; > +}; > + > +static const struct drm_i915_reg_table ivb_render_reg_tables[] =3D { > + { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false }, > + { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true }, > +}; > + > +static const struct drm_i915_reg_table ivb_blt_reg_tables[] =3D { > + { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false }, > + { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true }, > +}; > + > +static const struct drm_i915_reg_table hsw_render_reg_tables[] =3D { > + { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false }, > + { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true }, > +}; > + > +static const struct drm_i915_reg_table hsw_blt_reg_tables[] =3D { > + { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false }, > + { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true }, > +}; > + > static u32 gen7_render_get_cmd_length_mask(u32 cmd_header) > { > u32 client =3D (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; > @@ -614,9 +640,16 @@ static bool check_sorted(int ring_id, >=20=20 > static bool validate_regs_sorted(struct intel_engine_cs *ring) > { > - return check_sorted(ring->id, ring->reg_table, ring->reg_count) && > - check_sorted(ring->id, ring->master_reg_table, > - ring->master_reg_count); > + int i; > + const struct drm_i915_reg_table *table; > + > + for (i =3D 0; i < ring->reg_table_count; i++) { > + table =3D &ring->reg_tables[i]; > + if (!check_sorted(ring->id, table->regs, table->num_regs)) > + return false; > + } > + > + return true; > } >=20=20 > struct cmd_node { > @@ -711,15 +744,12 @@ int i915_cmd_parser_init_ring(struct intel_engine_c= s *ring) > cmd_table_count =3D ARRAY_SIZE(gen7_render_cmds); > } >=20=20 > - ring->reg_table =3D gen7_render_regs; > - ring->reg_count =3D ARRAY_SIZE(gen7_render_regs); > - > if (IS_HASWELL(ring->dev)) { > - ring->master_reg_table =3D hsw_master_regs; > - ring->master_reg_count =3D ARRAY_SIZE(hsw_master_regs); > + ring->reg_tables =3D hsw_render_reg_tables; > + ring->reg_table_count =3D ARRAY_SIZE(hsw_render_reg_tables); > } else { > - ring->master_reg_table =3D ivb_master_regs; > - ring->master_reg_count =3D ARRAY_SIZE(ivb_master_regs); > + ring->reg_tables =3D ivb_render_reg_tables; > + ring->reg_table_count =3D ARRAY_SIZE(ivb_render_reg_tables); > } >=20=20 > ring->get_cmd_length_mask =3D gen7_render_get_cmd_length_mask; > @@ -738,15 +768,12 @@ int i915_cmd_parser_init_ring(struct intel_engine_c= s *ring) > cmd_table_count =3D ARRAY_SIZE(gen7_blt_cmds); > } >=20=20 > - ring->reg_table =3D gen7_blt_regs; > - ring->reg_count =3D ARRAY_SIZE(gen7_blt_regs); > - > if (IS_HASWELL(ring->dev)) { > - ring->master_reg_table =3D hsw_master_regs; > - ring->master_reg_count =3D ARRAY_SIZE(hsw_master_regs); > + ring->reg_tables =3D hsw_blt_reg_tables; > + ring->reg_table_count =3D ARRAY_SIZE(hsw_blt_reg_tables); > } else { > - ring->master_reg_table =3D ivb_master_regs; > - ring->master_reg_count =3D ARRAY_SIZE(ivb_master_regs); > + ring->reg_tables =3D ivb_blt_reg_tables; > + ring->reg_table_count =3D ARRAY_SIZE(ivb_blt_reg_tables); > } >=20=20 > ring->get_cmd_length_mask =3D gen7_blt_get_cmd_length_mask; > @@ -849,12 +876,31 @@ static const struct drm_i915_reg_descriptor * > find_reg(const struct drm_i915_reg_descriptor *table, > int count, u32 addr) > { > - if (table) { > - int i; > + int i; > + > + for (i =3D 0; i < count; i++) { > + if (i915_mmio_reg_offset(table[i].addr) =3D=3D addr) > + return &table[i]; > + } >=20=20 > - for (i =3D 0; i < count; i++) { > - if (i915_mmio_reg_offset(table[i].addr) =3D=3D addr) > - return &table[i]; > + return NULL; > +} > + > +static const struct drm_i915_reg_descriptor * > +find_reg_in_tables(const struct drm_i915_reg_table *tables, > + int count, bool is_master, u32 addr) > +{ > + int i; > + const struct drm_i915_reg_table *table; > + const struct drm_i915_reg_descriptor *reg; > + > + for (i =3D 0; i < count; i++) { > + table =3D &tables[i]; > + if (!table->master || is_master) { > + reg =3D find_reg(table->regs, table->num_regs, > + addr); > + if (reg !=3D NULL) > + return reg; > } > } >=20=20 > @@ -1005,13 +1051,10 @@ static bool check_cmd(const struct intel_engine_c= s *ring, > offset +=3D step) { > const u32 reg_addr =3D cmd[offset] & desc->reg.mask; > const struct drm_i915_reg_descriptor *reg =3D > - find_reg(ring->reg_table, ring->reg_count, > - reg_addr); > - > - if (!reg && is_master) > - reg =3D find_reg(ring->master_reg_table, > - ring->master_reg_count, > - reg_addr); > + find_reg_in_tables(ring->reg_tables, > + ring->reg_table_count, > + is_master, > + reg_addr); >=20=20 > if (!reg) { > DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (= ring=3D%d)\n", > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i9= 15/intel_ringbuffer.h > index 566b0ae..5f89261 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h > @@ -125,7 +125,7 @@ struct intel_ringbuffer { > }; >=20=20 > struct intel_context; > -struct drm_i915_reg_descriptor; > +struct drm_i915_reg_table; >=20=20 > /* > * we use a single page to load ctx workarounds so all of these > @@ -332,15 +332,8 @@ struct intel_engine_cs { > /* > * Table of registers allowed in commands that read/write registers. > */ > - const struct drm_i915_reg_descriptor *reg_table; > - int reg_count; > - > - /* > - * Table of registers allowed in commands that read/write registers, but > - * only from the DRM master. > - */ > - const struct drm_i915_reg_descriptor *master_reg_table; > - int master_reg_count; > + const struct drm_i915_reg_table *reg_tables; > + int reg_table_count; >=20=20 > /* > * Returns the bitmask for the length field of the specified command. > --=20 > 2.7.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx --=-=-=-- --==-=-= Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iF4EAREIAAYFAlbp7VIACgkQg5k4nX1Sv1vlzQD/UsLobNON0+JMfwW/6H3mWuW9 vyvrooGu3NwzsCSGrXgA/RNe96yVpfUfo8P/pRw+B+3NLXu0/p0R1FZfQaSEI5cu =ihDH -----END PGP SIGNATURE----- --==-=-=-- --===============1384604818== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== --===============1384604818==--