From: Jani Nikula <jani.nikula@linux.intel.com>
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/5] drm/i915: Fix GMBUSFREQ on vlv/chv
Date: Fri, 17 Oct 2014 11:59:36 +0300 [thread overview]
Message-ID: <877fzzm5qf.fsf@intel.com> (raw)
In-Reply-To: <1413481954-18622-3-git-send-email-ville.syrjala@linux.intel.com>
On Thu, 16 Oct 2014, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> vlv_cdclk_freq is in kHz but we need MHz for the GMBUSFREQ divider.
>
> This is a regression from:
> commit f8bf63fdcb1f82459dae7a3f22ee5ce92f3ea727
> Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Date: Fri Jun 13 13:37:54 2014 +0300
>
> drm/i915: Kill duplicated cdclk readout code from i2c
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6e6f150..18b493f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4628,7 +4628,7 @@ static void vlv_update_cdclk(struct drm_device *dev)
> * BSpec erroneously claims we should aim for 4MHz, but
> * in fact 1MHz is the correct frequency.
> */
> - I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
> + I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
> }
>
> /* Adjust CDclk dividers to allow high res or save power if possible */
> --
> 2.0.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
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next prev parent reply other threads:[~2014-10-17 9:00 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-16 17:52 [PATCH 0/5] drm/i915: Random pile of VLV/CHV fixes ville.syrjala
2014-10-16 17:52 ` [PATCH 1/5] drm/i915: Don't claim that we're resetting PCH ADPA register ville.syrjala
2014-10-17 8:50 ` Jani Nikula
2014-10-16 17:52 ` [PATCH 2/5] drm/i915: Fix GMBUSFREQ on vlv/chv ville.syrjala
2014-10-17 8:59 ` Jani Nikula [this message]
2014-10-17 9:00 ` Jani Nikula
2014-10-22 13:41 ` Jani Nikula
2014-10-16 17:52 ` [PATCH 3/5] drm/i915: Fix chv PCS DW11 register defines ville.syrjala
2014-10-17 9:08 ` Jani Nikula
2014-10-21 16:08 ` Daniel Vetter
2014-10-16 17:52 ` [PATCH 4/5] drm/i915: Do vlv cmnlane toggle w/a in more cases ville.syrjala
2014-10-28 17:57 ` Jesse Barnes
2014-10-28 18:12 ` Ville Syrjälä
2014-11-03 11:10 ` Daniel Vetter
2014-10-16 17:52 ` [PATCH 5/5] drm/i915: Initialize new chv primary plane and pipe blender registers ville.syrjala
2014-10-29 21:18 ` Rodrigo Vivi
2014-10-30 8:33 ` Ville Syrjälä
2014-10-30 19:14 ` Rodrigo Vivi
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