From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH 6/9] drm/i915: Dsipll clk to be enabled for DSI1 in case of dual link configuration Date: Wed, 24 Sep 2014 12:34:59 +0300 Message-ID: <877g0tmke4.fsf@intel.com> References: <1411548418-26525-1-git-send-email-gaurav.k.singh@intel.com> <1411548418-26525-7-git-send-email-gaurav.k.singh@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 448A86E012 for ; Wed, 24 Sep 2014 02:35:19 -0700 (PDT) In-Reply-To: <1411548418-26525-7-git-send-email-gaurav.k.singh@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Gaurav K Singh , intel-gfx Cc: Shobhit Kumar List-Id: intel-gfx@lists.freedesktop.org On Wed, 24 Sep 2014, Gaurav K Singh wrote: > Signed-off-by: Gaurav K Singh > Signed-off-by: Shobhit Kumar > --- > drivers/gpu/drm/i915/intel_dsi_pll.c | 14 ++++++++------ > 1 file changed, 8 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c > index fa7a6ca..2464089 100644 > --- a/drivers/gpu/drm/i915/intel_dsi_pll.c > +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c > @@ -243,6 +243,9 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder) > > dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; > > + if (intel_dsi->dual_link) > + dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL; > + > DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n", > dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl); > > @@ -271,12 +274,11 @@ void vlv_enable_dsi_pll(struct intel_encoder *encoder) > > mutex_unlock(&dev_priv->dpio_lock); > > - if (wait_for(I915_READ(PIPECONF(PIPE_A)) & PIPECONF_DSI_PLL_LOCKED, 20)) { > - DRM_ERROR("DSI PLL lock failed\n"); > - return; > - } > - > - DRM_DEBUG_KMS("DSI PLL locked\n"); > + tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); Is there no need to wait for some timeout for the pll to lock? > + if (tmp & DSI_PLL_LOCK) > + DRM_DEBUG_KMS("DSI PLL locked\n"); > + else > + DRM_DEBUG_KMS("DSI PLL lock failed\n"); Please keep the happy day scenario without indent, and bail out on the fail paths. > } > > void vlv_disable_dsi_pll(struct intel_encoder *encoder) > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center