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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: deepak.s@linux.intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2] drm/i915: Add RP1 render P state thresholds	in CHV
Date: Fri, 11 Jul 2014 19:07:33 +0300	[thread overview]
Message-ID: <877g3jkhfe.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <1405170974-14003-1-git-send-email-deepak.s@linux.intel.com>

deepak.s@linux.intel.com writes:

> From: Deepak S <deepak.s@linux.intel.com>
>
> This is useful for userspace utilities to verify and micromanaging
> the increase/decrease frequncy.
>
> v2: Use vlv_gpu_freq to get freq (Deepak)
>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3fb65e9..225b6cb 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3809,6 +3809,16 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
>  	return rpe;
>  }
>  
> +int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
^^static
Daniel said he will add it, missing in other patches too.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> +{
> +	u32 val, rp1;
> +
> +	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> +	rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
> +
> +	return rp1;
> +}
> +
>  int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
>  {
>  	u32 val, rpn;
> @@ -4010,6 +4020,11 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
>  			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
>  			 dev_priv->rps.efficient_freq);
>  
> +	dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
> +	DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
> +			 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
> +			 dev_priv->rps.rp1_freq);
> +
>  	dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
>  	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
>  			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
> -- 
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2014-07-11 16:08 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-07-10  7:46 [PATCH 0/7] Enable RP1/RPn/RP0 sysfs and enable CHV PM interrupt deepak.s
2014-07-10  7:46 ` [PATCH 1/7] drm/i915: Read guaranteed freq for valleyview deepak.s
2014-07-11 14:42   ` Mika Kuoppala
2014-07-11 15:56     ` Daniel Vetter
2014-07-10  7:46 ` [PATCH 2/7] drm/i915: Add RP0/RP1/RPn render P state thresholds in VLV sysfs deepak.s
2014-07-11 14:44   ` Mika Kuoppala
2014-07-11 16:00   ` Daniel Vetter
2014-07-10  7:46 ` [PATCH 3/7] drm/i915: keep freq/opcode conversion function more generic deepak.s
2014-07-09 12:03   ` Daniel Vetter
2014-07-11  4:26     ` Deepak S
2014-07-10  6:28       ` Daniel Vetter
2014-07-11  6:50         ` Deepak S
2014-07-10  7:46 ` [PATCH 4/7] drm/i915: populate mem_freq/cz_clock for chv deepak.s
2014-07-11 14:50   ` Mika Kuoppala
2014-07-10  7:46 ` [PATCH 5/7] drm/i915: CHV GPU frequency to opcode functions deepak.s
2014-07-10  7:46 ` [PATCH 6/7] drm/i915/chv: Add basic PM interrupt support for CHV deepak.s
2014-07-11 15:03   ` Mika Kuoppala
2014-07-10  7:46 ` [PATCH 7/7] drm/i915: Add RP1 render P state thresholds in CHV deepak.s
2014-07-12  9:24 ` [PATCH v2 1/3] drm/i915: CHV GPU frequency to opcode functions deepak.s
2014-07-11 15:53   ` Mika Kuoppala
2014-07-11 15:58   ` Daniel Vetter
2014-07-12 13:16 ` [PATCH v2] drm/i915: Add RP1 render P state thresholds in CHV deepak.s
2014-07-11 16:07   ` Mika Kuoppala [this message]
2014-07-11 16:22     ` Daniel Vetter

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