From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH 49/62] drm/i915/bdw: Use The GT mailbox for IPS enable/disable Date: Mon, 04 Nov 2013 12:15:18 +0200 Message-ID: <877gcocw21.fsf@intel.com> References: <1383451680-11173-1-git-send-email-benjamin.widawsky@intel.com> <1383451680-11173-50-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 4A730131358 for ; Mon, 4 Nov 2013 02:13:27 -0800 (PST) In-Reply-To: <1383451680-11173-50-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Intel GFX Cc: Ben Widawsky , Art Runyan , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Sun, 03 Nov 2013, Ben Widawsky wrote: > v2: Squash in fixup from Ben to synchronize the GT mailbox commands. > > CC: Art Runyan > Reviewed-by: Art Runyan > Signed-off-by: Ben Widawsky The WARN_ON()s may be a bit loud, but Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_drv.h | 2 +- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++---------- > 3 files changed, 28 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 1a2e967..f222eb4 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1803,7 +1803,7 @@ struct drm_i915_file_private { > #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) > #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) > > -#define HAS_IPS(dev) (IS_ULT(dev)) > +#define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev)) > > #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) > #define HAS_POWER_WELL(dev) (IS_HASWELL(dev) || IS_GEN8(dev)) > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 2a65f92..65f9631 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4932,6 +4932,7 @@ > #define GEN6_PCODE_WRITE_D_COMP 0x11 > #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) > #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) > +#define DISPLAY_IPS_CONTROL 0x19 > #define GEN6_PCODE_DATA 0x138128 > #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 > #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index fce3b0d..fc4b4cf 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -3347,15 +3347,26 @@ void hsw_enable_ips(struct intel_crtc *crtc) > * only after intel_enable_plane. And intel_enable_plane already waits > * for a vblank, so all we need to do here is to enable the IPS bit. */ > assert_plane_enabled(dev_priv, crtc->plane); > - I915_WRITE(IPS_CTL, IPS_ENABLE); > - > - /* The bit only becomes 1 in the next vblank, so this wait here is > - * essentially intel_wait_for_vblank. If we don't have this and don't > - * wait for vblanks until the end of crtc_enable, then the HW state > - * readout code will complain that the expected IPS_CTL value is not the > - * one we read. */ > - if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) > - DRM_ERROR("Timed out waiting for IPS enable\n"); > + if (IS_BROADWELL(crtc->base.dev)) { > + mutex_lock(&dev_priv->rps.hw_lock); > + WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); > + mutex_unlock(&dev_priv->rps.hw_lock); > + /* Quoting Art Runyan: "its not safe to expect any particular > + * value in IPS_CTL bit 31 after enabling IPS through the > + * mailbox." Therefore we need to defer waiting on the state > + * change. > + * TODO: need to fix this for state checker > + */ > + } else { > + I915_WRITE(IPS_CTL, IPS_ENABLE); > + /* The bit only becomes 1 in the next vblank, so this wait here > + * is essentially intel_wait_for_vblank. If we don't have this > + * and don't wait for vblanks until the end of crtc_enable, then > + * the HW state readout code will complain that the expected > + * IPS_CTL value is not the one we read. */ > + if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) > + DRM_ERROR("Timed out waiting for IPS enable\n"); > + } > } > > void hsw_disable_ips(struct intel_crtc *crtc) > @@ -3367,7 +3378,12 @@ void hsw_disable_ips(struct intel_crtc *crtc) > return; > > assert_plane_enabled(dev_priv, crtc->plane); > - I915_WRITE(IPS_CTL, 0); > + if (IS_BROADWELL(crtc->base.dev)) { > + mutex_lock(&dev_priv->rps.hw_lock); > + WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); > + mutex_unlock(&dev_priv->rps.hw_lock); > + } else > + I915_WRITE(IPS_CTL, 0); > POSTING_READ(IPS_CTL); > > /* We need to wait for a vblank before we can disable the plane. */ > -- > 1.8.4.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center