From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 50CAAC433FE for ; Thu, 13 Oct 2022 15:55:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0CE8410E8CE; Thu, 13 Oct 2022 15:55:41 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id E864E10E29D; Thu, 13 Oct 2022 15:55:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665676534; x=1697212534; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=MMB9JPbiAfVjJFDQG4ccZnlNVA56v/sPsEvIMvdUtlc=; b=K6QjRoACAwdHvFkidVuUUB0InBv+xlW606/De1hV4q2pts/8Qex2PV9n Wlm+BQAddNFEca4gqafONSyWWJKgrGr1QrM800kWt+nYuqJ2mrHGsiHIh 6dI2Q/xJfcj/DBEfQh3uEYqVDQxbmWf24xj5EIx4VayiiH4De3Z5AG0dQ 3KpNJlJ3Pu2N7lNHUfzLHtrfE8QGtiYMyt7jkNY7f/UTx/2k2hjZ/veX3 LC9veWCxNcX/hc2pg4wEbhkk5YbZUkRQkfUhYBGvRnneemzVcZEgvAVsj SLASs8N10eLdMzyjdImsD5Xm044k+51jXOh6LErYWc7kJ9rKg1plNzZGw A==; X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="306765334" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="306765334" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2022 08:55:32 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="956219759" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="956219759" Received: from sudhars1-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.216.120]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2022 08:55:32 -0700 Date: Thu, 13 Oct 2022 08:55:31 -0700 Message-ID: <878rljsop8.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Andi Shyti In-Reply-To: References: <20220927055020.3499420-1-badal.nilawar@intel.com> <20220927055020.3499420-7-badal.nilawar@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 6/7] drm/i915/hwmon: Expose power1_max_interval X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-hwmon@vger.kernel.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Mon, 03 Oct 2022 14:32:36 -0700, Andi Shyti wrote: > Hi Andi, > > diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon > > index f9d6d3b08bba..19b9fe3ef237 100644 > > --- a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon > > +++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon > > @@ -26,6 +26,15 @@ Description: RO. Card default power limit (default TDP setting). > > > > Only supported for particular Intel i915 graphics platforms. > > > > +What: /sys/devices/.../hwmon/hwmon/power1_max_interval > > +Date: February 2023 > > +KernelVersion: 6.2 > > +Contact: dri-devel@lists.freedesktop.org > > same question here. > > > +Description: RW. Sustained power limit interval (Tau in PL1/Tau) in > > + milliseconds over which sustained power is averaged. > > + > > + Only supported for particular Intel i915 graphics platforms. > > + > > What: /sys/devices/.../hwmon/hwmon/power1_crit > > Date: February 2023 > > KernelVersion: 6.2 > > diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c > > index 2394fa789793..641143956c45 100644 > > --- a/drivers/gpu/drm/i915/i915_hwmon.c > > +++ b/drivers/gpu/drm/i915/i915_hwmon.c > > @@ -20,11 +20,13 @@ > > * - power - microwatts > > * - curr - milliamperes > > * - energy - microjoules > > + * - time - milliseconds > > */ > > #define SF_VOLTAGE 1000 > > #define SF_POWER 1000000 > > #define SF_CURR 1000 > > #define SF_ENERGY 1000000 > > +#define SF_TIME 1000 > > > > struct hwm_reg { > > i915_reg_t gt_perf_status; > > @@ -53,6 +55,7 @@ struct i915_hwmon { > > struct hwm_reg rg; > > int scl_shift_power; > > int scl_shift_energy; > > + int scl_shift_time; > > }; > > > > static void > > @@ -161,6 +164,115 @@ hwm_energy(struct hwm_drvdata *ddat, long *energy) > > return 0; > > } > > > > +static ssize_t > > +hwm_power1_max_interval_show(struct device *dev, struct device_attribute *attr, > > + char *buf) > > +{ > > + struct hwm_drvdata *ddat = dev_get_drvdata(dev); > > + struct i915_hwmon *hwmon = ddat->hwmon; > > + intel_wakeref_t wakeref; > > + u32 r, x, y, x_w = 2; /* 2 bits */ > > + u64 tau4, out; > > + > > + with_intel_runtime_pm(ddat->uncore->rpm, wakeref) > > + r = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit); > > + > > + x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r); > > + y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r); > > + /* > > + * tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17) > > + * = (4 | x) << (y - 2) > > + * where (y - 2) ensures a 1.x fixed point representation of 1.x > > + * However because y can be < 2, we compute > > + * tau4 = (4 | x) << y > > + * but add 2 when doing the final right shift to account for units > > + */ > > + tau4 = ((1 << x_w) | x) << y; > > + /* val in hwmon interface units (millisec) */ > > + out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w); > > + > > + return sysfs_emit(buf, "%llu\n", out); > > +} > > + > > +static ssize_t > > +hwm_power1_max_interval_store(struct device *dev, > > + struct device_attribute *attr, > > + const char *buf, size_t count) > > +{ > > + struct hwm_drvdata *ddat = dev_get_drvdata(dev); > > + struct i915_hwmon *hwmon = ddat->hwmon; > > + long val, max_win, ret; > > you have some type mismatch here: > > - val should be unsigned long > - max_win should be u64 > - ret should be int Thanks, fixed in v9. > > > + u32 x, y, rxy, x_w = 2; /* 2 bits */ > > + u64 tau4, r; > > + > > +#define PKG_MAX_WIN_DEFAULT 0x12ull > > could you please add a comment here? Done. > > + > > + ret = kstrtoul(buf, 0, &val); > > + if (ret) > > + return ret; > > + > > + /* > > + * val must be < max in hwmon interface units. The steps below are > > + * explained in i915_power1_max_interval_show() > > + */ > > + r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT); > > + > > + x = REG_FIELD_GET(PKG_MAX_WIN_X, r); > > + y = REG_FIELD_GET(PKG_MAX_WIN_Y, r); > > + tau4 = ((1 << x_w) | x) << y; > > + max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w); > > + > > + if (val > max_win) > > + return -EINVAL; > > + > > + /* val in hw units */ > > + val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME); > > + /* Convert to 1.x * power(2,y) */ > > + if (!val) > > + return -EINVAL; > > + y = ilog2(val); > > + /* x = (val - (1 << y)) >> (y - 2); */ > > some leftover No, it's a comment describing what's happening in the line below. I've left it as is for now. Can remove it if you think it's unnecessary. > > > + x = (val - (1ul << y)) << x_w >> y; > > + > > + rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y); > > + > > + hwm_locked_with_pm_intel_uncore_rmw(ddat, hwmon->rg.pkg_rapl_limit, > > + PKG_PWR_LIM_1_TIME, rxy); > > + return count; > > +} > > + > > +static SENSOR_DEVICE_ATTR(power1_max_interval, 0664, > > + hwm_power1_max_interval_show, > > + hwm_power1_max_interval_store, 0); > > + > > +static struct attribute *hwm_attributes[] = { > > + &sensor_dev_attr_power1_max_interval.dev_attr.attr, > > + NULL > > +}; > > + > > +static umode_t hwm_attributes_visible(struct kobject *kobj, > > + struct attribute *attr, int index) > > +{ > > + struct device *dev = kobj_to_dev(kobj); > > + struct hwm_drvdata *ddat = dev_get_drvdata(dev); > > + struct i915_hwmon *hwmon = ddat->hwmon; > > + > > + if (attr == &sensor_dev_attr_power1_max_interval.dev_attr.attr) > > + return i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit) ? attr->mode : 0; > > + else > > + return 0; > > please remove the else Done. Thanks. -- Ashutosh > > +} > > + > > +static const struct attribute_group hwm_attrgroup = { > > + .attrs = hwm_attributes, > > + .is_visible = hwm_attributes_visible, > > +}; > > + > > +static const struct attribute_group *hwm_groups[] = { > > + &hwm_attrgroup, > > + NULL > > +}; > > + > > static const struct hwmon_channel_info *hwm_info[] = { > > HWMON_CHANNEL_INFO(in, HWMON_I_INPUT), > > HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT), > > @@ -472,6 +584,7 @@ hwm_get_preregistration_info(struct drm_i915_private *i915) > > > > hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit); > > hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit); > > + hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit); > > > > /* > > * Initialize 'struct hwm_energy_info', i.e. set fields to the > > @@ -510,7 +623,7 @@ void i915_hwmon_register(struct drm_i915_private *i915) > > hwmon_dev = devm_hwmon_device_register_with_info(dev, ddat->name, > > ddat, > > &hwm_chip_info, > > - NULL); > > + hwm_groups); > > if (IS_ERR(hwmon_dev)) { > > i915->hwmon = NULL; > > return; > > diff --git a/drivers/gpu/drm/i915/intel_mchbar_regs.h b/drivers/gpu/drm/i915/intel_mchbar_regs.h > > index bd42fb66e297..64aa1e9be463 100644 > > --- a/drivers/gpu/drm/i915/intel_mchbar_regs.h > > +++ b/drivers/gpu/drm/i915/intel_mchbar_regs.h > > @@ -194,6 +194,9 @@ > > */ > > #define PCU_PACKAGE_POWER_SKU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5930) > > #define PKG_PKG_TDP GENMASK_ULL(14, 0) > > +#define PKG_MAX_WIN GENMASK_ULL(54, 48) > > +#define PKG_MAX_WIN_X GENMASK_ULL(54, 53) > > +#define PKG_MAX_WIN_Y GENMASK_ULL(52, 48) > > > > #define PCU_PACKAGE_POWER_SKU_UNIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5938) > > #define PKG_PWR_UNIT REG_GENMASK(3, 0) > > @@ -212,6 +215,10 @@ > > #define RPE_MASK REG_GENMASK(15, 8) > > #define PCU_PACKAGE_RAPL_LIMIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x59a0) > > #define PKG_PWR_LIM_1 REG_GENMASK(14, 0) > > +#define PKG_PWR_LIM_1_EN REG_BIT(15) > > +#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17) > > +#define PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22) > > +#define PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17) > > > > /* snb MCH registers for priority tuning */ > > #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10) > > -- > > 2.25.1