From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28723ECAAD5 for ; Thu, 8 Sep 2022 05:27:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2764E10E958; Thu, 8 Sep 2022 05:27:44 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id D017910E958 for ; Thu, 8 Sep 2022 05:27:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662614860; x=1694150860; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=8/PU5HviRRh/ZvmGXTvEtK098B9q9nOKHHb+7zA0iz8=; b=T2HSfkxbVthZ3SaIBF6dsPguncg1Wq8KUuqbTCpnfU5OIpAEL7mU+yLK Arp4HGZ5T2MGu6dUM+PBm5oajGt3dLXfQa/MAauPsECSWvACopEnHImsx Tr7I+8jFLUESgAHG4PexumrWTcR0Lang1w8F0KriESaM/uxkRGteEhTPr BcWXaaCsFQOdA3TsT0ohF1oOlDsXbyd0m/zyrYBrno/0NavNyW86mwhTl zsRh7GhAfrg4DrjDBoMUEfCoZDKygXuSt3kb/Msaeigpmuu8JyV5sE3qI WBu+zaXKV6KO3crqklqFuhf6IShuCfM5LFQtfDKMXWRMRUWJhEr4Qf6ep w==; X-IronPort-AV: E=McAfee;i="6500,9779,10463"; a="297877493" X-IronPort-AV: E=Sophos;i="5.93,299,1654585200"; d="scan'208";a="297877493" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 22:27:40 -0700 X-IronPort-AV: E=Sophos;i="5.93,299,1654585200"; d="scan'208";a="565802952" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.224.252]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 22:27:40 -0700 Date: Wed, 07 Sep 2022 22:27:39 -0700 Message-ID: <878rmuxwok.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Jani Nikula In-Reply-To: <87h71mb22i.fsf@intel.com> References: <20220902235302.1112388-1-ashutosh.dixit@intel.com> <20220902235302.1112388-6-ashutosh.dixit@intel.com> <87h71mb22i.fsf@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 5/6] drm/i915/mtl: PERF_LIMIT_REASONS changes for MTL X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Mon, 05 Sep 2022 02:30:45 -0700, Jani Nikula wrote: > > On Fri, 02 Sep 2022, Ashutosh Dixit wrote: > > PERF_LIMIT_REASONS register for MTL media gt is different now. > > > > Cc: Badal Nilawar > > Signed-off-by: Ashutosh Dixit > > --- > > drivers/gpu/drm/i915/gt/intel_gt.h | 8 ++++++++ > > drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 4 ++-- > > drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 6 +++--- > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > 4 files changed, 14 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h > > index c9a359f35d0f..7286d47113ee 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gt.h > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.h > > @@ -9,6 +9,7 @@ > > #include "intel_engine_types.h" > > #include "intel_gt_types.h" > > #include "intel_reset.h" > > +#include "i915_reg.h" > > > > struct drm_i915_private; > > struct drm_printer; > > @@ -86,6 +87,13 @@ static inline bool intel_gt_is_wedged(const struct intel_gt *gt) > > return unlikely(test_bit(I915_WEDGED, >->reset.flags)); > > } > > > > +static inline > > +i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt) > > +{ > > + return gt->type == GT_MEDIA ? > > + MTL_MEDIA_PERF_LIMIT_REASONS : GT0_PERF_LIMIT_REASONS; > > +} > > Nowadays, I pretty much think of everything from the standpoint of > setting the example for future changes. Is this what we want people to > copy? Because that's what we do, look for examples for what we want to > achieve, and emulate. > > Do we want this to be duplicated for other registers? Choose register > offset based on platform/engine/fusing/whatever parameter? Is this a > register definition that should be in a _regs.h file? > > I don't know. MTL_MEDIA_PERF_LIMIT_REASONS is an actual register so I'd think it needs to be in a _regs.h file. And here we need to choose the register offset at runtime based on the gt. So I don't see any way round what's happening above unless you have other suggestions. > I've also grown to dislike static inlines a lot, and this one's the > worst because it actually can't be static inline because its passed as a > function pointer. Based on your feedback I've eliminated the static inline and moved the function definition to a .c in v2 (though gcc allows taking addresses of static inline's in .h files). Thanks. -- Ashutosh > > > BR, > Jani. > > > > > + > > int intel_gt_probe_all(struct drm_i915_private *i915); > > int intel_gt_tiles_init(struct drm_i915_private *i915); > > void intel_gt_release_all(struct drm_i915_private *i915); > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > > index 5c95cba5e5df..fe0091f953c1 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > > @@ -661,7 +661,7 @@ static int perf_limit_reasons_get(void *data, u64 *val) > > intel_wakeref_t wakeref; > > > > with_intel_runtime_pm(gt->uncore->rpm, wakeref) > > - *val = intel_uncore_read(gt->uncore, GT0_PERF_LIMIT_REASONS); > > + *val = intel_uncore_read(gt->uncore, intel_gt_perf_limit_reasons_reg(gt)); > > > > return 0; > > } > > @@ -673,7 +673,7 @@ static int perf_limit_reasons_clear(void *data, u64 val) > > > > /* Clear the upper 16 log bits, the lower 16 status bits are read-only */ > > with_intel_runtime_pm(gt->uncore->rpm, wakeref) > > - intel_uncore_rmw(gt->uncore, GT0_PERF_LIMIT_REASONS, > > + intel_uncore_rmw(gt->uncore, intel_gt_perf_limit_reasons_reg(gt), > > GT0_PERF_LIMIT_REASONS_LOG_MASK, 0); > > > > return 0; > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c > > index e066cc33d9f2..54deae45d81f 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c > > @@ -510,7 +510,7 @@ struct intel_gt_bool_throttle_attr { > > struct attribute attr; > > ssize_t (*show)(struct device *dev, struct device_attribute *attr, > > char *buf); > > - i915_reg_t reg32; > > + i915_reg_t (*reg32)(struct intel_gt *gt); > > u32 mask; > > }; > > > > @@ -521,7 +521,7 @@ static ssize_t throttle_reason_bool_show(struct device *dev, > > struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name); > > struct intel_gt_bool_throttle_attr *t_attr = > > (struct intel_gt_bool_throttle_attr *) attr; > > - bool val = rps_read_mask_mmio(>->rps, t_attr->reg32, t_attr->mask); > > + bool val = rps_read_mask_mmio(>->rps, t_attr->reg32(gt), t_attr->mask); > > > > return sysfs_emit(buff, "%u\n", val); > > } > > @@ -530,7 +530,7 @@ static ssize_t throttle_reason_bool_show(struct device *dev, > > struct intel_gt_bool_throttle_attr attr_##sysfs_func__ = { \ > > .attr = { .name = __stringify(sysfs_func__), .mode = 0444 }, \ > > .show = throttle_reason_bool_show, \ > > - .reg32 = GT0_PERF_LIMIT_REASONS, \ > > + .reg32 = intel_gt_perf_limit_reasons_reg, \ > > .mask = mask__, \ > > } > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 10126995e1f6..06d555321651 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -1803,6 +1803,7 @@ > > #define POWER_LIMIT_1_MASK REG_BIT(11) > > #define POWER_LIMIT_2_MASK REG_BIT(12) > > #define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16) > > +#define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030) > > > > #define CHV_CLK_CTL1 _MMIO(0x101100) > > #define VLV_CLK_CTL2 _MMIO(0x101104) > > -- > Jani Nikula, Intel Open Source Graphics Center