From: Jani Nikula <jani.nikula@intel.com>
To: Madhav Chauhan <madhav.chauhan@intel.com>,
intel-gfx@lists.freedesktop.org
Cc: paulo.r.zanoni@intel.com, rodrigo.vivi@intel.com
Subject: Re: [PATCH v5 03/13] drm/i915/icl: Enable DDI Buffer
Date: Tue, 11 Sep 2018 21:54:35 +0300 [thread overview]
Message-ID: <878t47eufo.fsf@intel.com> (raw)
In-Reply-To: <1531215614-6828-4-git-send-email-madhav.chauhan@intel.com>
On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> This patch enables DDI buffer by writing to DDI_BUF_CTL
> register and wait for DDI status to be *not idle* for a
> port.
>
> v2: Rebase
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index dc16c1f..41faa19 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -251,6 +251,25 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
> }
> }
>
> +static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + u32 tmp;
> + enum port port;
> +
> + for_each_dsi_port(port, intel_dsi->ports) {
> + tmp = I915_READ(DDI_BUF_CTL(port));
> + tmp |= DDI_BUF_CTL_ENABLE;
> + I915_WRITE(DDI_BUF_CTL(port), tmp);
> +
> + if (wait_for_us(!(I915_READ(DDI_BUF_CTL(port)) &
> + DDI_BUF_IS_IDLE),
> + 500))
IMO a "== 0" check reads better in wait_for_us.
> + DRM_ERROR("DDI port:%c buffer idle\n", port_name(port));
> + }
> +}
> +
> static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
> {
> /* step 4a: power up all lanes of the DDI used by DSI */
> @@ -261,6 +280,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>
> /* step 4c: configure voltage swing and skew */
> gen11_dsi_voltage_swing_program_seq(encoder);
> +
> + /* step 4d: enable DDI buffer */
Alas, this is step 4e now, and you have a new 4d to take care of for
B0+.
Regardless,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> + gen11_dsi_enable_ddi_buffer(encoder);
> }
>
> static void __attribute__((unused))
--
Jani Nikula, Intel Open Source Graphics Center
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next prev parent reply other threads:[~2018-09-11 18:54 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-10 9:40 [PATCH v5 00/13] ICELAKE DSI DRIVER Madhav Chauhan
2018-07-10 9:40 ` [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter Madhav Chauhan
2018-07-19 16:11 ` Ville Syrjälä
2018-07-19 18:35 ` Chauhan, Madhav
2018-07-27 11:57 ` Chauhan, Madhav
2018-09-11 17:46 ` Jani Nikula
2018-09-12 6:32 ` Madhav Chauhan
2018-09-10 12:20 ` Lisovskiy, Stanislav
2018-09-10 15:27 ` Madhav Chauhan
2018-09-11 8:08 ` Lisovskiy, Stanislav
2018-07-10 9:40 ` [PATCH v5 02/13] drm/i915/icl: DSI vswing programming sequence Madhav Chauhan
2018-09-06 14:01 ` [v5, " Kulkarni, Vandita
2018-09-10 7:43 ` Madhav Chauhan
2018-09-11 18:16 ` Jani Nikula
2018-09-12 6:34 ` Madhav Chauhan
2018-09-11 18:50 ` [PATCH v5 " Jani Nikula
2018-09-12 9:03 ` Madhav Chauhan
2018-09-12 9:10 ` Jani Nikula
2018-07-10 9:40 ` [PATCH v5 03/13] drm/i915/icl: Enable DDI Buffer Madhav Chauhan
2018-09-11 18:54 ` Jani Nikula [this message]
2018-09-12 9:06 ` Madhav Chauhan
2018-09-12 9:10 ` Jani Nikula
2018-07-10 9:40 ` [PATCH v5 04/13] drm/i915/icl: Define T_INIT_MASTER registers Madhav Chauhan
2018-09-11 19:18 ` Jani Nikula
2018-07-10 9:40 ` [PATCH v5 05/13] drm/i915/icl: Program " Madhav Chauhan
2018-09-11 19:17 ` Jani Nikula
2018-07-10 9:40 ` [PATCH v5 06/13] drm/i915/icl: Define data/clock lanes dphy timing registers Madhav Chauhan
2018-09-11 19:14 ` Jani Nikula
2018-09-12 9:11 ` Madhav Chauhan
2018-07-10 9:40 ` [PATCH v5 07/13] drm/i915/icl: Program DSI clock and data lane timing params Madhav Chauhan
2018-07-19 16:17 ` Ville Syrjälä
2018-07-10 9:40 ` [PATCH v5 08/13] drm/i915/icl: Define TA_TIMING_PARAM registers Madhav Chauhan
2018-09-11 19:23 ` Jani Nikula
2018-09-12 9:13 ` Madhav Chauhan
2018-07-10 9:40 ` [PATCH v5 09/13] drm/i915/icl: Program " Madhav Chauhan
2018-07-19 16:21 ` Ville Syrjälä
2018-07-20 8:08 ` Chauhan, Madhav
2018-09-11 19:26 ` Jani Nikula
2018-09-12 9:25 ` Madhav Chauhan
2018-09-12 9:39 ` Jani Nikula
2018-07-10 9:40 ` [PATCH v5 10/13] drm/i915/icl: Get DSI transcoder for a given port Madhav Chauhan
2018-07-10 9:40 ` [PATCH v5 11/13] drm/i915/icl: Add macros for MMIO of DSI transcoder registers Madhav Chauhan
2018-07-19 16:22 ` Ville Syrjälä
2018-07-20 8:55 ` Chauhan, Madhav
2018-09-12 9:36 ` Madhav Chauhan
2018-09-12 18:00 ` Ville Syrjälä
2018-09-14 6:12 ` Madhav Chauhan
2018-09-14 12:25 ` Ville Syrjälä
2018-09-14 13:06 ` Madhav Chauhan
2018-09-14 13:27 ` Madhav Chauhan
2018-09-14 13:41 ` Ville Syrjälä
2018-07-10 9:40 ` [PATCH v5 12/13] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register Madhav Chauhan
2018-09-11 19:30 ` Jani Nikula
2018-09-12 9:35 ` Madhav Chauhan
2018-09-12 9:47 ` Jani Nikula
2018-07-10 9:40 ` [PATCH v5 13/13] drm/i915/icl: Configure DSI transcoders Madhav Chauhan
2018-07-10 10:46 ` ✗ Fi.CI.CHECKPATCH: warning for ICELAKE DSI DRIVER (rev5) Patchwork
2018-07-10 10:51 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-07-10 11:04 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-10 16:28 ` ✓ Fi.CI.IGT: " Patchwork
2018-09-11 19:35 ` [PATCH v5 00/13] ICELAKE DSI DRIVER Jani Nikula
2018-09-12 6:16 ` Madhav Chauhan
2018-09-12 7:31 ` Jani Nikula
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