[PATCH 2/2] drm/i915/BXT: Get pipe conf from the port registers

[PATCH 2/2] drm/i915/BXT: Get pipe conf from the port registers

[Ramalingam C]

At BXT DSI, PIPE registers are inactive. So we can't get the
PIPE's mode parameters from them. The possible option is
retriving them from the PORT registers.

The required changes are added for BXT in intel_dsi_get_config
(encoder->get_config).

v2: Addressed the Jani's comments
    -removed the redundant call to encoder->get_config
    -read bpp from port register
    -removed retrival of src_size from encoder->get_config

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
Previously reviewed at https://patchwork.freedesktop.org/patch/75301/

 drivers/gpu/drm/i915/intel_dsi.c |   99 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 99 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 0de74e1..2117187 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -46,6 +46,11 @@ static const struct {
 	},
 };
 
+enum mipi_dsi_pixel_format reg_to_pixel_format(u32 fmt)
+{
+	return pixel_format_from_vbt(fmt);
+}
+
 static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
 {
 	struct drm_encoder *encoder = &intel_dsi->base.base;
@@ -740,14 +745,108 @@ out_put_power:
 	return active;
 }
 
+/* return pixels equvalent to txbyteclkhs */
+static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
+		       u16 burst_mode_ratio)
+{
+	return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
+						(bpp * burst_mode_ratio));
+}
+
+static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
+				 struct intel_crtc_state *pipe_config)
+{
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_display_mode *adjusted_mode =
+					&pipe_config->base.adjusted_mode;
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	unsigned int lane_count = intel_dsi->lane_count;
+	unsigned int bpp, fmt;
+	enum port port;
+	u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
+
+	/*
+	 * Atleast one port is active as encoder->get_config called only if
+	 * encoder->get_hw_state() returns true.
+	 */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (!(I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE))
+			continue;
+		break;
+	}
+
+	fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
+	pipe_config->pipe_bpp = reg_to_pixel_format(fmt);
+
+	bpp = mipi_dsi_pixel_format_to_bpp(pipe_config->pipe_bpp);
+
+	/* In terms of pixels */
+	adjusted_mode->crtc_hdisplay =
+				I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
+	adjusted_mode->crtc_vdisplay =
+				I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
+	adjusted_mode->crtc_vtotal =
+				I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
+
+	hactive = adjusted_mode->crtc_hdisplay;
+	hfp = I915_READ(MIPI_HFP_COUNT(port));
+
+	/*
+	 * meaningful for video mode non-burst sync pulse mode only,
+	 * can be zero for non-burst sync events and burst modes
+	 */
+	hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
+	hbp = I915_READ(MIPI_HBP_COUNT(port));
+
+	/* horizontal values are in terms of high speed byte clock */
+	hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
+					intel_dsi->burst_mode_ratio);
+	hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
+					intel_dsi->burst_mode_ratio);
+	hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
+					intel_dsi->burst_mode_ratio);
+
+	if (intel_dsi->dual_link) {
+		hfp *= 2;
+		hsync *= 2;
+		hbp *= 2;
+	}
+
+	/* vertical values are in terms of lines */
+	vfp = I915_READ(MIPI_VFP_COUNT(port));
+	vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
+	vbp = I915_READ(MIPI_VBP_COUNT(port));
+
+	adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
+	adjusted_mode->crtc_hsync_start =
+				hfp + adjusted_mode->crtc_hdisplay;
+	adjusted_mode->crtc_hsync_end =
+				hsync + adjusted_mode->crtc_hsync_start;
+	adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
+	adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
+
+	adjusted_mode->crtc_vsync_start =
+				vfp + adjusted_mode->crtc_vdisplay;
+	adjusted_mode->crtc_vsync_end =
+				vsync + adjusted_mode->crtc_vsync_start;
+	adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
+	adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
+}
+
+
 static void intel_dsi_get_config(struct intel_encoder *encoder,
 				 struct intel_crtc_state *pipe_config)
 {
+	struct drm_device *dev = encoder->base.dev;
 	u32 pclk;
 	DRM_DEBUG_KMS("\n");
 
 	pipe_config->has_dsi_encoder = true;
 
+	if (IS_BROXTON(dev))
+		bxt_dsi_get_pipe_config(encoder, pipe_config);
+
 	/*
 	 * DPLL_MD is not used in case of DSI, reading will get some default value
 	 * set dpll_md = 0
-- 
1.7.9.5

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Re: [PATCH 2/2] drm/i915/BXT: Get pipe conf from the port registers

[Ramalingam C]

Jani/Daniel,

I am working on implementing the pipe_config compare as suggested by 
daniel at 
https://lists.freedesktop.org/archives/intel-gfx/2016-March/091148.html

But I think this patch need not wait for that change. Either way this 
patch is required. We can continue review on this and proceed further.

On Wednesday 30 March 2016 07:23 PM, Ramalingam C wrote:
> At BXT DSI, PIPE registers are inactive. So we can't get the
> PIPE's mode parameters from them. The possible option is
> retriving them from the PORT registers.
>
> The required changes are added for BXT in intel_dsi_get_config
> (encoder->get_config).
>
> v2: Addressed the Jani's comments
>      -removed the redundant call to encoder->get_config
>      -read bpp from port register
>      -removed retrival of src_size from encoder->get_config
>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> Previously reviewed at https://patchwork.freedesktop.org/patch/75301/
>
>   drivers/gpu/drm/i915/intel_dsi.c |   99 ++++++++++++++++++++++++++++++++++++++
>   1 file changed, 99 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 0de74e1..2117187 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -46,6 +46,11 @@ static const struct {
>   	},
>   };
>   
> +enum mipi_dsi_pixel_format reg_to_pixel_format(u32 fmt)
> +{
> +	return pixel_format_from_vbt(fmt);
> +}
> +
>   static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
>   {
>   	struct drm_encoder *encoder = &intel_dsi->base.base;
> @@ -740,14 +745,108 @@ out_put_power:
>   	return active;
>   }
>   
> +/* return pixels equvalent to txbyteclkhs */
> +static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
> +		       u16 burst_mode_ratio)
> +{
> +	return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
> +						(bpp * burst_mode_ratio));
> +}
> +
> +static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
> +				 struct intel_crtc_state *pipe_config)
> +{
> +	struct drm_device *dev = encoder->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct drm_display_mode *adjusted_mode =
> +					&pipe_config->base.adjusted_mode;
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	unsigned int lane_count = intel_dsi->lane_count;
> +	unsigned int bpp, fmt;
> +	enum port port;
> +	u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
> +
> +	/*
> +	 * Atleast one port is active as encoder->get_config called only if
> +	 * encoder->get_hw_state() returns true.
> +	 */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (!(I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE))
> +			continue;
> +		break;
> +	}
> +
> +	fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
> +	pipe_config->pipe_bpp = reg_to_pixel_format(fmt);
> +
> +	bpp = mipi_dsi_pixel_format_to_bpp(pipe_config->pipe_bpp);
> +
> +	/* In terms of pixels */
> +	adjusted_mode->crtc_hdisplay =
> +				I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
> +	adjusted_mode->crtc_vdisplay =
> +				I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
> +	adjusted_mode->crtc_vtotal =
> +				I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
> +
> +	hactive = adjusted_mode->crtc_hdisplay;
> +	hfp = I915_READ(MIPI_HFP_COUNT(port));
> +
> +	/*
> +	 * meaningful for video mode non-burst sync pulse mode only,
> +	 * can be zero for non-burst sync events and burst modes
> +	 */
> +	hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
> +	hbp = I915_READ(MIPI_HBP_COUNT(port));
> +
> +	/* horizontal values are in terms of high speed byte clock */
> +	hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
> +					intel_dsi->burst_mode_ratio);
> +	hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
> +					intel_dsi->burst_mode_ratio);
> +	hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
> +					intel_dsi->burst_mode_ratio);
> +
> +	if (intel_dsi->dual_link) {
> +		hfp *= 2;
> +		hsync *= 2;
> +		hbp *= 2;
> +	}
> +
> +	/* vertical values are in terms of lines */
> +	vfp = I915_READ(MIPI_VFP_COUNT(port));
> +	vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
> +	vbp = I915_READ(MIPI_VBP_COUNT(port));
> +
> +	adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
> +	adjusted_mode->crtc_hsync_start =
> +				hfp + adjusted_mode->crtc_hdisplay;
> +	adjusted_mode->crtc_hsync_end =
> +				hsync + adjusted_mode->crtc_hsync_start;
> +	adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
> +	adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
> +
> +	adjusted_mode->crtc_vsync_start =
> +				vfp + adjusted_mode->crtc_vdisplay;
> +	adjusted_mode->crtc_vsync_end =
> +				vsync + adjusted_mode->crtc_vsync_start;
> +	adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
> +	adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
> +}
> +
> +
>   static void intel_dsi_get_config(struct intel_encoder *encoder,
>   				 struct intel_crtc_state *pipe_config)
>   {
> +	struct drm_device *dev = encoder->base.dev;
>   	u32 pclk;
>   	DRM_DEBUG_KMS("\n");
>   
>   	pipe_config->has_dsi_encoder = true;
>   
> +	if (IS_BROXTON(dev))
> +		bxt_dsi_get_pipe_config(encoder, pipe_config);
> +
>   	/*
>   	 * DPLL_MD is not used in case of DSI, reading will get some default value
>   	 * set dpll_md = 0

-- 
Thanks,
--Ram

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Re: [PATCH 2/2] drm/i915/BXT: Get pipe conf from the port registers

[Jani Nikula]

On Wed, 30 Mar 2016, Ramalingam C <ramalingam.c@intel.com> wrote:
> At BXT DSI, PIPE registers are inactive. So we can't get the
> PIPE's mode parameters from them. The possible option is
> retriving them from the PORT registers.
>
> The required changes are added for BXT in intel_dsi_get_config
> (encoder->get_config).
>
> v2: Addressed the Jani's comments
>     -removed the redundant call to encoder->get_config
>     -read bpp from port register
>     -removed retrival of src_size from encoder->get_config
>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> Previously reviewed at https://patchwork.freedesktop.org/patch/75301/
>
>  drivers/gpu/drm/i915/intel_dsi.c |   99 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 99 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 0de74e1..2117187 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -46,6 +46,11 @@ static const struct {
>  	},
>  };
>  
> +enum mipi_dsi_pixel_format reg_to_pixel_format(u32 fmt)
> +{
> +	return pixel_format_from_vbt(fmt);
> +}
> +

See reply to preceding patch.

>  static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
>  {
>  	struct drm_encoder *encoder = &intel_dsi->base.base;
> @@ -740,14 +745,108 @@ out_put_power:
>  	return active;
>  }
>  
> +/* return pixels equvalent to txbyteclkhs */
> +static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
> +		       u16 burst_mode_ratio)
> +{
> +	return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
> +						(bpp * burst_mode_ratio));
> +}
> +
> +static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
> +				 struct intel_crtc_state *pipe_config)
> +{
> +	struct drm_device *dev = encoder->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct drm_display_mode *adjusted_mode =
> +					&pipe_config->base.adjusted_mode;
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	unsigned int lane_count = intel_dsi->lane_count;
> +	unsigned int bpp, fmt;
> +	enum port port;
> +	u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
> +
> +	/*
> +	 * Atleast one port is active as encoder->get_config called only if
> +	 * encoder->get_hw_state() returns true.
> +	 */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (!(I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE))
> +			continue;
> +		break;

In other words,

	if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
		break;


> +	}
> +
> +	fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
> +	pipe_config->pipe_bpp = reg_to_pixel_format(fmt);
> +
> +	bpp = mipi_dsi_pixel_format_to_bpp(pipe_config->pipe_bpp);
> +
> +	/* In terms of pixels */
> +	adjusted_mode->crtc_hdisplay =
> +				I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
> +	adjusted_mode->crtc_vdisplay =
> +				I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
> +	adjusted_mode->crtc_vtotal =
> +				I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
> +
> +	hactive = adjusted_mode->crtc_hdisplay;
> +	hfp = I915_READ(MIPI_HFP_COUNT(port));
> +
> +	/*
> +	 * meaningful for video mode non-burst sync pulse mode only,
> +	 * can be zero for non-burst sync events and burst modes
> +	 */
> +	hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
> +	hbp = I915_READ(MIPI_HBP_COUNT(port));
> +
> +	/* horizontal values are in terms of high speed byte clock */
> +	hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
> +					intel_dsi->burst_mode_ratio);
> +	hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
> +					intel_dsi->burst_mode_ratio);
> +	hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
> +					intel_dsi->burst_mode_ratio);
> +
> +	if (intel_dsi->dual_link) {
> +		hfp *= 2;
> +		hsync *= 2;
> +		hbp *= 2;
> +	}
> +
> +	/* vertical values are in terms of lines */
> +	vfp = I915_READ(MIPI_VFP_COUNT(port));
> +	vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
> +	vbp = I915_READ(MIPI_VBP_COUNT(port));
> +
> +	adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
> +	adjusted_mode->crtc_hsync_start =
> +				hfp + adjusted_mode->crtc_hdisplay;
> +	adjusted_mode->crtc_hsync_end =
> +				hsync + adjusted_mode->crtc_hsync_start;
> +	adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
> +	adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
> +
> +	adjusted_mode->crtc_vsync_start =
> +				vfp + adjusted_mode->crtc_vdisplay;
> +	adjusted_mode->crtc_vsync_end =
> +				vsync + adjusted_mode->crtc_vsync_start;
> +	adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
> +	adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;

As I suggested on IRC, to make progress please keep everything that we
can calculate accurately (and hence get no warnings about the diff for
them) and leave out all that is not accurate.

We need to get back to them too, but currently there seems to be
disagreement on what is the best/feasible/possible option.

BR,
Jani.


> +}
> +
> +
>  static void intel_dsi_get_config(struct intel_encoder *encoder,
>  				 struct intel_crtc_state *pipe_config)
>  {
> +	struct drm_device *dev = encoder->base.dev;
>  	u32 pclk;
>  	DRM_DEBUG_KMS("\n");
>  
>  	pipe_config->has_dsi_encoder = true;
>  
> +	if (IS_BROXTON(dev))
> +		bxt_dsi_get_pipe_config(encoder, pipe_config);
> +
>  	/*
>  	 * DPLL_MD is not used in case of DSI, reading will get some default value
>  	 * set dpll_md = 0

-- 
Jani Nikula, Intel Open Source Technology Center
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[PATCH 1/2] drm/i915: Sharing the pixel_format_from_vbt to whole i915

[Ramalingam C]

Shared the function pixel_format_from_vbt for whole display module.
Function declaration is added to intel_dsi.h.

V2: Moved the function to intel_dsi.c and renamed as per the purpose
	of the function. Suggested by Jani.

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>

Previously reviewed at https://lists.freedesktop.org/archives/intel-gfx/2016-April/091736.html
---
 drivers/gpu/drm/i915/intel_dsi.c           |   18 ++++++++++++++++++
 drivers/gpu/drm/i915/intel_dsi.h           |    1 +
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |   23 +++--------------------
 3 files changed, 22 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 0de74e1..a0f374f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -46,6 +46,24 @@ static const struct {
 	},
 };
 
+enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
+{
+	/* It just so happens the VBT matches register contents. */
+	switch (fmt) {
+	case VID_MODE_FORMAT_RGB888:
+		return MIPI_DSI_FMT_RGB888;
+	case VID_MODE_FORMAT_RGB666:
+		return MIPI_DSI_FMT_RGB666;
+	case VID_MODE_FORMAT_RGB666_PACKED:
+		return MIPI_DSI_FMT_RGB666_PACKED;
+	case VID_MODE_FORMAT_RGB565:
+		return MIPI_DSI_FMT_RGB565;
+	default:
+		MISSING_CASE(fmt);
+		return MIPI_DSI_FMT_RGB666;
+	}
+}
+
 static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
 {
 	struct drm_encoder *encoder = &intel_dsi->base.base;
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index ec58ead..dabde19 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -134,5 +134,6 @@ extern void intel_dsi_reset_clocks(struct intel_encoder *encoder,
 							enum port port);
 
 struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
+enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
 
 #endif /* _INTEL_DSI_H */
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 8302a97..ca1b016 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -412,25 +412,6 @@ static const struct drm_panel_funcs vbt_panel_funcs = {
 	.get_modes = vbt_panel_get_modes,
 };
 
-/* XXX: This should be done when parsing the VBT in intel_bios.c */
-static enum mipi_dsi_pixel_format pixel_format_from_vbt(u32 fmt)
-{
-	/* It just so happens the VBT matches register contents. */
-	switch (fmt) {
-	case VID_MODE_FORMAT_RGB888:
-		return MIPI_DSI_FMT_RGB888;
-	case VID_MODE_FORMAT_RGB666:
-		return MIPI_DSI_FMT_RGB666;
-	case VID_MODE_FORMAT_RGB666_PACKED:
-		return MIPI_DSI_FMT_RGB666_PACKED;
-	case VID_MODE_FORMAT_RGB565:
-		return MIPI_DSI_FMT_RGB565;
-	default:
-		MISSING_CASE(fmt);
-		return MIPI_DSI_FMT_RGB666;
-	}
-}
-
 struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
 {
 	struct drm_device *dev = intel_dsi->base.base.dev;
@@ -455,7 +436,9 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
 	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
 	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
-	intel_dsi->pixel_format = pixel_format_from_vbt(mipi_config->videomode_color_format << 7);
+	intel_dsi->pixel_format =
+			pixel_format_from_register_bits(
+				mipi_config->videomode_color_format << 7);
 	bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 
 	intel_dsi->dual_link = mipi_config->dual_link;
-- 
1.7.9.5

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[PATCH 2/2] drm/i915/BXT: Get pipe conf from the port registers

[Ramalingam C]

At BXT DSI, PIPE registers are inactive. So we can't get the
PIPE's mode parameters from them. The possible option is
retriving them from the PORT registers.

The required changes are added for BXT in intel_dsi_get_config
(encoder->get_config).

v2: Addressed the Jani's comments
    -removed the redundant call to encoder->get_config
    -read bpp from port register
    -removed retrival of src_size from encoder->get_config

v3: pipe_config->pipe_bpp is fixed
    Jani's review comments addressed:
	Few horizontal timing parameters dropped from the patch to make
	progress, as there seems to be some disagreement on
	best/feasible/possible options.

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>

Previously Reviewed at: https://lists.freedesktop.org/archives/intel-gfx/2016-April/091737.html
---
 drivers/gpu/drm/i915/intel_dsi.c |   60 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index a0f374f..a1e0547 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -758,14 +758,74 @@ out_put_power:
 	return active;
 }
 
+static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
+				 struct intel_crtc_state *pipe_config)
+{
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_display_mode *adjusted_mode =
+					&pipe_config->base.adjusted_mode;
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	unsigned int bpp, fmt;
+	enum port port;
+	u16 vfp, vsync, vbp;
+
+	/*
+	 * Atleast one port is active as encoder->get_config called only if
+	 * encoder->get_hw_state() returns true.
+	 */
+	for_each_dsi_port(port, intel_dsi->ports) {
+		if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
+			break;
+	}
+
+	fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
+	pipe_config->pipe_bpp =
+			mipi_dsi_pixel_format_to_bpp(
+				pixel_format_from_register_bits(fmt));
+	bpp = pipe_config->pipe_bpp;
+
+	/* In terms of pixels */
+	adjusted_mode->crtc_hdisplay =
+				I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
+	adjusted_mode->crtc_vdisplay =
+				I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
+	adjusted_mode->crtc_vtotal =
+				I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
+
+	/*
+	 * TODO: Retrieve hfp, hsync and hbp. Adjust them for dual link and
+	 * calculate hsync_start, hsync_end, htotal and hblank_end
+	 */
+
+	/* vertical values are in terms of lines */
+	vfp = I915_READ(MIPI_VFP_COUNT(port));
+	vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
+	vbp = I915_READ(MIPI_VBP_COUNT(port));
+
+	adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
+
+	adjusted_mode->crtc_vsync_start =
+				vfp + adjusted_mode->crtc_vdisplay;
+	adjusted_mode->crtc_vsync_end =
+				vsync + adjusted_mode->crtc_vsync_start;
+	adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
+	adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
+}
+
+
 static void intel_dsi_get_config(struct intel_encoder *encoder,
 				 struct intel_crtc_state *pipe_config)
 {
+	struct drm_device *dev = encoder->base.dev;
 	u32 pclk;
 	DRM_DEBUG_KMS("\n");
 
 	pipe_config->has_dsi_encoder = true;
 
+	if (IS_BROXTON(dev))
+		bxt_dsi_get_pipe_config(encoder, pipe_config);
+
 	/*
 	 * DPLL_MD is not used in case of DSI, reading will get some default value
 	 * set dpll_md = 0
-- 
1.7.9.5

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✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Sharing the pixel_format_from_vbt to whole i915

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Sharing the pixel_format_from_vbt to whole i915
URL   : https://patchwork.freedesktop.org/series/5405/
State : failure

== Summary ==

Series 5405v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/5405/revisions/1/mbox/

Test drv_hangman:
        Subgroup error-state-basic:
                fail       -> PASS       (ilk-hp8440p)
Test drv_module_reload_basic:
                dmesg-warn -> PASS       (bsw-nuc-2)
Test gem_basic:
        Subgroup bad-close:
                dmesg-warn -> PASS       (bsw-nuc-2)
        Subgroup create-close:
                dmesg-warn -> PASS       (bsw-nuc-2)
Test gem_ctx_create:
        Subgroup basic:
                pass       -> DMESG-WARN (bsw-nuc-2)
Test gem_ctx_param_basic:
        Subgroup invalid-param-set:
                pass       -> DMESG-WARN (bsw-nuc-2)
        Subgroup non-root-set:
                dmesg-warn -> PASS       (bsw-nuc-2)
        Subgroup non-root-set-no-zeromap:
                dmesg-warn -> PASS       (bsw-nuc-2)
        Subgroup root-set:
                pass       -> DMESG-WARN (bsw-nuc-2)
Test gem_ctx_switch:
        Subgroup basic-default:
                pass       -> SKIP       (bsw-nuc-2)
Test gem_exec_basic:
        Subgroup basic-blt:
                pass       -> SKIP       (bsw-nuc-2)
        Subgroup basic-render:
                skip       -> PASS       (bsw-nuc-2)
Test gem_exec_suspend:
        Subgroup basic-s3:
                pass       -> SKIP       (bsw-nuc-2)
Test gem_exec_whisper:
        Subgroup basic:
                skip       -> PASS       (bsw-nuc-2)
Test gem_flink_basic:
        Subgroup basic:
                dmesg-warn -> PASS       (bsw-nuc-2)
        Subgroup flink-lifetime:
                dmesg-warn -> PASS       (bsw-nuc-2)
Test gem_linear_blits:
        Subgroup basic:
                dmesg-fail -> PASS       (bsw-nuc-2)
Test gem_mmap_gtt:
        Subgroup basic-write-gtt:
                dmesg-warn -> PASS       (bsw-nuc-2)
        Subgroup basic-write-read-distinct:
                pass       -> DMESG-WARN (bsw-nuc-2)
Test gem_pread:
        Subgroup basic:
                pass       -> DMESG-WARN (bsw-nuc-2)
Test gem_ringfill:
        Subgroup basic-default-hang:
                pass       -> SKIP       (bsw-nuc-2)
        Subgroup basic-default-interruptible:
                skip       -> DMESG-FAIL (bsw-nuc-2)
Test gem_sync:
        Subgroup basic-all:
                dmesg-fail -> PASS       (bsw-nuc-2)
        Subgroup basic-bsd:
                skip       -> PASS       (bsw-nuc-2)
        Subgroup basic-default:
                skip       -> PASS       (bsw-nuc-2)
        Subgroup basic-render:
                incomplete -> PASS       (bdw-nuci7) UNSTABLE
        Subgroup basic-vebox:
                skip       -> PASS       (bsw-nuc-2)
Test gem_tiled_fence_blits:
        Subgroup basic:
                dmesg-fail -> PASS       (bsw-nuc-2)
Test kms_addfb_basic:
        Subgroup bad-pitch-256:
                pass       -> DMESG-WARN (bsw-nuc-2)
        Subgroup bo-too-small-due-to-tiling:
                dmesg-warn -> PASS       (bsw-nuc-2)
        Subgroup size-max:
                dmesg-warn -> PASS       (bsw-nuc-2)
        Subgroup too-high:
                dmesg-warn -> PASS       (bsw-nuc-2)
Test kms_flip:
        Subgroup basic-flip-vs-modeset:
                dmesg-fail -> PASS       (bsw-nuc-2)
                pass       -> DMESG-WARN (ilk-hp8440p) UNSTABLE
        Subgroup basic-flip-vs-wf_vblank:
                pass       -> FAIL       (snb-x220t)
Test kms_force_connector_basic:
        Subgroup force-connector-state:
                skip       -> PASS       (ivb-t430s)
        Subgroup prune-stale-modes:
                pass       -> SKIP       (ilk-hp8440p)
Test kms_pipe_crc_basic:
        Subgroup hang-read-crc-pipe-b:
                pass       -> DMESG-WARN (ilk-hp8440p)
Test pm_rpm:
        Subgroup basic-rte:
                pass       -> DMESG-WARN (byt-nuc) UNSTABLE
Test prime_self_import:
        Subgroup basic-llseek-size:
                pass       -> DMESG-WARN (bsw-nuc-2)
        Subgroup basic-with_one_bo_two_files:
                pass       -> DMESG-WARN (bsw-nuc-2)

bdw-nuci7        total:196  pass:184  dwarn:0   dfail:0   fail:0   skip:12 
bdw-ultra        total:196  pass:175  dwarn:0   dfail:0   fail:0   skip:21 
bsw-nuc-2        total:141  pass:80   dwarn:24  dfail:1   fail:0   skip:35 
byt-nuc          total:196  pass:160  dwarn:1   dfail:0   fail:0   skip:35 
hsw-brixbox      total:196  pass:174  dwarn:0   dfail:0   fail:0   skip:22 
hsw-gt2          total:196  pass:179  dwarn:0   dfail:0   fail:0   skip:17 
ilk-hp8440p      total:196  pass:129  dwarn:2   dfail:0   fail:0   skip:65 
ivb-t430s        total:196  pass:171  dwarn:0   dfail:0   fail:0   skip:25 
skl-i7k-2        total:196  pass:173  dwarn:0   dfail:0   fail:0   skip:23 
skl-nuci5        total:196  pass:185  dwarn:0   dfail:0   fail:0   skip:11 
snb-dellxps      total:196  pass:162  dwarn:0   dfail:0   fail:0   skip:34 
snb-x220t        total:196  pass:161  dwarn:0   dfail:0   fail:2   skip:33 

Results at /archive/results/CI_IGT_test/Patchwork_1825/

6b0bf94b75318abeab4c95fbf0507bc54d8959be drm-intel-nightly: 2016y-04m-07d-08h-29m-47s UTC integration manifest
f61e309357f54fdc441fd20996225232627daa19 drm/i915/BXT: Get pipe conf from the port registers
81be0d7c63a7ef0c202434202d4f2982f5dcf304 drm/i915: Sharing the pixel_format_from_vbt to whole i915

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Re: ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Sharing the pixel_format_from_vbt to whole i915

[Jani Nikula]

On Thu, 07 Apr 2016, Patchwork <patchwork@emeril.freedesktop.org> wrote:
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915: Sharing the pixel_format_from_vbt to whole i915
> URL   : https://patchwork.freedesktop.org/series/5405/
> State : failure
>
> == Summary ==
>
> Series 5405v1 Series without cover letter
> http://patchwork.freedesktop.org/api/1.0/series/5405/revisions/1/mbox/
>
> Test drv_hangman:
>         Subgroup error-state-basic:
>                 fail       -> PASS       (ilk-hp8440p)
> Test drv_module_reload_basic:
>                 dmesg-warn -> PASS       (bsw-nuc-2)
> Test gem_basic:
>         Subgroup bad-close:
>                 dmesg-warn -> PASS       (bsw-nuc-2)
>         Subgroup create-close:
>                 dmesg-warn -> PASS       (bsw-nuc-2)
> Test gem_ctx_create:
>         Subgroup basic:
>                 pass       -> DMESG-WARN (bsw-nuc-2)
> Test gem_ctx_param_basic:
>         Subgroup invalid-param-set:
>                 pass       -> DMESG-WARN (bsw-nuc-2)
>         Subgroup non-root-set:
>                 dmesg-warn -> PASS       (bsw-nuc-2)
>         Subgroup non-root-set-no-zeromap:
>                 dmesg-warn -> PASS       (bsw-nuc-2)
>         Subgroup root-set:
>                 pass       -> DMESG-WARN (bsw-nuc-2)
> Test gem_ctx_switch:
>         Subgroup basic-default:
>                 pass       -> SKIP       (bsw-nuc-2)
> Test gem_exec_basic:
>         Subgroup basic-blt:
>                 pass       -> SKIP       (bsw-nuc-2)
>         Subgroup basic-render:
>                 skip       -> PASS       (bsw-nuc-2)
> Test gem_exec_suspend:
>         Subgroup basic-s3:
>                 pass       -> SKIP       (bsw-nuc-2)
> Test gem_exec_whisper:
>         Subgroup basic:
>                 skip       -> PASS       (bsw-nuc-2)
> Test gem_flink_basic:
>         Subgroup basic:
>                 dmesg-warn -> PASS       (bsw-nuc-2)
>         Subgroup flink-lifetime:
>                 dmesg-warn -> PASS       (bsw-nuc-2)
> Test gem_linear_blits:
>         Subgroup basic:
>                 dmesg-fail -> PASS       (bsw-nuc-2)
> Test gem_mmap_gtt:
>         Subgroup basic-write-gtt:
>                 dmesg-warn -> PASS       (bsw-nuc-2)
>         Subgroup basic-write-read-distinct:
>                 pass       -> DMESG-WARN (bsw-nuc-2)
> Test gem_pread:
>         Subgroup basic:
>                 pass       -> DMESG-WARN (bsw-nuc-2)
> Test gem_ringfill:
>         Subgroup basic-default-hang:
>                 pass       -> SKIP       (bsw-nuc-2)
>         Subgroup basic-default-interruptible:
>                 skip       -> DMESG-FAIL (bsw-nuc-2)
> Test gem_sync:
>         Subgroup basic-all:
>                 dmesg-fail -> PASS       (bsw-nuc-2)
>         Subgroup basic-bsd:
>                 skip       -> PASS       (bsw-nuc-2)
>         Subgroup basic-default:
>                 skip       -> PASS       (bsw-nuc-2)
>         Subgroup basic-render:
>                 incomplete -> PASS       (bdw-nuci7) UNSTABLE
>         Subgroup basic-vebox:
>                 skip       -> PASS       (bsw-nuc-2)
> Test gem_tiled_fence_blits:
>         Subgroup basic:
>                 dmesg-fail -> PASS       (bsw-nuc-2)
> Test kms_addfb_basic:
>         Subgroup bad-pitch-256:
>                 pass       -> DMESG-WARN (bsw-nuc-2)
>         Subgroup bo-too-small-due-to-tiling:
>                 dmesg-warn -> PASS       (bsw-nuc-2)
>         Subgroup size-max:
>                 dmesg-warn -> PASS       (bsw-nuc-2)
>         Subgroup too-high:
>                 dmesg-warn -> PASS       (bsw-nuc-2)
> Test kms_flip:
>         Subgroup basic-flip-vs-modeset:
>                 dmesg-fail -> PASS       (bsw-nuc-2)
>                 pass       -> DMESG-WARN (ilk-hp8440p) UNSTABLE
>         Subgroup basic-flip-vs-wf_vblank:
>                 pass       -> FAIL       (snb-x220t)
> Test kms_force_connector_basic:
>         Subgroup force-connector-state:
>                 skip       -> PASS       (ivb-t430s)
>         Subgroup prune-stale-modes:
>                 pass       -> SKIP       (ilk-hp8440p)
> Test kms_pipe_crc_basic:
>         Subgroup hang-read-crc-pipe-b:
>                 pass       -> DMESG-WARN (ilk-hp8440p)
> Test pm_rpm:
>         Subgroup basic-rte:
>                 pass       -> DMESG-WARN (byt-nuc) UNSTABLE
> Test prime_self_import:
>         Subgroup basic-llseek-size:
>                 pass       -> DMESG-WARN (bsw-nuc-2)
>         Subgroup basic-with_one_bo_two_files:
>                 pass       -> DMESG-WARN (bsw-nuc-2)

*sigh*, there's pretty much no way the patches could cause any of
 this. :(

BR,
Jani.

>
> bdw-nuci7        total:196  pass:184  dwarn:0   dfail:0   fail:0   skip:12 
> bdw-ultra        total:196  pass:175  dwarn:0   dfail:0   fail:0   skip:21 
> bsw-nuc-2        total:141  pass:80   dwarn:24  dfail:1   fail:0   skip:35 
> byt-nuc          total:196  pass:160  dwarn:1   dfail:0   fail:0   skip:35 
> hsw-brixbox      total:196  pass:174  dwarn:0   dfail:0   fail:0   skip:22 
> hsw-gt2          total:196  pass:179  dwarn:0   dfail:0   fail:0   skip:17 
> ilk-hp8440p      total:196  pass:129  dwarn:2   dfail:0   fail:0   skip:65 
> ivb-t430s        total:196  pass:171  dwarn:0   dfail:0   fail:0   skip:25 
> skl-i7k-2        total:196  pass:173  dwarn:0   dfail:0   fail:0   skip:23 
> skl-nuci5        total:196  pass:185  dwarn:0   dfail:0   fail:0   skip:11 
> snb-dellxps      total:196  pass:162  dwarn:0   dfail:0   fail:0   skip:34 
> snb-x220t        total:196  pass:161  dwarn:0   dfail:0   fail:2   skip:33 
>
> Results at /archive/results/CI_IGT_test/Patchwork_1825/
>
> 6b0bf94b75318abeab4c95fbf0507bc54d8959be drm-intel-nightly: 2016y-04m-07d-08h-29m-47s UTC integration manifest
> f61e309357f54fdc441fd20996225232627daa19 drm/i915/BXT: Get pipe conf from the port registers
> 81be0d7c63a7ef0c202434202d4f2982f5dcf304 drm/i915: Sharing the pixel_format_from_vbt to whole i915
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Sharing the pixel_format_from_vbt to whole i915

[Tomi Sarvela]

On Thursday 07 April 2016 15:58:12 Jani Nikula wrote:
> 
> *sigh*, there's pretty much no way the patches could cause any of
>  this. :(
> 
> BR,
> Jani.

I'm guessing that the IGT randomized testing order is hiding problems ... 
can't really reproduce easily. I kind of liked the old system better.

BSW isn't feeling well, anyway.

Tomi
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Re: [PATCH 2/2] drm/i915/BXT: Get pipe conf from the port registers

[Jani Nikula]

On Thu, 07 Apr 2016, Ramalingam C <ramalingam.c@intel.com> wrote:
> At BXT DSI, PIPE registers are inactive. So we can't get the
> PIPE's mode parameters from them. The possible option is
> retriving them from the PORT registers.
>
> The required changes are added for BXT in intel_dsi_get_config
> (encoder->get_config).
>
> v2: Addressed the Jani's comments
>     -removed the redundant call to encoder->get_config
>     -read bpp from port register
>     -removed retrival of src_size from encoder->get_config
>
> v3: pipe_config->pipe_bpp is fixed
>     Jani's review comments addressed:
> 	Few horizontal timing parameters dropped from the patch to make
> 	progress, as there seems to be some disagreement on
> 	best/feasible/possible options.
>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>
> Previously Reviewed at: https://lists.freedesktop.org/archives/intel-gfx/2016-April/091737.html

Both pushed to drm-intel-next-queued, thanks for the patches.

BR,
Jani.


> ---
>  drivers/gpu/drm/i915/intel_dsi.c |   60 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 60 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index a0f374f..a1e0547 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -758,14 +758,74 @@ out_put_power:
>  	return active;
>  }
>  
> +static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
> +				 struct intel_crtc_state *pipe_config)
> +{
> +	struct drm_device *dev = encoder->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct drm_display_mode *adjusted_mode =
> +					&pipe_config->base.adjusted_mode;
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	unsigned int bpp, fmt;
> +	enum port port;
> +	u16 vfp, vsync, vbp;
> +
> +	/*
> +	 * Atleast one port is active as encoder->get_config called only if
> +	 * encoder->get_hw_state() returns true.
> +	 */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
> +			break;
> +	}
> +
> +	fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
> +	pipe_config->pipe_bpp =
> +			mipi_dsi_pixel_format_to_bpp(
> +				pixel_format_from_register_bits(fmt));
> +	bpp = pipe_config->pipe_bpp;
> +
> +	/* In terms of pixels */
> +	adjusted_mode->crtc_hdisplay =
> +				I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
> +	adjusted_mode->crtc_vdisplay =
> +				I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
> +	adjusted_mode->crtc_vtotal =
> +				I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
> +
> +	/*
> +	 * TODO: Retrieve hfp, hsync and hbp. Adjust them for dual link and
> +	 * calculate hsync_start, hsync_end, htotal and hblank_end
> +	 */
> +
> +	/* vertical values are in terms of lines */
> +	vfp = I915_READ(MIPI_VFP_COUNT(port));
> +	vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
> +	vbp = I915_READ(MIPI_VBP_COUNT(port));
> +
> +	adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
> +
> +	adjusted_mode->crtc_vsync_start =
> +				vfp + adjusted_mode->crtc_vdisplay;
> +	adjusted_mode->crtc_vsync_end =
> +				vsync + adjusted_mode->crtc_vsync_start;
> +	adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
> +	adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
> +}
> +
> +
>  static void intel_dsi_get_config(struct intel_encoder *encoder,
>  				 struct intel_crtc_state *pipe_config)
>  {
> +	struct drm_device *dev = encoder->base.dev;
>  	u32 pclk;
>  	DRM_DEBUG_KMS("\n");
>  
>  	pipe_config->has_dsi_encoder = true;
>  
> +	if (IS_BROXTON(dev))
> +		bxt_dsi_get_pipe_config(encoder, pipe_config);
> +
>  	/*
>  	 * DPLL_MD is not used in case of DSI, reading will get some default value
>  	 * set dpll_md = 0

-- 
Jani Nikula, Intel Open Source Technology Center
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