From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH 5/6] drm/i915/bdw: Add support for DRRS to switch RR Date: Wed, 26 Mar 2014 15:06:18 +0200 Message-ID: <878urxgldh.fsf@intel.com> References: <1394169478-26438-1-git-send-email-vandana.kannan@intel.com> <1394169478-26438-6-git-send-email-vandana.kannan@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id DBE8C6E5CA for ; Wed, 26 Mar 2014 06:08:10 -0700 (PDT) In-Reply-To: <1394169478-26438-6-git-send-email-vandana.kannan@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Vandana Kannan , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org The last two patches seem okay, but let's get back to them once the beginning of the series is rebased. Thanks, Jani. On Fri, 07 Mar 2014, Vandana Kannan wrote: > For Broadwell, there is one instance of Transcoder MN values per transcoder. > For dynamic switching between multiple refreshr rates, M/N values may be > reprogrammed on the fly. Link N programming triggers update of all data and > link M & N registers and the new M/N values will be used in the next frame > that is output. > > v2: Incorporated Chris's review comments > Changed to check for gen >=8 or gen > 5 before setting M/N registers > > v3: Incorporated Jani's review comments > Re-use cpu_transcoder_set_m_n for BDW. > > Signed-off-by: Vandana Kannan > Signed-off-by: Pradeep Bhat > --- > drivers/gpu/drm/i915/intel_display.c | 2 +- > drivers/gpu/drm/i915/intel_dp.c | 25 +++++++++++++++++++------ > drivers/gpu/drm/i915/intel_drv.h | 2 ++ > 3 files changed, 22 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 86cd603..64ed4e3 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4901,7 +4901,7 @@ static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, > I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); > } > > -static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, > +void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, > struct intel_link_m_n *m_n) > { > struct drm_device *dev = crtc->base.dev; > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 6a91856..a76a58c 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -839,11 +839,15 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) > struct drm_i915_private *dev_priv = dev->dev_private; > enum transcoder transcoder = crtc->config.cpu_transcoder; > > - I915_WRITE(PIPE_DATA_M2(transcoder), > - TU_SIZE(m_n->tu) | m_n->gmch_m); > - I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); > - I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); > - I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); > + if (INTEL_INFO(dev)->gen >= 8) { > + intel_cpu_transcoder_set_m_n(crtc, m_n); > + } else if (INTEL_INFO(dev)->gen > 6) { > + I915_WRITE(PIPE_DATA_M2(transcoder), > + TU_SIZE(m_n->tu) | m_n->gmch_m); > + I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); > + I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); > + I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); > + } > } > > bool > @@ -3763,7 +3767,16 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) > return; > } > > - if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) { > + if (INTEL_INFO(dev)->gen >= 8) { > + switch (index) { > + case DRRS_HIGH_RR: > + intel_dp_set_m2_n2(intel_crtc, &config->dp_m_n); > + break; > + case DRRS_LOW_RR: > + intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2); > + break; > + }; > + } else if (INTEL_INFO(dev)->gen > 6) { > reg = PIPECONF(intel_crtc->config.cpu_transcoder); > val = I915_READ(reg); > if (index > DRRS_HIGH_RR) { > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 7b6dcc0..3d280b0 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -751,6 +751,8 @@ void hsw_enable_ips(struct intel_crtc *crtc); > void hsw_disable_ips(struct intel_crtc *crtc); > void intel_display_set_init_power(struct drm_device *dev, bool enable); > int valleyview_get_vco(struct drm_i915_private *dev_priv); > +void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, > + struct intel_link_m_n *m_n); > > /* intel_dp.c */ > void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center