From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 14/16] drm/i915: Extract skl_plane_{wm,ddb}_reg_val()
Date: Mon, 13 May 2024 23:43:10 +0300 [thread overview]
Message-ID: <87a5kte941.fsf@intel.com> (raw)
In-Reply-To: <20240510152329.24098-15-ville.syrjala@linux.intel.com>
On Fri, 10 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract helpers to calculate the final wm/ddb register
> values for skl+. Will allow me to more cleanly remove the
> register write wrappers for these registers.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c | 29 +++++++++++++-------
> 1 file changed, 19 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 2a2073bf3aca..8a0a26ab8e6a 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2365,21 +2365,23 @@ static int skl_build_pipe_wm(struct intel_atomic_state *state,
> return skl_wm_check_vblank(crtc_state);
> }
>
> +static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
> +{
> + if (!entry->end)
> + return 0;
> +
> + return PLANE_BUF_END(entry->end - 1) |
> + PLANE_BUF_START(entry->start);
> +}
> +
> static void skl_ddb_entry_write(struct drm_i915_private *i915,
> i915_reg_t reg,
> const struct skl_ddb_entry *entry)
> {
> - if (entry->end)
> - intel_de_write_fw(i915, reg,
> - PLANE_BUF_END(entry->end - 1) |
> - PLANE_BUF_START(entry->start));
> - else
> - intel_de_write_fw(i915, reg, 0);
> + intel_de_write_fw(i915, reg, skl_plane_ddb_reg_val(entry));
> }
>
> -static void skl_write_wm_level(struct drm_i915_private *i915,
> - i915_reg_t reg,
> - const struct skl_wm_level *level)
> +static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
> {
> u32 val = 0;
>
> @@ -2390,7 +2392,14 @@ static void skl_write_wm_level(struct drm_i915_private *i915,
> val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks);
> val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
>
> - intel_de_write_fw(i915, reg, val);
> + return val;
> +}
> +
> +static void skl_write_wm_level(struct drm_i915_private *i915,
> + i915_reg_t reg,
> + const struct skl_wm_level *level)
> +{
> + intel_de_write_fw(i915, reg, skl_plane_wm_reg_val(level));
> }
>
> void skl_write_plane_wm(struct intel_plane *plane,
--
Jani Nikula, Intel
next prev parent reply other threads:[~2024-05-13 20:43 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-10 15:23 [PATCH 00/16] drm/i915: skl+ plane register stuff Ville Syrjala
2024-05-10 15:23 ` [PATCH 01/16] drm/i915: Nuke _MMIO_PLANE_GAMC() Ville Syrjala
2024-05-13 9:50 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 02/16] drm/i915: Extract skl_universal_plane_regs.h Ville Syrjala
2024-05-13 10:07 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 03/16] drm/i915: Extract intel_cursor_regs.h Ville Syrjala
2024-05-13 10:10 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 04/16] drm/i915: Move skl+ wm/ddb registers to proper headers Ville Syrjala
2024-05-13 10:13 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 05/16] drm/i915/gvt: Use the proper PLANE_AUX_DIST() define Ville Syrjala
2024-05-13 10:21 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 06/16] drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() define Ville Syrjala
2024-05-13 10:23 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 07/16] drm/i915/gvt: Use the full PLANE_KEY*() defines Ville Syrjala
2024-05-13 10:25 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 08/16] drm/i915/gvt: Use PLANE_CTL and PLANE_SURF defines Ville Syrjala
2024-05-13 10:30 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 09/16] drm/i915: Drop useless PLANE_FOO_3 register defines Ville Syrjala
2024-05-13 10:32 ` Jani Nikula
2024-05-13 16:58 ` [PATCH v2 " Ville Syrjala
2024-05-10 15:23 ` [PATCH 10/16] drm/i915: Shuffle the skl+ plane register definitions Ville Syrjala
2024-05-13 11:28 ` Jani Nikula
2024-05-13 16:13 ` Ville Syrjälä
2024-05-13 16:59 ` [PATCH v2 " Ville Syrjala
2024-05-13 20:30 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 11/16] drm/i915: Use REG_BIT for PLANE_WM bits Ville Syrjala
2024-05-13 10:38 ` Jani Nikula
2024-05-13 16:59 ` [PATCH v2 " Ville Syrjala
2024-05-10 15:23 ` [PATCH 12/16] drm/i915: Drop a few unwanted tabs from skl+ plane reg defines Ville Syrjala
2024-05-13 10:40 ` Jani Nikula
2024-05-13 17:00 ` [PATCH v2 " Ville Syrjala
2024-05-10 15:23 ` [PATCH 13/16] drm/i915: Refactor skl+ plane register offset calculations Ville Syrjala
2024-05-13 17:00 ` [PATCH v2 " Ville Syrjala
2024-05-13 20:41 ` Jani Nikula
2024-05-13 20:43 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 14/16] drm/i915: Extract skl_plane_{wm,ddb}_reg_val() Ville Syrjala
2024-05-13 20:43 ` Jani Nikula [this message]
2024-05-10 15:23 ` [PATCH 15/16] drm/i915: Nuke skl_write_wm_level() and skl_ddb_entry_write() Ville Syrjala
2024-05-13 20:46 ` Jani Nikula
2024-05-10 15:23 ` [PATCH 16/16] drm/i915: Handle SKL+ WM/DDB registers next to all other plane registers Ville Syrjala
2024-05-13 20:52 ` Jani Nikula
2024-05-15 11:17 ` Ville Syrjälä
2024-05-10 16:28 ` ✓ Fi.CI.BAT: success for drm/i915: skl+ plane register stuff Patchwork
2024-05-11 20:02 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-05-13 18:39 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: skl+ plane register stuff (rev6) Patchwork
2024-05-13 18:39 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-05-13 18:55 ` ✓ Fi.CI.BAT: success " Patchwork
2024-05-14 2:01 ` ✗ Fi.CI.IGT: failure " Patchwork
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