From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 85238C32771 for ; Fri, 16 Sep 2022 01:22:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A9D7810EC42; Fri, 16 Sep 2022 01:21:59 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id F2A4510EC42 for ; Fri, 16 Sep 2022 01:21:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663291316; x=1694827316; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=6DYycxnKb+rZPQJzEWYTB/H9kGzEc9LnnO3PtjBFtCw=; b=exg87CNlCBIhI1lOn+W+H8lr+6G6FVAhV7+P5zLwZLP2E0UMp0XzmEWG RxMic1Es/3gyayD+p8F/6u30WigZ5oFxG0LyuEbV9kdni8igWoGbsqsPw cCUh7uImCTFo21YP99EAbl48n0ErztHU1ON1cJ7wsvXcE6c3GPtJeXgrU 2jhPYf4ozVyLnMV6htr1LveYRLKADLtboaywymgQnK7CW9JcsMBSHgIGJ 1nS/Ay429yMuVmtpw6jHzsLJigtvLApSzORKqXkHvus+KtwCXV9uqdWgz DVvDzywTZsE8f+XM18LX1+OAKonzotv0LwamgT57t9EHPlrteZff1h0xZ Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10471"; a="285924216" X-IronPort-AV: E=Sophos;i="5.93,319,1654585200"; d="scan'208";a="285924216" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Sep 2022 18:21:55 -0700 X-IronPort-AV: E=Sophos;i="5.93,319,1654585200"; d="scan'208";a="617500420" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.209.41.22]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Sep 2022 18:21:55 -0700 Date: Thu, 15 Sep 2022 18:21:55 -0700 Message-ID: <87a6703yh8.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Umesh Nerlige Ramappa In-Reply-To: <20220823204155.8178-15-umesh.nerlige.ramappa@intel.com> References: <20220823204155.8178-1-umesh.nerlige.ramappa@intel.com> <20220823204155.8178-15-umesh.nerlige.ramappa@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 14/19] drm/i915/perf: Add Wa_1608133521:dg2 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, 23 Aug 2022 13:41:50 -0700, Umesh Nerlige Ramappa wrote: > > DG2 introduces 64 bit counters and OA reports that have 64 bit values > for fields in the report header - report_id, timestamp, context_id and > gpu ticks. i915 uses report_id, timestamp and context_id to check for > valid reports. > > In some DG2 variants, only the lower dwords for timestamp, report_id and > context_id are accessible. Add workaround for such reports. Once again, if we are productizing A-step or it is going to be in CI upstream, this is: Reviewed-by: Ashutosh Dixit > Signed-off-by: Umesh Nerlige Ramappa > --- > drivers/gpu/drm/i915/i915_perf.c | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > index a28f07923d8f..a858ce57e465 100644 > --- a/drivers/gpu/drm/i915/i915_perf.c > +++ b/drivers/gpu/drm/i915/i915_perf.c > @@ -310,7 +310,7 @@ static u32 i915_oa_max_sample_rate = 100000; > * be used as a mask to align the OA tail pointer. In some of the > * formats, R is used to denote reserved field. > */ > -static const struct i915_oa_format oa_formats[I915_OA_FORMAT_MAX] = { > +static struct i915_oa_format oa_formats[I915_OA_FORMAT_MAX] = { > [I915_OA_FORMAT_A13] = { 0, 64 }, > [I915_OA_FORMAT_A29] = { 1, 128 }, > [I915_OA_FORMAT_A13_B8_C8] = { 2, 128 }, > @@ -4746,6 +4746,13 @@ static void oa_init_supported_formats(struct i915_perf *perf) > /* Wa_16010703925:dg2 */ > clear_bit(I915_OAR_FORMAT_A36u64_B8_C8, perf->format_mask); > } > + > + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) || > + IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_FOREVER)) { > + /* Wa_1608133521:dg2 */ > + oa_formats[I915_OAR_FORMAT_A36u64_B8_C8].header = HDR_32_BIT; > + oa_formats[I915_OA_FORMAT_A38u64_R2u64_B8_C8].header = HDR_32_BIT; > + } > } > > static void i915_perf_init_info(struct drm_i915_private *i915) > -- > 2.25.1 >