[Intel-gfx] [PATCH 1/3] drm/i915: split out PCI config space registers from i915

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* [Intel-gfx] [PATCH 1/3] drm/i915: split out PCI config space registers from i915_reg.h
@ 2022-01-07  9:49 Jani Nikula
  2022-01-07  9:49 ` [Intel-gfx] [PATCH 2/3] drm/i915: move VGA registers to intel_vga.c Jani Nikula
                   ` (6 more replies)
  0 siblings, 7 replies; 12+ messages in thread
From: Jani Nikula @ 2022-01-07  9:49 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

The PCI config space registers don't really belong next to the MMIO
register definitions.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_backlight.c    |  1 +
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  1 +
 drivers/gpu/drm/i915/display/intel_opregion.c |  1 +
 drivers/gpu/drm/i915/display/intel_overlay.c  |  1 +
 drivers/gpu/drm/i915/gt/intel_reset.c         |  1 +
 drivers/gpu/drm/i915/i915_driver.c            |  1 +
 drivers/gpu/drm/i915/i915_reg.h               | 78 -----------------
 drivers/gpu/drm/i915/i915_suspend.c           |  1 +
 drivers/gpu/drm/i915/intel_pci_config.h       | 85 +++++++++++++++++++
 9 files changed, 92 insertions(+), 78 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_pci_config.h

diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index 2db3b792aca6..98f7ea44042f 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -13,6 +13,7 @@
 #include "intel_dp_aux_backlight.h"
 #include "intel_dsi_dcs_backlight.h"
 #include "intel_panel.h"
+#include "intel_pci_config.h"
 
 /**
  * scale - scale values from one range to another
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 249f81a80eb7..1f13398e8ac2 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -31,6 +31,7 @@
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
+#include "intel_pci_config.h"
 #include "intel_pcode.h"
 #include "intel_psr.h"
 #include "vlv_sideband.h"
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index 985790a66a4d..af9d30f56cc1 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -35,6 +35,7 @@
 #include "intel_backlight.h"
 #include "intel_display_types.h"
 #include "intel_opregion.h"
+#include "intel_pci_config.h"
 
 #define OPREGION_HEADER_OFFSET 0
 #define OPREGION_ACPI_OFFSET   0x100
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index 1a376e9a1ff3..991624a1351a 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -38,6 +38,7 @@
 #include "intel_display_types.h"
 #include "intel_frontbuffer.h"
 #include "intel_overlay.h"
+#include "intel_pci_config.h"
 
 /* Limits for overlay size. According to intel doc, the real limits are:
  * Y width: 4095, UV width (planar): 2047, Y height: 2047,
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 7be0002d9d70..a75ef7bf36c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -19,6 +19,7 @@
 #include "intel_gt.h"
 #include "intel_gt_pm.h"
 #include "intel_gt_requests.h"
+#include "intel_pci_config.h"
 #include "intel_reset.h"
 
 #include "uc/intel_guc.h"
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 5f2343389b5e..762bf7e65784 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -86,6 +86,7 @@
 #include "intel_dram.h"
 #include "intel_gvt.h"
 #include "intel_memory_region.h"
+#include "intel_pci_config.h"
 #include "intel_pcode.h"
 #include "intel_pm.h"
 #include "intel_region_ttm.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e20e832162b4..baa0b9e6acb2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -275,84 +275,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _MASKED_BIT_ENABLE(a)	({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
 #define _MASKED_BIT_DISABLE(a)	(_MASKED_FIELD((a), 0))
 
-/* PCI config space */
-
-#define MCHBAR_I915 0x44
-#define MCHBAR_I965 0x48
-#define MCHBAR_SIZE (4 * 4096)
-
-#define DEVEN 0x54
-#define   DEVEN_MCHBAR_EN (1 << 28)
-
-/* BSM in include/drm/i915_drm.h */
-
-#define HPLLCC	0xc0 /* 85x only */
-#define   GC_CLOCK_CONTROL_MASK		(0x7 << 0)
-#define   GC_CLOCK_133_200		(0 << 0)
-#define   GC_CLOCK_100_200		(1 << 0)
-#define   GC_CLOCK_100_133		(2 << 0)
-#define   GC_CLOCK_133_266		(3 << 0)
-#define   GC_CLOCK_133_200_2		(4 << 0)
-#define   GC_CLOCK_133_266_2		(5 << 0)
-#define   GC_CLOCK_166_266		(6 << 0)
-#define   GC_CLOCK_166_250		(7 << 0)
-
-#define I915_GDRST 0xc0 /* PCI config register */
-#define   GRDOM_FULL		(0 << 2)
-#define   GRDOM_RENDER		(1 << 2)
-#define   GRDOM_MEDIA		(3 << 2)
-#define   GRDOM_MASK		(3 << 2)
-#define   GRDOM_RESET_STATUS	(1 << 1)
-#define   GRDOM_RESET_ENABLE	(1 << 0)
-
-/* BSpec only has register offset, PCI device and bit found empirically */
-#define I830_CLOCK_GATE	0xc8 /* device 0 */
-#define   I830_L2_CACHE_CLOCK_GATE_DISABLE	(1 << 2)
-
-#define GCDGMBUS 0xcc
-
-#define GCFGC2	0xda
-#define GCFGC	0xf0 /* 915+ only */
-#define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)
-#define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
-#define   GC_DISPLAY_CLOCK_333_320_MHZ	(4 << 4)
-#define   GC_DISPLAY_CLOCK_267_MHZ_PNV	(0 << 4)
-#define   GC_DISPLAY_CLOCK_333_MHZ_PNV	(1 << 4)
-#define   GC_DISPLAY_CLOCK_444_MHZ_PNV	(2 << 4)
-#define   GC_DISPLAY_CLOCK_200_MHZ_PNV	(5 << 4)
-#define   GC_DISPLAY_CLOCK_133_MHZ_PNV	(6 << 4)
-#define   GC_DISPLAY_CLOCK_167_MHZ_PNV	(7 << 4)
-#define   GC_DISPLAY_CLOCK_MASK		(7 << 4)
-#define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)
-#define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)
-#define   GM45_GC_RENDER_CLOCK_320_MHZ	(9 << 0)
-#define   GM45_GC_RENDER_CLOCK_400_MHZ	(0xb << 0)
-#define   GM45_GC_RENDER_CLOCK_533_MHZ	(0xc << 0)
-#define   I965_GC_RENDER_CLOCK_MASK	(0xf << 0)
-#define   I965_GC_RENDER_CLOCK_267_MHZ	(2 << 0)
-#define   I965_GC_RENDER_CLOCK_333_MHZ	(3 << 0)
-#define   I965_GC_RENDER_CLOCK_444_MHZ	(4 << 0)
-#define   I965_GC_RENDER_CLOCK_533_MHZ	(5 << 0)
-#define   I945_GC_RENDER_CLOCK_MASK	(7 << 0)
-#define   I945_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
-#define   I945_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
-#define   I945_GC_RENDER_CLOCK_250_MHZ	(3 << 0)
-#define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)
-#define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)
-#define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
-#define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
-#define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)
-
-#define ASLE	0xe4
-#define ASLS	0xfc
-
-#define SWSCI	0xe8
-#define   SWSCI_SCISEL	(1 << 15)
-#define   SWSCI_GSSCIE	(1 << 0)
-
-#define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
-
-
 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
 #define  ILK_GRDOM_FULL		(0 << 1)
 #define  ILK_GRDOM_RENDER	(1 << 1)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index f7b55f34dba8..889f5b7dc78e 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -32,6 +32,7 @@
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "i915_suspend.h"
+#include "intel_pci_config.h"
 
 static void intel_save_swf(struct drm_i915_private *dev_priv)
 {
diff --git a/drivers/gpu/drm/i915/intel_pci_config.h b/drivers/gpu/drm/i915/intel_pci_config.h
new file mode 100644
index 000000000000..db35b91d36e0
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_pci_config.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef __INTEL_PCI_CONFIG_H__
+#define __INTEL_PCI_CONFIG_H__
+
+/* BSM in include/drm/i915_drm.h */
+
+#define MCHBAR_I915				0x44
+#define MCHBAR_I965				0x48
+#define   MCHBAR_SIZE				(4 * 4096)
+
+#define DEVEN					0x54
+#define   DEVEN_MCHBAR_EN			(1 << 28)
+
+#define HPLLCC					0xc0 /* 85x only */
+#define   GC_CLOCK_CONTROL_MASK			(0x7 << 0)
+#define   GC_CLOCK_133_200			(0 << 0)
+#define   GC_CLOCK_100_200			(1 << 0)
+#define   GC_CLOCK_100_133			(2 << 0)
+#define   GC_CLOCK_133_266			(3 << 0)
+#define   GC_CLOCK_133_200_2			(4 << 0)
+#define   GC_CLOCK_133_266_2			(5 << 0)
+#define   GC_CLOCK_166_266			(6 << 0)
+#define   GC_CLOCK_166_250			(7 << 0)
+
+#define I915_GDRST				0xc0
+#define   GRDOM_FULL				(0 << 2)
+#define   GRDOM_RENDER				(1 << 2)
+#define   GRDOM_MEDIA				(3 << 2)
+#define   GRDOM_MASK				(3 << 2)
+#define   GRDOM_RESET_STATUS			(1 << 1)
+#define   GRDOM_RESET_ENABLE			(1 << 0)
+
+/* BSpec only has register offset, PCI device and bit found empirically */
+#define I830_CLOCK_GATE				0xc8 /* device 0 */
+#define   I830_L2_CACHE_CLOCK_GATE_DISABLE	(1 << 2)
+
+#define GCDGMBUS				0xcc
+
+#define GCFGC2					0xda
+#define GCFGC					0xf0 /* 915+ only */
+#define   GC_LOW_FREQUENCY_ENABLE		(1 << 7)
+#define   GC_DISPLAY_CLOCK_190_200_MHZ		(0 << 4)
+#define   GC_DISPLAY_CLOCK_333_320_MHZ		(4 << 4)
+#define   GC_DISPLAY_CLOCK_267_MHZ_PNV		(0 << 4)
+#define   GC_DISPLAY_CLOCK_333_MHZ_PNV		(1 << 4)
+#define   GC_DISPLAY_CLOCK_444_MHZ_PNV		(2 << 4)
+#define   GC_DISPLAY_CLOCK_200_MHZ_PNV		(5 << 4)
+#define   GC_DISPLAY_CLOCK_133_MHZ_PNV		(6 << 4)
+#define   GC_DISPLAY_CLOCK_167_MHZ_PNV		(7 << 4)
+#define   GC_DISPLAY_CLOCK_MASK			(7 << 4)
+#define   GM45_GC_RENDER_CLOCK_MASK		(0xf << 0)
+#define   GM45_GC_RENDER_CLOCK_266_MHZ		(8 << 0)
+#define   GM45_GC_RENDER_CLOCK_320_MHZ		(9 << 0)
+#define   GM45_GC_RENDER_CLOCK_400_MHZ		(0xb << 0)
+#define   GM45_GC_RENDER_CLOCK_533_MHZ		(0xc << 0)
+#define   I965_GC_RENDER_CLOCK_MASK		(0xf << 0)
+#define   I965_GC_RENDER_CLOCK_267_MHZ		(2 << 0)
+#define   I965_GC_RENDER_CLOCK_333_MHZ		(3 << 0)
+#define   I965_GC_RENDER_CLOCK_444_MHZ		(4 << 0)
+#define   I965_GC_RENDER_CLOCK_533_MHZ		(5 << 0)
+#define   I945_GC_RENDER_CLOCK_MASK		(7 << 0)
+#define   I945_GC_RENDER_CLOCK_166_MHZ		(0 << 0)
+#define   I945_GC_RENDER_CLOCK_200_MHZ		(1 << 0)
+#define   I945_GC_RENDER_CLOCK_250_MHZ		(3 << 0)
+#define   I945_GC_RENDER_CLOCK_400_MHZ		(5 << 0)
+#define   I915_GC_RENDER_CLOCK_MASK		(7 << 0)
+#define   I915_GC_RENDER_CLOCK_166_MHZ		(0 << 0)
+#define   I915_GC_RENDER_CLOCK_200_MHZ		(1 << 0)
+#define   I915_GC_RENDER_CLOCK_333_MHZ		(4 << 0)
+
+#define ASLE					0xe4
+#define ASLS					0xfc
+
+#define SWSCI					0xe8
+#define   SWSCI_SCISEL				(1 << 15)
+#define   SWSCI_GSSCIE				(1 << 0)
+
+/* legacy/combination backlight modes, also called LBB */
+#define LBPC					0xf4
+
+#endif /* __INTEL_PCI_CONFIG_H__ */
-- 
2.30.2


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [Intel-gfx] [PATCH 2/3] drm/i915: move VGA registers to intel_vga.c
  2022-01-07  9:49 [Intel-gfx] [PATCH 1/3] drm/i915: split out PCI config space registers from i915_reg.h Jani Nikula
@ 2022-01-07  9:49 ` Jani Nikula
  2022-01-07 17:24   ` Matt Roper
  2022-01-07  9:49 ` [Intel-gfx] [PATCH 3/3] drm/i915: split out vlv sideband registers from i915_reg.h Jani Nikula
                   ` (5 subsequent siblings)
  6 siblings, 1 reply; 12+ messages in thread
From: Jani Nikula @ 2022-01-07  9:49 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

The only users of the VGA register macros are in intel_vga.c. Hide the
macros there.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vga.c | 41 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h          | 41 ------------------------
 2 files changed, 41 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c
index fa779f7ea415..5801cd41eb72 100644
--- a/drivers/gpu/drm/i915/display/intel_vga.c
+++ b/drivers/gpu/drm/i915/display/intel_vga.c
@@ -12,6 +12,47 @@
 #include "intel_de.h"
 #include "intel_vga.h"
 
+/* VGA registers */
+#define VGA_ST01_MDA				0x3ba
+#define VGA_ST01_CGA				0x3da
+
+#define VGA_MSR_WRITE				0x3c2
+#define VGA_MSR_READ				0x3cc
+#define   VGA_MSR_MEM_EN			(1 << 1)
+#define   VGA_MSR_CGA_MODE			(1 << 0)
+
+#define VGA_SR_INDEX				0x3c4
+#define   SR01					1
+#define VGA_SR_DATA				0x3c5
+
+#define VGA_AR_INDEX				0x3c0
+#define   VGA_AR_VID_EN (1 << 5)
+#define VGA_AR_DATA_WRITE			0x3c0
+#define VGA_AR_DATA_READ			0x3c1
+
+#define VGA_GR_INDEX				0x3ce
+#define VGA_GR_DATA				0x3cf
+/* GR05 */
+#define   VGA_GR_MEM_READ_MODE_SHIFT		3
+#define   VGA_GR_MEM_READ_MODE_PLANE		1
+/* GR06 */
+#define   VGA_GR_MEM_MODE_MASK			0xc
+#define   VGA_GR_MEM_MODE_SHIFT			2
+#define   VGA_GR_MEM_A0000_AFFFF		0
+#define   VGA_GR_MEM_A0000_BFFFF		1
+#define   VGA_GR_MEM_B0000_B7FFF		2
+#define   VGA_GR_MEM_B0000_BFFFF		3
+
+#define VGA_DACMASK				0x3c6
+#define VGA_DACRX				0x3c7
+#define VGA_DACWX				0x3c8
+#define VGA_DACDATA				0x3c9
+
+#define VGA_CR_INDEX_MDA			0x3b4
+#define VGA_CR_DATA_MDA				0x3b5
+#define VGA_CR_INDEX_CGA			0x3d4
+#define VGA_CR_DATA_CGA				0x3d5
+
 static i915_reg_t intel_vga_cntrl_reg(struct drm_i915_private *i915)
 {
 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index baa0b9e6acb2..7517a2688896 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -460,48 +460,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define GEN6_STOLEN_RESERVED_ENABLE	(1 << 0)
 #define GEN11_STOLEN_RESERVED_ADDR_MASK	(0xFFFFFFFFFFFULL << 20)
 
-/* VGA stuff */
-
-#define VGA_ST01_MDA 0x3ba
-#define VGA_ST01_CGA 0x3da
-
 #define _VGA_MSR_WRITE _MMIO(0x3c2)
-#define VGA_MSR_WRITE 0x3c2
-#define VGA_MSR_READ 0x3cc
-#define   VGA_MSR_MEM_EN (1 << 1)
-#define   VGA_MSR_CGA_MODE (1 << 0)
-
-#define VGA_SR_INDEX 0x3c4
-#define SR01			1
-#define VGA_SR_DATA 0x3c5
-
-#define VGA_AR_INDEX 0x3c0
-#define   VGA_AR_VID_EN (1 << 5)
-#define VGA_AR_DATA_WRITE 0x3c0
-#define VGA_AR_DATA_READ 0x3c1
-
-#define VGA_GR_INDEX 0x3ce
-#define VGA_GR_DATA 0x3cf
-/* GR05 */
-#define   VGA_GR_MEM_READ_MODE_SHIFT 3
-#define     VGA_GR_MEM_READ_MODE_PLANE 1
-/* GR06 */
-#define   VGA_GR_MEM_MODE_MASK 0xc
-#define   VGA_GR_MEM_MODE_SHIFT 2
-#define   VGA_GR_MEM_A0000_AFFFF 0
-#define   VGA_GR_MEM_A0000_BFFFF 1
-#define   VGA_GR_MEM_B0000_B7FFF 2
-#define   VGA_GR_MEM_B0000_BFFFF 3
-
-#define VGA_DACMASK 0x3c6
-#define VGA_DACRX 0x3c7
-#define VGA_DACWX 0x3c8
-#define VGA_DACDATA 0x3c9
-
-#define VGA_CR_INDEX_MDA 0x3b4
-#define VGA_CR_DATA_MDA 0x3b5
-#define VGA_CR_INDEX_CGA 0x3d4
-#define VGA_CR_DATA_CGA 0x3d5
 
 #define MI_PREDICATE_SRC0	_MMIO(0x2400)
 #define MI_PREDICATE_SRC0_UDW	_MMIO(0x2400 + 4)
-- 
2.30.2


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* Re: [Intel-gfx] [PATCH 2/3] drm/i915: move VGA registers to intel_vga.c
  2022-01-07  9:49 ` [Intel-gfx] [PATCH 2/3] drm/i915: move VGA registers to intel_vga.c Jani Nikula
@ 2022-01-07 17:24   ` Matt Roper
  2022-01-10  9:58     ` Jani Nikula
  0 siblings, 1 reply; 12+ messages in thread
From: Matt Roper @ 2022-01-07 17:24 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

On Fri, Jan 07, 2022 at 11:49:50AM +0200, Jani Nikula wrote:
> The only users of the VGA register macros are in intel_vga.c. Hide the
> macros there.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

It looks like only 5 of the ~30 registers here are actually used.  And
I think those could just be pulled from generic definitions in
include/video/vga.h rather than having something in i915?

E.g.,
 * VGA_MSR_WRITE -> VGA_MIS_W
 * VGA_MSR_READ -> VGA_MIS_R
 * VGA_SR_INDEX -> VGA_SEQ_I
 * SR01 -> 1
 * VGA_SR_DATA -> VGA_SEQ_D


Matt

> ---
>  drivers/gpu/drm/i915/display/intel_vga.c | 41 ++++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h          | 41 ------------------------
>  2 files changed, 41 insertions(+), 41 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c
> index fa779f7ea415..5801cd41eb72 100644
> --- a/drivers/gpu/drm/i915/display/intel_vga.c
> +++ b/drivers/gpu/drm/i915/display/intel_vga.c
> @@ -12,6 +12,47 @@
>  #include "intel_de.h"
>  #include "intel_vga.h"
>  
> +/* VGA registers */
> +#define VGA_ST01_MDA				0x3ba
> +#define VGA_ST01_CGA				0x3da
> +
> +#define VGA_MSR_WRITE				0x3c2
> +#define VGA_MSR_READ				0x3cc
> +#define   VGA_MSR_MEM_EN			(1 << 1)
> +#define   VGA_MSR_CGA_MODE			(1 << 0)
> +
> +#define VGA_SR_INDEX				0x3c4
> +#define   SR01					1
> +#define VGA_SR_DATA				0x3c5
> +
> +#define VGA_AR_INDEX				0x3c0
> +#define   VGA_AR_VID_EN (1 << 5)
> +#define VGA_AR_DATA_WRITE			0x3c0
> +#define VGA_AR_DATA_READ			0x3c1
> +
> +#define VGA_GR_INDEX				0x3ce
> +#define VGA_GR_DATA				0x3cf
> +/* GR05 */
> +#define   VGA_GR_MEM_READ_MODE_SHIFT		3
> +#define   VGA_GR_MEM_READ_MODE_PLANE		1
> +/* GR06 */
> +#define   VGA_GR_MEM_MODE_MASK			0xc
> +#define   VGA_GR_MEM_MODE_SHIFT			2
> +#define   VGA_GR_MEM_A0000_AFFFF		0
> +#define   VGA_GR_MEM_A0000_BFFFF		1
> +#define   VGA_GR_MEM_B0000_B7FFF		2
> +#define   VGA_GR_MEM_B0000_BFFFF		3
> +
> +#define VGA_DACMASK				0x3c6
> +#define VGA_DACRX				0x3c7
> +#define VGA_DACWX				0x3c8
> +#define VGA_DACDATA				0x3c9
> +
> +#define VGA_CR_INDEX_MDA			0x3b4
> +#define VGA_CR_DATA_MDA				0x3b5
> +#define VGA_CR_INDEX_CGA			0x3d4
> +#define VGA_CR_DATA_CGA				0x3d5
> +
>  static i915_reg_t intel_vga_cntrl_reg(struct drm_i915_private *i915)
>  {
>  	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index baa0b9e6acb2..7517a2688896 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -460,48 +460,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define GEN6_STOLEN_RESERVED_ENABLE	(1 << 0)
>  #define GEN11_STOLEN_RESERVED_ADDR_MASK	(0xFFFFFFFFFFFULL << 20)
>  
> -/* VGA stuff */
> -
> -#define VGA_ST01_MDA 0x3ba
> -#define VGA_ST01_CGA 0x3da
> -
>  #define _VGA_MSR_WRITE _MMIO(0x3c2)
> -#define VGA_MSR_WRITE 0x3c2
> -#define VGA_MSR_READ 0x3cc
> -#define   VGA_MSR_MEM_EN (1 << 1)
> -#define   VGA_MSR_CGA_MODE (1 << 0)
> -
> -#define VGA_SR_INDEX 0x3c4
> -#define SR01			1
> -#define VGA_SR_DATA 0x3c5
> -
> -#define VGA_AR_INDEX 0x3c0
> -#define   VGA_AR_VID_EN (1 << 5)
> -#define VGA_AR_DATA_WRITE 0x3c0
> -#define VGA_AR_DATA_READ 0x3c1
> -
> -#define VGA_GR_INDEX 0x3ce
> -#define VGA_GR_DATA 0x3cf
> -/* GR05 */
> -#define   VGA_GR_MEM_READ_MODE_SHIFT 3
> -#define     VGA_GR_MEM_READ_MODE_PLANE 1
> -/* GR06 */
> -#define   VGA_GR_MEM_MODE_MASK 0xc
> -#define   VGA_GR_MEM_MODE_SHIFT 2
> -#define   VGA_GR_MEM_A0000_AFFFF 0
> -#define   VGA_GR_MEM_A0000_BFFFF 1
> -#define   VGA_GR_MEM_B0000_B7FFF 2
> -#define   VGA_GR_MEM_B0000_BFFFF 3
> -
> -#define VGA_DACMASK 0x3c6
> -#define VGA_DACRX 0x3c7
> -#define VGA_DACWX 0x3c8
> -#define VGA_DACDATA 0x3c9
> -
> -#define VGA_CR_INDEX_MDA 0x3b4
> -#define VGA_CR_DATA_MDA 0x3b5
> -#define VGA_CR_INDEX_CGA 0x3d4
> -#define VGA_CR_DATA_CGA 0x3d5
>  
>  #define MI_PREDICATE_SRC0	_MMIO(0x2400)
>  #define MI_PREDICATE_SRC0_UDW	_MMIO(0x2400 + 4)
> -- 
> 2.30.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [Intel-gfx] [PATCH 2/3] drm/i915: move VGA registers to intel_vga.c
  2022-01-07 17:24   ` Matt Roper
@ 2022-01-10  9:58     ` Jani Nikula
  0 siblings, 0 replies; 12+ messages in thread
From: Jani Nikula @ 2022-01-10  9:58 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Fri, 07 Jan 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Fri, Jan 07, 2022 at 11:49:50AM +0200, Jani Nikula wrote:
>> The only users of the VGA register macros are in intel_vga.c. Hide the
>> macros there.
>> 
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> It looks like only 5 of the ~30 registers here are actually used.  And
> I think those could just be pulled from generic definitions in
> include/video/vga.h rather than having something in i915?

Good idea, thanks. Fixed in v2.

BR,
Jani.

>
> E.g.,
>  * VGA_MSR_WRITE -> VGA_MIS_W
>  * VGA_MSR_READ -> VGA_MIS_R
>  * VGA_SR_INDEX -> VGA_SEQ_I
>  * SR01 -> 1
>  * VGA_SR_DATA -> VGA_SEQ_D
>
>
> Matt
>
>> ---
>>  drivers/gpu/drm/i915/display/intel_vga.c | 41 ++++++++++++++++++++++++
>>  drivers/gpu/drm/i915/i915_reg.h          | 41 ------------------------
>>  2 files changed, 41 insertions(+), 41 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c
>> index fa779f7ea415..5801cd41eb72 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vga.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vga.c
>> @@ -12,6 +12,47 @@
>>  #include "intel_de.h"
>>  #include "intel_vga.h"
>>  
>> +/* VGA registers */
>> +#define VGA_ST01_MDA				0x3ba
>> +#define VGA_ST01_CGA				0x3da
>> +
>> +#define VGA_MSR_WRITE				0x3c2
>> +#define VGA_MSR_READ				0x3cc
>> +#define   VGA_MSR_MEM_EN			(1 << 1)
>> +#define   VGA_MSR_CGA_MODE			(1 << 0)
>> +
>> +#define VGA_SR_INDEX				0x3c4
>> +#define   SR01					1
>> +#define VGA_SR_DATA				0x3c5
>> +
>> +#define VGA_AR_INDEX				0x3c0
>> +#define   VGA_AR_VID_EN (1 << 5)
>> +#define VGA_AR_DATA_WRITE			0x3c0
>> +#define VGA_AR_DATA_READ			0x3c1
>> +
>> +#define VGA_GR_INDEX				0x3ce
>> +#define VGA_GR_DATA				0x3cf
>> +/* GR05 */
>> +#define   VGA_GR_MEM_READ_MODE_SHIFT		3
>> +#define   VGA_GR_MEM_READ_MODE_PLANE		1
>> +/* GR06 */
>> +#define   VGA_GR_MEM_MODE_MASK			0xc
>> +#define   VGA_GR_MEM_MODE_SHIFT			2
>> +#define   VGA_GR_MEM_A0000_AFFFF		0
>> +#define   VGA_GR_MEM_A0000_BFFFF		1
>> +#define   VGA_GR_MEM_B0000_B7FFF		2
>> +#define   VGA_GR_MEM_B0000_BFFFF		3
>> +
>> +#define VGA_DACMASK				0x3c6
>> +#define VGA_DACRX				0x3c7
>> +#define VGA_DACWX				0x3c8
>> +#define VGA_DACDATA				0x3c9
>> +
>> +#define VGA_CR_INDEX_MDA			0x3b4
>> +#define VGA_CR_DATA_MDA				0x3b5
>> +#define VGA_CR_INDEX_CGA			0x3d4
>> +#define VGA_CR_DATA_CGA				0x3d5
>> +
>>  static i915_reg_t intel_vga_cntrl_reg(struct drm_i915_private *i915)
>>  {
>>  	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index baa0b9e6acb2..7517a2688896 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -460,48 +460,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>>  #define GEN6_STOLEN_RESERVED_ENABLE	(1 << 0)
>>  #define GEN11_STOLEN_RESERVED_ADDR_MASK	(0xFFFFFFFFFFFULL << 20)
>>  
>> -/* VGA stuff */
>> -
>> -#define VGA_ST01_MDA 0x3ba
>> -#define VGA_ST01_CGA 0x3da
>> -
>>  #define _VGA_MSR_WRITE _MMIO(0x3c2)
>> -#define VGA_MSR_WRITE 0x3c2
>> -#define VGA_MSR_READ 0x3cc
>> -#define   VGA_MSR_MEM_EN (1 << 1)
>> -#define   VGA_MSR_CGA_MODE (1 << 0)
>> -
>> -#define VGA_SR_INDEX 0x3c4
>> -#define SR01			1
>> -#define VGA_SR_DATA 0x3c5
>> -
>> -#define VGA_AR_INDEX 0x3c0
>> -#define   VGA_AR_VID_EN (1 << 5)
>> -#define VGA_AR_DATA_WRITE 0x3c0
>> -#define VGA_AR_DATA_READ 0x3c1
>> -
>> -#define VGA_GR_INDEX 0x3ce
>> -#define VGA_GR_DATA 0x3cf
>> -/* GR05 */
>> -#define   VGA_GR_MEM_READ_MODE_SHIFT 3
>> -#define     VGA_GR_MEM_READ_MODE_PLANE 1
>> -/* GR06 */
>> -#define   VGA_GR_MEM_MODE_MASK 0xc
>> -#define   VGA_GR_MEM_MODE_SHIFT 2
>> -#define   VGA_GR_MEM_A0000_AFFFF 0
>> -#define   VGA_GR_MEM_A0000_BFFFF 1
>> -#define   VGA_GR_MEM_B0000_B7FFF 2
>> -#define   VGA_GR_MEM_B0000_BFFFF 3
>> -
>> -#define VGA_DACMASK 0x3c6
>> -#define VGA_DACRX 0x3c7
>> -#define VGA_DACWX 0x3c8
>> -#define VGA_DACDATA 0x3c9
>> -
>> -#define VGA_CR_INDEX_MDA 0x3b4
>> -#define VGA_CR_DATA_MDA 0x3b5
>> -#define VGA_CR_INDEX_CGA 0x3d4
>> -#define VGA_CR_DATA_CGA 0x3d5
>>  
>>  #define MI_PREDICATE_SRC0	_MMIO(0x2400)
>>  #define MI_PREDICATE_SRC0_UDW	_MMIO(0x2400 + 4)
>> -- 
>> 2.30.2
>> 

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 12+ messages in thread

* [Intel-gfx] [PATCH 3/3] drm/i915: split out vlv sideband registers from i915_reg.h
  2022-01-07  9:49 [Intel-gfx] [PATCH 1/3] drm/i915: split out PCI config space registers from i915_reg.h Jani Nikula
  2022-01-07  9:49 ` [Intel-gfx] [PATCH 2/3] drm/i915: move VGA registers to intel_vga.c Jani Nikula
@ 2022-01-07  9:49 ` Jani Nikula
  2022-01-07 17:30   ` Matt Roper
  2022-01-07 10:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: split out PCI config space " Patchwork
                   ` (4 subsequent siblings)
  6 siblings, 1 reply; 12+ messages in thread
From: Jani Nikula @ 2022-01-07  9:49 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

Add a dedicated file vlv_sideband_reg.h for the VLV/CHV sideband
registers. The sideband registers macros are needed by the same files
that need vlv_sideband.h, so include the definitions from there.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 171 ----------------------
 drivers/gpu/drm/i915/vlv_sideband.h     |   2 +
 drivers/gpu/drm/i915/vlv_sideband_reg.h | 180 ++++++++++++++++++++++++
 3 files changed, 182 insertions(+), 171 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/vlv_sideband_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7517a2688896..459105f232d3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1125,177 +1125,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define VLV_IOSF_DATA				_MMIO(VLV_DISPLAY_BASE + 0x2104)
 #define VLV_IOSF_ADDR				_MMIO(VLV_DISPLAY_BASE + 0x2108)
 
-/* See configdb bunit SB addr map */
-#define BUNIT_REG_BISOC				0x11
-
-/* PUNIT_REG_*SSPM0 */
-#define   _SSPM0_SSC(val)			((val) << 0)
-#define   SSPM0_SSC_MASK			_SSPM0_SSC(0x3)
-#define   SSPM0_SSC_PWR_ON			_SSPM0_SSC(0x0)
-#define   SSPM0_SSC_CLK_GATE			_SSPM0_SSC(0x1)
-#define   SSPM0_SSC_RESET			_SSPM0_SSC(0x2)
-#define   SSPM0_SSC_PWR_GATE			_SSPM0_SSC(0x3)
-#define   _SSPM0_SSS(val)			((val) << 24)
-#define   SSPM0_SSS_MASK			_SSPM0_SSS(0x3)
-#define   SSPM0_SSS_PWR_ON			_SSPM0_SSS(0x0)
-#define   SSPM0_SSS_CLK_GATE			_SSPM0_SSS(0x1)
-#define   SSPM0_SSS_RESET			_SSPM0_SSS(0x2)
-#define   SSPM0_SSS_PWR_GATE			_SSPM0_SSS(0x3)
-
-/* PUNIT_REG_*SSPM1 */
-#define   SSPM1_FREQSTAT_SHIFT			24
-#define   SSPM1_FREQSTAT_MASK			(0x1f << SSPM1_FREQSTAT_SHIFT)
-#define   SSPM1_FREQGUAR_SHIFT			8
-#define   SSPM1_FREQGUAR_MASK			(0x1f << SSPM1_FREQGUAR_SHIFT)
-#define   SSPM1_FREQ_SHIFT			0
-#define   SSPM1_FREQ_MASK			(0x1f << SSPM1_FREQ_SHIFT)
-
-#define PUNIT_REG_VEDSSPM0			0x32
-#define PUNIT_REG_VEDSSPM1			0x33
-
-#define PUNIT_REG_DSPSSPM			0x36
-#define   DSPFREQSTAT_SHIFT_CHV			24
-#define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
-#define   DSPFREQGUAR_SHIFT_CHV			8
-#define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
-#define   DSPFREQSTAT_SHIFT			30
-#define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
-#define   DSPFREQGUAR_SHIFT			14
-#define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
-#define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
-#define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
-#define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
-#define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
-#define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
-#define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
-#define   DP_SSC_CLK_GATE(pipe)			_DP_SSC(0x1, (pipe))
-#define   DP_SSC_RESET(pipe)			_DP_SSC(0x2, (pipe))
-#define   DP_SSC_PWR_GATE(pipe)			_DP_SSC(0x3, (pipe))
-#define   _DP_SSS(val, pipe)			((val) << (2 * (pipe) + 16))
-#define   DP_SSS_MASK(pipe)			_DP_SSS(0x3, (pipe))
-#define   DP_SSS_PWR_ON(pipe)			_DP_SSS(0x0, (pipe))
-#define   DP_SSS_CLK_GATE(pipe)			_DP_SSS(0x1, (pipe))
-#define   DP_SSS_RESET(pipe)			_DP_SSS(0x2, (pipe))
-#define   DP_SSS_PWR_GATE(pipe)			_DP_SSS(0x3, (pipe))
-
-#define PUNIT_REG_ISPSSPM0			0x39
-#define PUNIT_REG_ISPSSPM1			0x3a
-
-#define PUNIT_REG_PWRGT_CTRL			0x60
-#define PUNIT_REG_PWRGT_STATUS			0x61
-#define   PUNIT_PWRGT_MASK(pw_idx)		(3 << ((pw_idx) * 2))
-#define   PUNIT_PWRGT_PWR_ON(pw_idx)		(0 << ((pw_idx) * 2))
-#define   PUNIT_PWRGT_CLK_GATE(pw_idx)		(1 << ((pw_idx) * 2))
-#define   PUNIT_PWRGT_RESET(pw_idx)		(2 << ((pw_idx) * 2))
-#define   PUNIT_PWRGT_PWR_GATE(pw_idx)		(3 << ((pw_idx) * 2))
-
-#define PUNIT_PWGT_IDX_RENDER			0
-#define PUNIT_PWGT_IDX_MEDIA			1
-#define PUNIT_PWGT_IDX_DISP2D			3
-#define PUNIT_PWGT_IDX_DPIO_CMN_BC		5
-#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01	6
-#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23	7
-#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01	8
-#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23	9
-#define PUNIT_PWGT_IDX_DPIO_RX0			10
-#define PUNIT_PWGT_IDX_DPIO_RX1			11
-#define PUNIT_PWGT_IDX_DPIO_CMN_D		12
-
-#define PUNIT_REG_GPU_LFM			0xd3
-#define PUNIT_REG_GPU_FREQ_REQ			0xd4
-#define PUNIT_REG_GPU_FREQ_STS			0xd8
-#define   GPLLENABLE				(1 << 4)
-#define   GENFREQSTATUS				(1 << 0)
-#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
-#define PUNIT_REG_CZ_TIMESTAMP			0xce
-
-#define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
-#define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
-
-#define FB_GFX_FMAX_AT_VMAX_FUSE		0x136
-#define FB_GFX_FREQ_FUSE_MASK			0xff
-#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT	24
-#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT	16
-#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT	8
-
-#define FB_GFX_FMIN_AT_VMIN_FUSE		0x137
-#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT		8
-
-#define PUNIT_REG_DDR_SETUP2			0x139
-#define   FORCE_DDR_FREQ_REQ_ACK		(1 << 8)
-#define   FORCE_DDR_LOW_FREQ			(1 << 1)
-#define   FORCE_DDR_HIGH_FREQ			(1 << 0)
-
-#define PUNIT_GPU_STATUS_REG			0xdb
-#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT	16
-#define PUNIT_GPU_STATUS_MAX_FREQ_MASK		0xff
-#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT	8
-#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK	0xff
-
-#define PUNIT_GPU_DUTYCYCLE_REG		0xdf
-#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT	8
-#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK	0xff
-
-#define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
-#define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
-#define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8
-#define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT	11
-#define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK	0x0007f800
-#define IOSF_NC_FB_GFX_FMAX_FUSE_HI		0x34
-#define   FB_FMAX_VMIN_FREQ_HI_MASK		0x00000007
-#define IOSF_NC_FB_GFX_FMAX_FUSE_LO		0x30
-#define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27
-#define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000
-
-#define VLV_TURBO_SOC_OVERRIDE		0x04
-#define   VLV_OVERRIDE_EN		1
-#define   VLV_SOC_TDP_EN		(1 << 1)
-#define   VLV_BIAS_CPU_125_SOC_875	(6 << 2)
-#define   CHV_BIAS_CPU_50_SOC_50	(3 << 2)
-
-/* vlv2 north clock has */
-#define CCK_FUSE_REG				0x8
-#define  CCK_FUSE_HPLL_FREQ_MASK		0x3
-#define CCK_REG_DSI_PLL_FUSE			0x44
-#define CCK_REG_DSI_PLL_CONTROL			0x48
-#define  DSI_PLL_VCO_EN				(1 << 31)
-#define  DSI_PLL_LDO_GATE			(1 << 30)
-#define  DSI_PLL_P1_POST_DIV_SHIFT		17
-#define  DSI_PLL_P1_POST_DIV_MASK		(0x1ff << 17)
-#define  DSI_PLL_P2_MUX_DSI0_DIV2		(1 << 13)
-#define  DSI_PLL_P3_MUX_DSI1_DIV2		(1 << 12)
-#define  DSI_PLL_MUX_MASK			(3 << 9)
-#define  DSI_PLL_MUX_DSI0_DSIPLL		(0 << 10)
-#define  DSI_PLL_MUX_DSI0_CCK			(1 << 10)
-#define  DSI_PLL_MUX_DSI1_DSIPLL		(0 << 9)
-#define  DSI_PLL_MUX_DSI1_CCK			(1 << 9)
-#define  DSI_PLL_CLK_GATE_MASK			(0xf << 5)
-#define  DSI_PLL_CLK_GATE_DSI0_DSIPLL		(1 << 8)
-#define  DSI_PLL_CLK_GATE_DSI1_DSIPLL		(1 << 7)
-#define  DSI_PLL_CLK_GATE_DSI0_CCK		(1 << 6)
-#define  DSI_PLL_CLK_GATE_DSI1_CCK		(1 << 5)
-#define  DSI_PLL_LOCK				(1 << 0)
-#define CCK_REG_DSI_PLL_DIVIDER			0x4c
-#define  DSI_PLL_LFSR				(1 << 31)
-#define  DSI_PLL_FRACTION_EN			(1 << 30)
-#define  DSI_PLL_FRAC_COUNTER_SHIFT		27
-#define  DSI_PLL_FRAC_COUNTER_MASK		(7 << 27)
-#define  DSI_PLL_USYNC_CNT_SHIFT		18
-#define  DSI_PLL_USYNC_CNT_MASK			(0x1ff << 18)
-#define  DSI_PLL_N1_DIV_SHIFT			16
-#define  DSI_PLL_N1_DIV_MASK			(3 << 16)
-#define  DSI_PLL_M1_DIV_SHIFT			0
-#define  DSI_PLL_M1_DIV_MASK			(0x1ff << 0)
-#define CCK_CZ_CLOCK_CONTROL			0x62
-#define CCK_GPLL_CLOCK_CONTROL			0x67
-#define CCK_DISPLAY_CLOCK_CONTROL		0x6b
-#define CCK_DISPLAY_REF_CLOCK_CONTROL		0x6c
-#define  CCK_TRUNK_FORCE_ON			(1 << 17)
-#define  CCK_TRUNK_FORCE_OFF			(1 << 16)
-#define  CCK_FREQUENCY_STATUS			(0x1f << 8)
-#define  CCK_FREQUENCY_STATUS_SHIFT		8
-#define  CCK_FREQUENCY_VALUES			(0x1f << 0)
-
 /* DPIO registers */
 #define DPIO_DEVFN			0
 
diff --git a/drivers/gpu/drm/i915/vlv_sideband.h b/drivers/gpu/drm/i915/vlv_sideband.h
index d7732f612e7f..9ce283d96b80 100644
--- a/drivers/gpu/drm/i915/vlv_sideband.h
+++ b/drivers/gpu/drm/i915/vlv_sideband.h
@@ -9,6 +9,8 @@
 #include <linux/bitops.h>
 #include <linux/types.h>
 
+#include "vlv_sideband_reg.h"
+
 enum pipe;
 struct drm_i915_private;
 
diff --git a/drivers/gpu/drm/i915/vlv_sideband_reg.h b/drivers/gpu/drm/i915/vlv_sideband_reg.h
new file mode 100644
index 000000000000..ae163881d9c4
--- /dev/null
+++ b/drivers/gpu/drm/i915/vlv_sideband_reg.h
@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef _VLV_SIDEBAND_REG_H_
+#define _VLV_SIDEBAND_REG_H_
+
+/* See configdb bunit SB addr map */
+#define BUNIT_REG_BISOC				0x11
+
+/* PUNIT_REG_*SSPM0 */
+#define   _SSPM0_SSC(val)			((val) << 0)
+#define   SSPM0_SSC_MASK			_SSPM0_SSC(0x3)
+#define   SSPM0_SSC_PWR_ON			_SSPM0_SSC(0x0)
+#define   SSPM0_SSC_CLK_GATE			_SSPM0_SSC(0x1)
+#define   SSPM0_SSC_RESET			_SSPM0_SSC(0x2)
+#define   SSPM0_SSC_PWR_GATE			_SSPM0_SSC(0x3)
+#define   _SSPM0_SSS(val)			((val) << 24)
+#define   SSPM0_SSS_MASK			_SSPM0_SSS(0x3)
+#define   SSPM0_SSS_PWR_ON			_SSPM0_SSS(0x0)
+#define   SSPM0_SSS_CLK_GATE			_SSPM0_SSS(0x1)
+#define   SSPM0_SSS_RESET			_SSPM0_SSS(0x2)
+#define   SSPM0_SSS_PWR_GATE			_SSPM0_SSS(0x3)
+
+/* PUNIT_REG_*SSPM1 */
+#define   SSPM1_FREQSTAT_SHIFT			24
+#define   SSPM1_FREQSTAT_MASK			(0x1f << SSPM1_FREQSTAT_SHIFT)
+#define   SSPM1_FREQGUAR_SHIFT			8
+#define   SSPM1_FREQGUAR_MASK			(0x1f << SSPM1_FREQGUAR_SHIFT)
+#define   SSPM1_FREQ_SHIFT			0
+#define   SSPM1_FREQ_MASK			(0x1f << SSPM1_FREQ_SHIFT)
+
+#define PUNIT_REG_VEDSSPM0			0x32
+#define PUNIT_REG_VEDSSPM1			0x33
+
+#define PUNIT_REG_DSPSSPM			0x36
+#define   DSPFREQSTAT_SHIFT_CHV			24
+#define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
+#define   DSPFREQGUAR_SHIFT_CHV			8
+#define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
+#define   DSPFREQSTAT_SHIFT			30
+#define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
+#define   DSPFREQGUAR_SHIFT			14
+#define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
+#define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
+#define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
+#define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
+#define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
+#define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
+#define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
+#define   DP_SSC_CLK_GATE(pipe)			_DP_SSC(0x1, (pipe))
+#define   DP_SSC_RESET(pipe)			_DP_SSC(0x2, (pipe))
+#define   DP_SSC_PWR_GATE(pipe)			_DP_SSC(0x3, (pipe))
+#define   _DP_SSS(val, pipe)			((val) << (2 * (pipe) + 16))
+#define   DP_SSS_MASK(pipe)			_DP_SSS(0x3, (pipe))
+#define   DP_SSS_PWR_ON(pipe)			_DP_SSS(0x0, (pipe))
+#define   DP_SSS_CLK_GATE(pipe)			_DP_SSS(0x1, (pipe))
+#define   DP_SSS_RESET(pipe)			_DP_SSS(0x2, (pipe))
+#define   DP_SSS_PWR_GATE(pipe)			_DP_SSS(0x3, (pipe))
+
+#define PUNIT_REG_ISPSSPM0			0x39
+#define PUNIT_REG_ISPSSPM1			0x3a
+
+#define PUNIT_REG_PWRGT_CTRL			0x60
+#define PUNIT_REG_PWRGT_STATUS			0x61
+#define   PUNIT_PWRGT_MASK(pw_idx)		(3 << ((pw_idx) * 2))
+#define   PUNIT_PWRGT_PWR_ON(pw_idx)		(0 << ((pw_idx) * 2))
+#define   PUNIT_PWRGT_CLK_GATE(pw_idx)		(1 << ((pw_idx) * 2))
+#define   PUNIT_PWRGT_RESET(pw_idx)		(2 << ((pw_idx) * 2))
+#define   PUNIT_PWRGT_PWR_GATE(pw_idx)		(3 << ((pw_idx) * 2))
+
+#define PUNIT_PWGT_IDX_RENDER			0
+#define PUNIT_PWGT_IDX_MEDIA			1
+#define PUNIT_PWGT_IDX_DISP2D			3
+#define PUNIT_PWGT_IDX_DPIO_CMN_BC		5
+#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01	6
+#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23	7
+#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01	8
+#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23	9
+#define PUNIT_PWGT_IDX_DPIO_RX0			10
+#define PUNIT_PWGT_IDX_DPIO_RX1			11
+#define PUNIT_PWGT_IDX_DPIO_CMN_D		12
+
+#define PUNIT_REG_GPU_LFM			0xd3
+#define PUNIT_REG_GPU_FREQ_REQ			0xd4
+#define PUNIT_REG_GPU_FREQ_STS			0xd8
+#define   GPLLENABLE				(1 << 4)
+#define   GENFREQSTATUS				(1 << 0)
+#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
+#define PUNIT_REG_CZ_TIMESTAMP			0xce
+
+#define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
+#define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
+
+#define FB_GFX_FMAX_AT_VMAX_FUSE		0x136
+#define FB_GFX_FREQ_FUSE_MASK			0xff
+#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT	24
+#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT	16
+#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT	8
+
+#define FB_GFX_FMIN_AT_VMIN_FUSE		0x137
+#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT		8
+
+#define PUNIT_REG_DDR_SETUP2			0x139
+#define   FORCE_DDR_FREQ_REQ_ACK		(1 << 8)
+#define   FORCE_DDR_LOW_FREQ			(1 << 1)
+#define   FORCE_DDR_HIGH_FREQ			(1 << 0)
+
+#define PUNIT_GPU_STATUS_REG			0xdb
+#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT	16
+#define PUNIT_GPU_STATUS_MAX_FREQ_MASK		0xff
+#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT	8
+#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK	0xff
+
+#define PUNIT_GPU_DUTYCYCLE_REG		0xdf
+#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT	8
+#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK	0xff
+
+#define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
+#define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
+#define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8
+#define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT	11
+#define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK	0x0007f800
+#define IOSF_NC_FB_GFX_FMAX_FUSE_HI		0x34
+#define   FB_FMAX_VMIN_FREQ_HI_MASK		0x00000007
+#define IOSF_NC_FB_GFX_FMAX_FUSE_LO		0x30
+#define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27
+#define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000
+
+#define VLV_TURBO_SOC_OVERRIDE		0x04
+#define   VLV_OVERRIDE_EN		1
+#define   VLV_SOC_TDP_EN		(1 << 1)
+#define   VLV_BIAS_CPU_125_SOC_875	(6 << 2)
+#define   CHV_BIAS_CPU_50_SOC_50	(3 << 2)
+
+/* vlv2 north clock has */
+#define CCK_FUSE_REG				0x8
+#define  CCK_FUSE_HPLL_FREQ_MASK		0x3
+#define CCK_REG_DSI_PLL_FUSE			0x44
+#define CCK_REG_DSI_PLL_CONTROL			0x48
+#define  DSI_PLL_VCO_EN				(1 << 31)
+#define  DSI_PLL_LDO_GATE			(1 << 30)
+#define  DSI_PLL_P1_POST_DIV_SHIFT		17
+#define  DSI_PLL_P1_POST_DIV_MASK		(0x1ff << 17)
+#define  DSI_PLL_P2_MUX_DSI0_DIV2		(1 << 13)
+#define  DSI_PLL_P3_MUX_DSI1_DIV2		(1 << 12)
+#define  DSI_PLL_MUX_MASK			(3 << 9)
+#define  DSI_PLL_MUX_DSI0_DSIPLL		(0 << 10)
+#define  DSI_PLL_MUX_DSI0_CCK			(1 << 10)
+#define  DSI_PLL_MUX_DSI1_DSIPLL		(0 << 9)
+#define  DSI_PLL_MUX_DSI1_CCK			(1 << 9)
+#define  DSI_PLL_CLK_GATE_MASK			(0xf << 5)
+#define  DSI_PLL_CLK_GATE_DSI0_DSIPLL		(1 << 8)
+#define  DSI_PLL_CLK_GATE_DSI1_DSIPLL		(1 << 7)
+#define  DSI_PLL_CLK_GATE_DSI0_CCK		(1 << 6)
+#define  DSI_PLL_CLK_GATE_DSI1_CCK		(1 << 5)
+#define  DSI_PLL_LOCK				(1 << 0)
+#define CCK_REG_DSI_PLL_DIVIDER			0x4c
+#define  DSI_PLL_LFSR				(1 << 31)
+#define  DSI_PLL_FRACTION_EN			(1 << 30)
+#define  DSI_PLL_FRAC_COUNTER_SHIFT		27
+#define  DSI_PLL_FRAC_COUNTER_MASK		(7 << 27)
+#define  DSI_PLL_USYNC_CNT_SHIFT		18
+#define  DSI_PLL_USYNC_CNT_MASK			(0x1ff << 18)
+#define  DSI_PLL_N1_DIV_SHIFT			16
+#define  DSI_PLL_N1_DIV_MASK			(3 << 16)
+#define  DSI_PLL_M1_DIV_SHIFT			0
+#define  DSI_PLL_M1_DIV_MASK			(0x1ff << 0)
+#define CCK_CZ_CLOCK_CONTROL			0x62
+#define CCK_GPLL_CLOCK_CONTROL			0x67
+#define CCK_DISPLAY_CLOCK_CONTROL		0x6b
+#define CCK_DISPLAY_REF_CLOCK_CONTROL		0x6c
+#define  CCK_TRUNK_FORCE_ON			(1 << 17)
+#define  CCK_TRUNK_FORCE_OFF			(1 << 16)
+#define  CCK_FREQUENCY_STATUS			(0x1f << 8)
+#define  CCK_FREQUENCY_STATUS_SHIFT		8
+#define  CCK_FREQUENCY_VALUES			(0x1f << 0)
+
+#endif /* _VLV_SIDEBAND_REG_H_ */
-- 
2.30.2


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* Re: [Intel-gfx] [PATCH 3/3] drm/i915: split out vlv sideband registers from i915_reg.h
  2022-01-07  9:49 ` [Intel-gfx] [PATCH 3/3] drm/i915: split out vlv sideband registers from i915_reg.h Jani Nikula
@ 2022-01-07 17:30   ` Matt Roper
  0 siblings, 0 replies; 12+ messages in thread
From: Matt Roper @ 2022-01-07 17:30 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

On Fri, Jan 07, 2022 at 11:49:51AM +0200, Jani Nikula wrote:
> Add a dedicated file vlv_sideband_reg.h for the VLV/CHV sideband
> registers. The sideband registers macros are needed by the same files
> that need vlv_sideband.h, so include the definitions from there.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

This one also needs 2022 on the copyright line, but otherwise,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h         | 171 ----------------------
>  drivers/gpu/drm/i915/vlv_sideband.h     |   2 +
>  drivers/gpu/drm/i915/vlv_sideband_reg.h | 180 ++++++++++++++++++++++++
>  3 files changed, 182 insertions(+), 171 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/vlv_sideband_reg.h
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7517a2688896..459105f232d3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1125,177 +1125,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define VLV_IOSF_DATA				_MMIO(VLV_DISPLAY_BASE + 0x2104)
>  #define VLV_IOSF_ADDR				_MMIO(VLV_DISPLAY_BASE + 0x2108)
>  
> -/* See configdb bunit SB addr map */
> -#define BUNIT_REG_BISOC				0x11
> -
> -/* PUNIT_REG_*SSPM0 */
> -#define   _SSPM0_SSC(val)			((val) << 0)
> -#define   SSPM0_SSC_MASK			_SSPM0_SSC(0x3)
> -#define   SSPM0_SSC_PWR_ON			_SSPM0_SSC(0x0)
> -#define   SSPM0_SSC_CLK_GATE			_SSPM0_SSC(0x1)
> -#define   SSPM0_SSC_RESET			_SSPM0_SSC(0x2)
> -#define   SSPM0_SSC_PWR_GATE			_SSPM0_SSC(0x3)
> -#define   _SSPM0_SSS(val)			((val) << 24)
> -#define   SSPM0_SSS_MASK			_SSPM0_SSS(0x3)
> -#define   SSPM0_SSS_PWR_ON			_SSPM0_SSS(0x0)
> -#define   SSPM0_SSS_CLK_GATE			_SSPM0_SSS(0x1)
> -#define   SSPM0_SSS_RESET			_SSPM0_SSS(0x2)
> -#define   SSPM0_SSS_PWR_GATE			_SSPM0_SSS(0x3)
> -
> -/* PUNIT_REG_*SSPM1 */
> -#define   SSPM1_FREQSTAT_SHIFT			24
> -#define   SSPM1_FREQSTAT_MASK			(0x1f << SSPM1_FREQSTAT_SHIFT)
> -#define   SSPM1_FREQGUAR_SHIFT			8
> -#define   SSPM1_FREQGUAR_MASK			(0x1f << SSPM1_FREQGUAR_SHIFT)
> -#define   SSPM1_FREQ_SHIFT			0
> -#define   SSPM1_FREQ_MASK			(0x1f << SSPM1_FREQ_SHIFT)
> -
> -#define PUNIT_REG_VEDSSPM0			0x32
> -#define PUNIT_REG_VEDSSPM1			0x33
> -
> -#define PUNIT_REG_DSPSSPM			0x36
> -#define   DSPFREQSTAT_SHIFT_CHV			24
> -#define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
> -#define   DSPFREQGUAR_SHIFT_CHV			8
> -#define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
> -#define   DSPFREQSTAT_SHIFT			30
> -#define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
> -#define   DSPFREQGUAR_SHIFT			14
> -#define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
> -#define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
> -#define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
> -#define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
> -#define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
> -#define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
> -#define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
> -#define   DP_SSC_CLK_GATE(pipe)			_DP_SSC(0x1, (pipe))
> -#define   DP_SSC_RESET(pipe)			_DP_SSC(0x2, (pipe))
> -#define   DP_SSC_PWR_GATE(pipe)			_DP_SSC(0x3, (pipe))
> -#define   _DP_SSS(val, pipe)			((val) << (2 * (pipe) + 16))
> -#define   DP_SSS_MASK(pipe)			_DP_SSS(0x3, (pipe))
> -#define   DP_SSS_PWR_ON(pipe)			_DP_SSS(0x0, (pipe))
> -#define   DP_SSS_CLK_GATE(pipe)			_DP_SSS(0x1, (pipe))
> -#define   DP_SSS_RESET(pipe)			_DP_SSS(0x2, (pipe))
> -#define   DP_SSS_PWR_GATE(pipe)			_DP_SSS(0x3, (pipe))
> -
> -#define PUNIT_REG_ISPSSPM0			0x39
> -#define PUNIT_REG_ISPSSPM1			0x3a
> -
> -#define PUNIT_REG_PWRGT_CTRL			0x60
> -#define PUNIT_REG_PWRGT_STATUS			0x61
> -#define   PUNIT_PWRGT_MASK(pw_idx)		(3 << ((pw_idx) * 2))
> -#define   PUNIT_PWRGT_PWR_ON(pw_idx)		(0 << ((pw_idx) * 2))
> -#define   PUNIT_PWRGT_CLK_GATE(pw_idx)		(1 << ((pw_idx) * 2))
> -#define   PUNIT_PWRGT_RESET(pw_idx)		(2 << ((pw_idx) * 2))
> -#define   PUNIT_PWRGT_PWR_GATE(pw_idx)		(3 << ((pw_idx) * 2))
> -
> -#define PUNIT_PWGT_IDX_RENDER			0
> -#define PUNIT_PWGT_IDX_MEDIA			1
> -#define PUNIT_PWGT_IDX_DISP2D			3
> -#define PUNIT_PWGT_IDX_DPIO_CMN_BC		5
> -#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01	6
> -#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23	7
> -#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01	8
> -#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23	9
> -#define PUNIT_PWGT_IDX_DPIO_RX0			10
> -#define PUNIT_PWGT_IDX_DPIO_RX1			11
> -#define PUNIT_PWGT_IDX_DPIO_CMN_D		12
> -
> -#define PUNIT_REG_GPU_LFM			0xd3
> -#define PUNIT_REG_GPU_FREQ_REQ			0xd4
> -#define PUNIT_REG_GPU_FREQ_STS			0xd8
> -#define   GPLLENABLE				(1 << 4)
> -#define   GENFREQSTATUS				(1 << 0)
> -#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
> -#define PUNIT_REG_CZ_TIMESTAMP			0xce
> -
> -#define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
> -#define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
> -
> -#define FB_GFX_FMAX_AT_VMAX_FUSE		0x136
> -#define FB_GFX_FREQ_FUSE_MASK			0xff
> -#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT	24
> -#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT	16
> -#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT	8
> -
> -#define FB_GFX_FMIN_AT_VMIN_FUSE		0x137
> -#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT		8
> -
> -#define PUNIT_REG_DDR_SETUP2			0x139
> -#define   FORCE_DDR_FREQ_REQ_ACK		(1 << 8)
> -#define   FORCE_DDR_LOW_FREQ			(1 << 1)
> -#define   FORCE_DDR_HIGH_FREQ			(1 << 0)
> -
> -#define PUNIT_GPU_STATUS_REG			0xdb
> -#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT	16
> -#define PUNIT_GPU_STATUS_MAX_FREQ_MASK		0xff
> -#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT	8
> -#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK	0xff
> -
> -#define PUNIT_GPU_DUTYCYCLE_REG		0xdf
> -#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT	8
> -#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK	0xff
> -
> -#define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
> -#define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
> -#define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8
> -#define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT	11
> -#define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK	0x0007f800
> -#define IOSF_NC_FB_GFX_FMAX_FUSE_HI		0x34
> -#define   FB_FMAX_VMIN_FREQ_HI_MASK		0x00000007
> -#define IOSF_NC_FB_GFX_FMAX_FUSE_LO		0x30
> -#define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27
> -#define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000
> -
> -#define VLV_TURBO_SOC_OVERRIDE		0x04
> -#define   VLV_OVERRIDE_EN		1
> -#define   VLV_SOC_TDP_EN		(1 << 1)
> -#define   VLV_BIAS_CPU_125_SOC_875	(6 << 2)
> -#define   CHV_BIAS_CPU_50_SOC_50	(3 << 2)
> -
> -/* vlv2 north clock has */
> -#define CCK_FUSE_REG				0x8
> -#define  CCK_FUSE_HPLL_FREQ_MASK		0x3
> -#define CCK_REG_DSI_PLL_FUSE			0x44
> -#define CCK_REG_DSI_PLL_CONTROL			0x48
> -#define  DSI_PLL_VCO_EN				(1 << 31)
> -#define  DSI_PLL_LDO_GATE			(1 << 30)
> -#define  DSI_PLL_P1_POST_DIV_SHIFT		17
> -#define  DSI_PLL_P1_POST_DIV_MASK		(0x1ff << 17)
> -#define  DSI_PLL_P2_MUX_DSI0_DIV2		(1 << 13)
> -#define  DSI_PLL_P3_MUX_DSI1_DIV2		(1 << 12)
> -#define  DSI_PLL_MUX_MASK			(3 << 9)
> -#define  DSI_PLL_MUX_DSI0_DSIPLL		(0 << 10)
> -#define  DSI_PLL_MUX_DSI0_CCK			(1 << 10)
> -#define  DSI_PLL_MUX_DSI1_DSIPLL		(0 << 9)
> -#define  DSI_PLL_MUX_DSI1_CCK			(1 << 9)
> -#define  DSI_PLL_CLK_GATE_MASK			(0xf << 5)
> -#define  DSI_PLL_CLK_GATE_DSI0_DSIPLL		(1 << 8)
> -#define  DSI_PLL_CLK_GATE_DSI1_DSIPLL		(1 << 7)
> -#define  DSI_PLL_CLK_GATE_DSI0_CCK		(1 << 6)
> -#define  DSI_PLL_CLK_GATE_DSI1_CCK		(1 << 5)
> -#define  DSI_PLL_LOCK				(1 << 0)
> -#define CCK_REG_DSI_PLL_DIVIDER			0x4c
> -#define  DSI_PLL_LFSR				(1 << 31)
> -#define  DSI_PLL_FRACTION_EN			(1 << 30)
> -#define  DSI_PLL_FRAC_COUNTER_SHIFT		27
> -#define  DSI_PLL_FRAC_COUNTER_MASK		(7 << 27)
> -#define  DSI_PLL_USYNC_CNT_SHIFT		18
> -#define  DSI_PLL_USYNC_CNT_MASK			(0x1ff << 18)
> -#define  DSI_PLL_N1_DIV_SHIFT			16
> -#define  DSI_PLL_N1_DIV_MASK			(3 << 16)
> -#define  DSI_PLL_M1_DIV_SHIFT			0
> -#define  DSI_PLL_M1_DIV_MASK			(0x1ff << 0)
> -#define CCK_CZ_CLOCK_CONTROL			0x62
> -#define CCK_GPLL_CLOCK_CONTROL			0x67
> -#define CCK_DISPLAY_CLOCK_CONTROL		0x6b
> -#define CCK_DISPLAY_REF_CLOCK_CONTROL		0x6c
> -#define  CCK_TRUNK_FORCE_ON			(1 << 17)
> -#define  CCK_TRUNK_FORCE_OFF			(1 << 16)
> -#define  CCK_FREQUENCY_STATUS			(0x1f << 8)
> -#define  CCK_FREQUENCY_STATUS_SHIFT		8
> -#define  CCK_FREQUENCY_VALUES			(0x1f << 0)
> -
>  /* DPIO registers */
>  #define DPIO_DEVFN			0
>  
> diff --git a/drivers/gpu/drm/i915/vlv_sideband.h b/drivers/gpu/drm/i915/vlv_sideband.h
> index d7732f612e7f..9ce283d96b80 100644
> --- a/drivers/gpu/drm/i915/vlv_sideband.h
> +++ b/drivers/gpu/drm/i915/vlv_sideband.h
> @@ -9,6 +9,8 @@
>  #include <linux/bitops.h>
>  #include <linux/types.h>
>  
> +#include "vlv_sideband_reg.h"
> +
>  enum pipe;
>  struct drm_i915_private;
>  
> diff --git a/drivers/gpu/drm/i915/vlv_sideband_reg.h b/drivers/gpu/drm/i915/vlv_sideband_reg.h
> new file mode 100644
> index 000000000000..ae163881d9c4
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/vlv_sideband_reg.h
> @@ -0,0 +1,180 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#ifndef _VLV_SIDEBAND_REG_H_
> +#define _VLV_SIDEBAND_REG_H_
> +
> +/* See configdb bunit SB addr map */
> +#define BUNIT_REG_BISOC				0x11
> +
> +/* PUNIT_REG_*SSPM0 */
> +#define   _SSPM0_SSC(val)			((val) << 0)
> +#define   SSPM0_SSC_MASK			_SSPM0_SSC(0x3)
> +#define   SSPM0_SSC_PWR_ON			_SSPM0_SSC(0x0)
> +#define   SSPM0_SSC_CLK_GATE			_SSPM0_SSC(0x1)
> +#define   SSPM0_SSC_RESET			_SSPM0_SSC(0x2)
> +#define   SSPM0_SSC_PWR_GATE			_SSPM0_SSC(0x3)
> +#define   _SSPM0_SSS(val)			((val) << 24)
> +#define   SSPM0_SSS_MASK			_SSPM0_SSS(0x3)
> +#define   SSPM0_SSS_PWR_ON			_SSPM0_SSS(0x0)
> +#define   SSPM0_SSS_CLK_GATE			_SSPM0_SSS(0x1)
> +#define   SSPM0_SSS_RESET			_SSPM0_SSS(0x2)
> +#define   SSPM0_SSS_PWR_GATE			_SSPM0_SSS(0x3)
> +
> +/* PUNIT_REG_*SSPM1 */
> +#define   SSPM1_FREQSTAT_SHIFT			24
> +#define   SSPM1_FREQSTAT_MASK			(0x1f << SSPM1_FREQSTAT_SHIFT)
> +#define   SSPM1_FREQGUAR_SHIFT			8
> +#define   SSPM1_FREQGUAR_MASK			(0x1f << SSPM1_FREQGUAR_SHIFT)
> +#define   SSPM1_FREQ_SHIFT			0
> +#define   SSPM1_FREQ_MASK			(0x1f << SSPM1_FREQ_SHIFT)
> +
> +#define PUNIT_REG_VEDSSPM0			0x32
> +#define PUNIT_REG_VEDSSPM1			0x33
> +
> +#define PUNIT_REG_DSPSSPM			0x36
> +#define   DSPFREQSTAT_SHIFT_CHV			24
> +#define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
> +#define   DSPFREQGUAR_SHIFT_CHV			8
> +#define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
> +#define   DSPFREQSTAT_SHIFT			30
> +#define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
> +#define   DSPFREQGUAR_SHIFT			14
> +#define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
> +#define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
> +#define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
> +#define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
> +#define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
> +#define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
> +#define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
> +#define   DP_SSC_CLK_GATE(pipe)			_DP_SSC(0x1, (pipe))
> +#define   DP_SSC_RESET(pipe)			_DP_SSC(0x2, (pipe))
> +#define   DP_SSC_PWR_GATE(pipe)			_DP_SSC(0x3, (pipe))
> +#define   _DP_SSS(val, pipe)			((val) << (2 * (pipe) + 16))
> +#define   DP_SSS_MASK(pipe)			_DP_SSS(0x3, (pipe))
> +#define   DP_SSS_PWR_ON(pipe)			_DP_SSS(0x0, (pipe))
> +#define   DP_SSS_CLK_GATE(pipe)			_DP_SSS(0x1, (pipe))
> +#define   DP_SSS_RESET(pipe)			_DP_SSS(0x2, (pipe))
> +#define   DP_SSS_PWR_GATE(pipe)			_DP_SSS(0x3, (pipe))
> +
> +#define PUNIT_REG_ISPSSPM0			0x39
> +#define PUNIT_REG_ISPSSPM1			0x3a
> +
> +#define PUNIT_REG_PWRGT_CTRL			0x60
> +#define PUNIT_REG_PWRGT_STATUS			0x61
> +#define   PUNIT_PWRGT_MASK(pw_idx)		(3 << ((pw_idx) * 2))
> +#define   PUNIT_PWRGT_PWR_ON(pw_idx)		(0 << ((pw_idx) * 2))
> +#define   PUNIT_PWRGT_CLK_GATE(pw_idx)		(1 << ((pw_idx) * 2))
> +#define   PUNIT_PWRGT_RESET(pw_idx)		(2 << ((pw_idx) * 2))
> +#define   PUNIT_PWRGT_PWR_GATE(pw_idx)		(3 << ((pw_idx) * 2))
> +
> +#define PUNIT_PWGT_IDX_RENDER			0
> +#define PUNIT_PWGT_IDX_MEDIA			1
> +#define PUNIT_PWGT_IDX_DISP2D			3
> +#define PUNIT_PWGT_IDX_DPIO_CMN_BC		5
> +#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01	6
> +#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23	7
> +#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01	8
> +#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23	9
> +#define PUNIT_PWGT_IDX_DPIO_RX0			10
> +#define PUNIT_PWGT_IDX_DPIO_RX1			11
> +#define PUNIT_PWGT_IDX_DPIO_CMN_D		12
> +
> +#define PUNIT_REG_GPU_LFM			0xd3
> +#define PUNIT_REG_GPU_FREQ_REQ			0xd4
> +#define PUNIT_REG_GPU_FREQ_STS			0xd8
> +#define   GPLLENABLE				(1 << 4)
> +#define   GENFREQSTATUS				(1 << 0)
> +#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
> +#define PUNIT_REG_CZ_TIMESTAMP			0xce
> +
> +#define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
> +#define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
> +
> +#define FB_GFX_FMAX_AT_VMAX_FUSE		0x136
> +#define FB_GFX_FREQ_FUSE_MASK			0xff
> +#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT	24
> +#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT	16
> +#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT	8
> +
> +#define FB_GFX_FMIN_AT_VMIN_FUSE		0x137
> +#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT		8
> +
> +#define PUNIT_REG_DDR_SETUP2			0x139
> +#define   FORCE_DDR_FREQ_REQ_ACK		(1 << 8)
> +#define   FORCE_DDR_LOW_FREQ			(1 << 1)
> +#define   FORCE_DDR_HIGH_FREQ			(1 << 0)
> +
> +#define PUNIT_GPU_STATUS_REG			0xdb
> +#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT	16
> +#define PUNIT_GPU_STATUS_MAX_FREQ_MASK		0xff
> +#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT	8
> +#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK	0xff
> +
> +#define PUNIT_GPU_DUTYCYCLE_REG		0xdf
> +#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT	8
> +#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK	0xff
> +
> +#define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
> +#define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
> +#define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8
> +#define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT	11
> +#define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK	0x0007f800
> +#define IOSF_NC_FB_GFX_FMAX_FUSE_HI		0x34
> +#define   FB_FMAX_VMIN_FREQ_HI_MASK		0x00000007
> +#define IOSF_NC_FB_GFX_FMAX_FUSE_LO		0x30
> +#define   FB_FMAX_VMIN_FREQ_LO_SHIFT		27
> +#define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000
> +
> +#define VLV_TURBO_SOC_OVERRIDE		0x04
> +#define   VLV_OVERRIDE_EN		1
> +#define   VLV_SOC_TDP_EN		(1 << 1)
> +#define   VLV_BIAS_CPU_125_SOC_875	(6 << 2)
> +#define   CHV_BIAS_CPU_50_SOC_50	(3 << 2)
> +
> +/* vlv2 north clock has */
> +#define CCK_FUSE_REG				0x8
> +#define  CCK_FUSE_HPLL_FREQ_MASK		0x3
> +#define CCK_REG_DSI_PLL_FUSE			0x44
> +#define CCK_REG_DSI_PLL_CONTROL			0x48
> +#define  DSI_PLL_VCO_EN				(1 << 31)
> +#define  DSI_PLL_LDO_GATE			(1 << 30)
> +#define  DSI_PLL_P1_POST_DIV_SHIFT		17
> +#define  DSI_PLL_P1_POST_DIV_MASK		(0x1ff << 17)
> +#define  DSI_PLL_P2_MUX_DSI0_DIV2		(1 << 13)
> +#define  DSI_PLL_P3_MUX_DSI1_DIV2		(1 << 12)
> +#define  DSI_PLL_MUX_MASK			(3 << 9)
> +#define  DSI_PLL_MUX_DSI0_DSIPLL		(0 << 10)
> +#define  DSI_PLL_MUX_DSI0_CCK			(1 << 10)
> +#define  DSI_PLL_MUX_DSI1_DSIPLL		(0 << 9)
> +#define  DSI_PLL_MUX_DSI1_CCK			(1 << 9)
> +#define  DSI_PLL_CLK_GATE_MASK			(0xf << 5)
> +#define  DSI_PLL_CLK_GATE_DSI0_DSIPLL		(1 << 8)
> +#define  DSI_PLL_CLK_GATE_DSI1_DSIPLL		(1 << 7)
> +#define  DSI_PLL_CLK_GATE_DSI0_CCK		(1 << 6)
> +#define  DSI_PLL_CLK_GATE_DSI1_CCK		(1 << 5)
> +#define  DSI_PLL_LOCK				(1 << 0)
> +#define CCK_REG_DSI_PLL_DIVIDER			0x4c
> +#define  DSI_PLL_LFSR				(1 << 31)
> +#define  DSI_PLL_FRACTION_EN			(1 << 30)
> +#define  DSI_PLL_FRAC_COUNTER_SHIFT		27
> +#define  DSI_PLL_FRAC_COUNTER_MASK		(7 << 27)
> +#define  DSI_PLL_USYNC_CNT_SHIFT		18
> +#define  DSI_PLL_USYNC_CNT_MASK			(0x1ff << 18)
> +#define  DSI_PLL_N1_DIV_SHIFT			16
> +#define  DSI_PLL_N1_DIV_MASK			(3 << 16)
> +#define  DSI_PLL_M1_DIV_SHIFT			0
> +#define  DSI_PLL_M1_DIV_MASK			(0x1ff << 0)
> +#define CCK_CZ_CLOCK_CONTROL			0x62
> +#define CCK_GPLL_CLOCK_CONTROL			0x67
> +#define CCK_DISPLAY_CLOCK_CONTROL		0x6b
> +#define CCK_DISPLAY_REF_CLOCK_CONTROL		0x6c
> +#define  CCK_TRUNK_FORCE_ON			(1 << 17)
> +#define  CCK_TRUNK_FORCE_OFF			(1 << 16)
> +#define  CCK_FREQUENCY_STATUS			(0x1f << 8)
> +#define  CCK_FREQUENCY_STATUS_SHIFT		8
> +#define  CCK_FREQUENCY_VALUES			(0x1f << 0)
> +
> +#endif /* _VLV_SIDEBAND_REG_H_ */
> -- 
> 2.30.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

^ permalink raw reply	[flat|nested] 12+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: split out PCI config space registers from i915_reg.h
  2022-01-07  9:49 [Intel-gfx] [PATCH 1/3] drm/i915: split out PCI config space registers from i915_reg.h Jani Nikula
  2022-01-07  9:49 ` [Intel-gfx] [PATCH 2/3] drm/i915: move VGA registers to intel_vga.c Jani Nikula
  2022-01-07  9:49 ` [Intel-gfx] [PATCH 3/3] drm/i915: split out vlv sideband registers from i915_reg.h Jani Nikula
@ 2022-01-07 10:07 ` Patchwork
  2022-01-07 10:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
                   ` (3 subsequent siblings)
  6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2022-01-07 10:07 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/3] drm/i915: split out PCI config space registers from i915_reg.h
URL   : https://patchwork.freedesktop.org/series/98597/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
0eec9f19cbae drm/i915: split out PCI config space registers from i915_reg.h
-:187: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#187: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 218 lines checked
66ca8d122638 drm/i915: move VGA registers to intel_vga.c
48a43a2e5438 drm/i915: split out vlv sideband registers from i915_reg.h
-:209: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#209: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 365 lines checked



^ permalink raw reply	[flat|nested] 12+ messages in thread

* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915: split out PCI config space registers from i915_reg.h
  2022-01-07  9:49 [Intel-gfx] [PATCH 1/3] drm/i915: split out PCI config space registers from i915_reg.h Jani Nikula
                   ` (2 preceding siblings ...)
  2022-01-07 10:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: split out PCI config space " Patchwork
@ 2022-01-07 10:08 ` Patchwork
  2022-01-07 10:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
                   ` (2 subsequent siblings)
  6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2022-01-07 10:08 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/3] drm/i915: split out PCI config space registers from i915_reg.h
URL   : https://patchwork.freedesktop.org/series/98597/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.



^ permalink raw reply	[flat|nested] 12+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: split out PCI config space registers from i915_reg.h
  2022-01-07  9:49 [Intel-gfx] [PATCH 1/3] drm/i915: split out PCI config space registers from i915_reg.h Jani Nikula
                   ` (3 preceding siblings ...)
  2022-01-07 10:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-01-07 10:36 ` Patchwork
  2022-01-07 17:10 ` [Intel-gfx] [PATCH 1/3] " Matt Roper
  2022-01-07 17:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] " Patchwork
  6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2022-01-07 10:36 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 6168 bytes --]

== Series Details ==

Series: series starting with [1/3] drm/i915: split out PCI config space registers from i915_reg.h
URL   : https://patchwork.freedesktop.org/series/98597/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11053 -> Patchwork_21939
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/index.html

Participating hosts (43 -> 36)
------------------------------

  Additional (1): fi-pnv-d510 
  Missing    (8): fi-bdw-5557u bat-dg1-6 bat-dg1-5 bat-adlp-6 bat-adlp-4 bat-rpls-1 fi-bdw-samus bat-jsl-1 

Known issues
------------

  Here are the changes found in Patchwork_21939 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@cs-gfx:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][1] ([fdo#109271]) +13 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/fi-kbl-soraka/igt@amdgpu/amd_basic@cs-gfx.html

  * igt@core_hotunplug@unbind-rebind:
    - fi-pnv-d510:        NOTRUN -> [FAIL][2] ([i915#3194])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/fi-pnv-d510/igt@core_hotunplug@unbind-rebind.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-guc:         [PASS][5] -> [FAIL][6] ([i915#579])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live:
    - fi-skl-6600u:       NOTRUN -> [FAIL][7] ([i915#4547])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/fi-skl-6600u/igt@i915_selftest@live.html

  * igt@i915_selftest@live@gt_pm:
    - fi-kbl-soraka:      NOTRUN -> [DMESG-FAIL][8] ([i915#1886] / [i915#2291])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#533])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@prime_vgem@basic-userptr:
    - fi-pnv-d510:        NOTRUN -> [SKIP][11] ([fdo#109271]) +57 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/fi-pnv-d510/igt@prime_vgem@basic-userptr.html

  * igt@runner@aborted:
    - fi-skl-6600u:       NOTRUN -> [FAIL][12] ([i915#1436] / [i915#4312])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/fi-skl-6600u/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0@smem:
    - fi-kbl-soraka:      [INCOMPLETE][13] -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/fi-kbl-soraka/igt@gem_exec_suspend@basic-s0@smem.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/fi-kbl-soraka/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-skl-6600u:       [FAIL][15] ([i915#3239]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/fi-skl-6600u/igt@i915_pm_rpm@basic-pci-d3-state.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/fi-skl-6600u/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-bxt-dsi:         [DMESG-FAIL][17] ([i915#541]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194
  [i915#3239]: https://gitlab.freedesktop.org/drm/intel/issues/3239
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
  [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579


Build changes
-------------

  * Linux: CI_DRM_11053 -> Patchwork_21939

  CI-20190529: 20190529
  CI_DRM_11053: f0ad19ec6238528d9ea1ee54c9dcde4e0119f1e5 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6325: ac29e097d4ff0f2e269a955ca86c5eb23908467a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21939: 48a43a2e543807f1910d6d009f984c4f99addec5 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

48a43a2e5438 drm/i915: split out vlv sideband registers from i915_reg.h
66ca8d122638 drm/i915: move VGA registers to intel_vga.c
0eec9f19cbae drm/i915: split out PCI config space registers from i915_reg.h

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/index.html

[-- Attachment #2: Type: text/html, Size: 7464 bytes --]

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [Intel-gfx] [PATCH 1/3] drm/i915: split out PCI config space registers from i915_reg.h
  2022-01-07  9:49 [Intel-gfx] [PATCH 1/3] drm/i915: split out PCI config space registers from i915_reg.h Jani Nikula
                   ` (4 preceding siblings ...)
  2022-01-07 10:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-01-07 17:10 ` Matt Roper
  2022-01-10  9:59   ` Jani Nikula
  2022-01-07 17:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] " Patchwork
  6 siblings, 1 reply; 12+ messages in thread
From: Matt Roper @ 2022-01-07 17:10 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

On Fri, Jan 07, 2022 at 11:49:49AM +0200, Jani Nikula wrote:
> The PCI config space registers don't really belong next to the MMIO
> register definitions.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
...
> diff --git a/drivers/gpu/drm/i915/intel_pci_config.h b/drivers/gpu/drm/i915/intel_pci_config.h
> new file mode 100644
> index 000000000000..db35b91d36e0
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_pci_config.h
> @@ -0,0 +1,85 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2021 Intel Corporation

It's 2022 now!

Otherwise,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [Intel-gfx] [PATCH 1/3] drm/i915: split out PCI config space registers from i915_reg.h
  2022-01-07 17:10 ` [Intel-gfx] [PATCH 1/3] " Matt Roper
@ 2022-01-10  9:59   ` Jani Nikula
  0 siblings, 0 replies; 12+ messages in thread
From: Jani Nikula @ 2022-01-10  9:59 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Fri, 07 Jan 2022, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Fri, Jan 07, 2022 at 11:49:49AM +0200, Jani Nikula wrote:
>> The PCI config space registers don't really belong next to the MMIO
>> register definitions.
>> 
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
> ...
>> diff --git a/drivers/gpu/drm/i915/intel_pci_config.h b/drivers/gpu/drm/i915/intel_pci_config.h
>> new file mode 100644
>> index 000000000000..db35b91d36e0
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/intel_pci_config.h
>> @@ -0,0 +1,85 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2021 Intel Corporation
>
> It's 2022 now!

They were written in 2021, but I guess it's the first posting that
matters. Fixed in v2.

>
> Otherwise,
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Thanks!

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 12+ messages in thread

* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: split out PCI config space registers from i915_reg.h
  2022-01-07  9:49 [Intel-gfx] [PATCH 1/3] drm/i915: split out PCI config space registers from i915_reg.h Jani Nikula
                   ` (5 preceding siblings ...)
  2022-01-07 17:10 ` [Intel-gfx] [PATCH 1/3] " Matt Roper
@ 2022-01-07 17:18 ` Patchwork
  6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2022-01-07 17:18 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 30312 bytes --]

== Series Details ==

Series: series starting with [1/3] drm/i915: split out PCI config space registers from i915_reg.h
URL   : https://patchwork.freedesktop.org/series/98597/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11053_full -> Patchwork_21939_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_21939_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_21939_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_21939_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_mmap_offset@clear:
    - shard-tglb:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-tglb3/igt@gem_mmap_offset@clear.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb8/igt@gem_mmap_offset@clear.html

  * igt@gem_ppgtt@blt-vs-render-ctx0:
    - shard-snb:          [PASS][3] -> [DMESG-FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-snb2/igt@gem_ppgtt@blt-vs-render-ctx0.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-snb7/igt@gem_ppgtt@blt-vs-render-ctx0.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_whisper@basic-queues-priority-all:
    - {shard-rkl}:        NOTRUN -> [INCOMPLETE][5]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-rkl-5/igt@gem_exec_whisper@basic-queues-priority-all.html

  * igt@kms_cursor_legacy@pipe-a-torture-move:
    - {shard-rkl}:        [PASS][6] -> [INCOMPLETE][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-rkl-5/igt@kms_cursor_legacy@pipe-a-torture-move.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-rkl-5/igt@kms_cursor_legacy@pipe-a-torture-move.html

  
Known issues
------------

  Here are the changes found in Patchwork_21939_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@preservation-s3@bcs0:
    - shard-kbl:          [PASS][8] -> [DMESG-WARN][9] ([i915#180]) +3 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-kbl3/igt@gem_ctx_isolation@preservation-s3@bcs0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html

  * igt@gem_ctx_shared@q-smoketest-all:
    - shard-glk:          [PASS][10] -> [DMESG-WARN][11] ([i915#118]) +1 similar issue
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-glk6/igt@gem_ctx_shared@q-smoketest-all.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-glk4/igt@gem_ctx_shared@q-smoketest-all.html

  * igt@gem_ctx_sseu@invalid-args:
    - shard-tglb:         NOTRUN -> [SKIP][12] ([i915#280])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb6/igt@gem_ctx_sseu@invalid-args.html

  * igt@gem_eio@in-flight-1us:
    - shard-tglb:         [PASS][13] -> [TIMEOUT][14] ([i915#3063])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-tglb5/igt@gem_eio@in-flight-1us.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb3/igt@gem_eio@in-flight-1us.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          [PASS][15] -> [FAIL][16] ([i915#2846])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-glk7/igt@gem_exec_fair@basic-deadline.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-glk3/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-flow@rcs0:
    - shard-skl:          NOTRUN -> [SKIP][17] ([fdo#109271]) +178 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-skl10/igt@gem_exec_fair@basic-flow@rcs0.html
    - shard-tglb:         [PASS][18] -> [FAIL][19] ([i915#2842])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
    - shard-iclb:         NOTRUN -> [FAIL][20] ([i915#2842])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-iclb2/igt@gem_exec_fair@basic-none@vcs1.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-kbl:          [PASS][21] -> [FAIL][22] ([i915#2842]) +4 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-kbl3/igt@gem_exec_fair@basic-pace@rcs0.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_lmem_swapping@random:
    - shard-glk:          NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#4613])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-glk2/igt@gem_lmem_swapping@random.html

  * igt@gem_lmem_swapping@random-engines:
    - shard-skl:          NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#4613])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-skl10/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_pxp@protected-raw-src-copy-not-readible:
    - shard-tglb:         NOTRUN -> [SKIP][25] ([i915#4270])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb5/igt@gem_pxp@protected-raw-src-copy-not-readible.html

  * igt@gem_userptr_blits@input-checking:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][26] ([i915#3002])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-kbl3/igt@gem_userptr_blits@input-checking.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [PASS][27] -> [DMESG-WARN][28] ([i915#180]) +2 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-apl2/igt@gem_workarounds@suspend-resume-context.html

  * igt@gen9_exec_parse@bb-start-cmd:
    - shard-tglb:         NOTRUN -> [SKIP][29] ([i915#2527] / [i915#2856])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb6/igt@gen9_exec_parse@bb-start-cmd.html

  * igt@gen9_exec_parse@unaligned-access:
    - shard-iclb:         NOTRUN -> [SKIP][30] ([i915#2856])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-iclb3/igt@gen9_exec_parse@unaligned-access.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-skl:          NOTRUN -> [FAIL][31] ([i915#454])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-skl10/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_rpm@system-suspend-modeset:
    - shard-skl:          [PASS][32] -> [INCOMPLETE][33] ([i915#151])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-skl4/igt@i915_pm_rpm@system-suspend-modeset.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-skl8/igt@i915_pm_rpm@system-suspend-modeset.html

  * igt@i915_query@query-topology-known-pci-ids:
    - shard-tglb:         NOTRUN -> [SKIP][34] ([fdo#109303])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb5/igt@i915_query@query-topology-known-pci-ids.html

  * igt@i915_selftest@live@gt_pm:
    - shard-skl:          NOTRUN -> [DMESG-FAIL][35] ([i915#1886] / [i915#2291])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-skl7/igt@i915_selftest@live@gt_pm.html

  * igt@kms_big_fb@linear-8bpp-rotate-90:
    - shard-tglb:         NOTRUN -> [SKIP][36] ([fdo#111614])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb6/igt@kms_big_fb@linear-8bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][37] ([i915#3743])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-skl3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-tglb:         [PASS][38] -> [FAIL][39] ([i915#3743]) +2 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-tglb3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-kbl:          NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#3777])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-kbl3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-skl:          NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#3777])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-skl3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][42] ([i915#3689]) +1 similar issue
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb5/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_ccs.html

  * igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#3886])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-apl6/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-kbl:          NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#3886])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-kbl3/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
    - shard-glk:          NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3886]) +2 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-glk2/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][46] ([fdo#111615] / [i915#3689]) +1 similar issue
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb5/igt@kms_ccs@pipe-b-crc-primary-rotation-180-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
    - shard-skl:          NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#3886]) +6 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-skl3/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][48] ([i915#3689] / [i915#3886])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb6/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs:
    - shard-apl:          NOTRUN -> [SKIP][49] ([fdo#109271]) +24 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-apl6/igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs.html

  * igt@kms_chamelium@dp-crc-multiple:
    - shard-glk:          NOTRUN -> [SKIP][50] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-glk2/igt@kms_chamelium@dp-crc-multiple.html

  * igt@kms_chamelium@dp-hpd-for-each-pipe:
    - shard-kbl:          NOTRUN -> [SKIP][51] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-kbl3/igt@kms_chamelium@dp-hpd-for-each-pipe.html

  * igt@kms_color_chamelium@pipe-c-degamma:
    - shard-tglb:         NOTRUN -> [SKIP][52] ([fdo#109284] / [fdo#111827]) +4 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb6/igt@kms_color_chamelium@pipe-c-degamma.html

  * igt@kms_color_chamelium@pipe-d-ctm-0-25:
    - shard-apl:          NOTRUN -> [SKIP][53] ([fdo#109271] / [fdo#111827])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-apl6/igt@kms_color_chamelium@pipe-d-ctm-0-25.html

  * igt@kms_color_chamelium@pipe-d-degamma:
    - shard-skl:          NOTRUN -> [SKIP][54] ([fdo#109271] / [fdo#111827]) +13 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-skl7/igt@kms_color_chamelium@pipe-d-degamma.html

  * igt@kms_content_protection@legacy:
    - shard-glk:          NOTRUN -> [SKIP][55] ([fdo#109271]) +38 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-glk2/igt@kms_content_protection@legacy.html

  * igt@kms_cursor_crc@pipe-b-cursor-32x10-onscreen:
    - shard-tglb:         NOTRUN -> [SKIP][56] ([i915#3359])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb6/igt@kms_cursor_crc@pipe-b-cursor-32x10-onscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen:
    - shard-tglb:         NOTRUN -> [SKIP][57] ([fdo#109279] / [i915#3359]) +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
    - shard-iclb:         NOTRUN -> [SKIP][58] ([fdo#109274] / [fdo#109278])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-iclb3/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-skl:          [PASS][59] -> [FAIL][60] ([i915#2346]) +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-tglb:         NOTRUN -> [SKIP][61] ([i915#4103])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-apl:          [PASS][62] -> [INCOMPLETE][63] ([i915#180] / [i915#1982])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
    - shard-tglb:         NOTRUN -> [SKIP][64] ([fdo#109274] / [fdo#111825]) +1 similar issue
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb6/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-skl:          [PASS][65] -> [FAIL][66] ([i915#79])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
    - shard-tglb:         [PASS][67] -> [FAIL][68] ([i915#79])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-tglb5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
    - shard-iclb:         [PASS][69] -> [SKIP][70] ([i915#3701]) +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-iclb8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
    - shard-kbl:          NOTRUN -> [SKIP][71] ([fdo#109271]) +41 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite:
    - shard-tglb:         NOTRUN -> [SKIP][72] ([fdo#109280] / [fdo#111825]) +6 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-skl:          NOTRUN -> [FAIL][73] ([fdo#108145] / [i915#265]) +2 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
    - shard-apl:          NOTRUN -> [FAIL][74] ([fdo#108145] / [i915#265])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [PASS][75] -> [FAIL][76] ([fdo#108145] / [i915#265])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
    - shard-skl:          NOTRUN -> [FAIL][77] ([i915#265])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html

  * igt@kms_plane_lowres@pipe-b-tiling-x:
    - shard-tglb:         NOTRUN -> [SKIP][78] ([i915#3536])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb5/igt@kms_plane_lowres@pipe-b-tiling-x.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
    - shard-glk:          NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#2733])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-glk2/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
    - shard-skl:          NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#658])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-skl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
    - shard-apl:          NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#658])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-apl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
    - shard-kbl:          NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#658]) +1 similar issue
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-kbl3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-tglb:         NOTRUN -> [SKIP][83] ([i915#1911])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb6/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@psr2_cursor_mmap_gtt:
    - shard-iclb:         NOTRUN -> [SKIP][84] ([fdo#109441])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-iclb3/igt@kms_psr@psr2_cursor_mmap_gtt.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-tglb:         NOTRUN -> [FAIL][85] ([i915#132] / [i915#3467])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb5/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         [PASS][86] -> [SKIP][87] ([fdo#109441]) +1 similar issue
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-iclb3/igt@kms_psr@psr2_primary_mmap_cpu.html

  * igt@kms_sysfs_edid_timing:
    - shard-skl:          NOTRUN -> [FAIL][88] ([IGT#2])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-skl10/igt@kms_sysfs_edid_timing.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [PASS][89] -> [DMESG-WARN][90] ([i915#180] / [i915#295])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-skl:          [PASS][91] -> [INCOMPLETE][92] ([i915#2828])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-skl10/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-skl4/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  * igt@kms_vblank@pipe-d-query-forked-hang:
    - shard-snb:          NOTRUN -> [SKIP][93] ([fdo#109271]) +12 similar issues
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-snb5/igt@kms_vblank@pipe-d-query-forked-hang.html

  * igt@kms_vrr@flipline:
    - shard-tglb:         NOTRUN -> [SKIP][94] ([fdo#109502])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb5/igt@kms_vrr@flipline.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-skl:          NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#2437]) +1 similar issue
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-skl3/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@perf@per-context-mode-unprivileged:
    - shard-tglb:         NOTRUN -> [SKIP][96] ([fdo#109289])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb6/igt@perf@per-context-mode-unprivileged.html

  * igt@prime_nv_pcopy@test3_2:
    - shard-tglb:         NOTRUN -> [SKIP][97] ([fdo#109291]) +2 similar issues
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb5/igt@prime_nv_pcopy@test3_2.html

  * igt@sysfs_clients@fair-7:
    - shard-glk:          NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#2994])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-glk2/igt@sysfs_clients@fair-7.html

  * igt@sysfs_clients@pidname:
    - shard-tglb:         NOTRUN -> [SKIP][99] ([i915#2994])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb5/igt@sysfs_clients@pidname.html

  * igt@sysfs_clients@recycle-many:
    - shard-apl:          NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#2994])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-apl6/igt@sysfs_clients@recycle-many.html
    - shard-skl:          NOTRUN -> [SKIP][101] ([fdo#109271] / [i915#2994])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-skl7/igt@sysfs_clients@recycle-many.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@nonpriv-switch@vecs0:
    - {shard-rkl}:        [INCOMPLETE][102] -> [PASS][103] +2 similar issues
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-rkl-5/igt@gem_ctx_isolation@nonpriv-switch@vecs0.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-rkl-5/igt@gem_ctx_isolation@nonpriv-switch@vecs0.html

  * igt@gem_eio@in-flight-contexts-immediate:
    - shard-tglb:         [TIMEOUT][104] ([i915#3063]) -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-tglb2/igt@gem_eio@in-flight-contexts-immediate.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb2/igt@gem_eio@in-flight-contexts-immediate.html

  * igt@gem_eio@in-flight-suspend:
    - shard-apl:          [DMESG-WARN][106] ([i915#180]) -> [PASS][107]
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-apl1/igt@gem_eio@in-flight-suspend.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-apl6/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_balancer@bonded-pair:
    - {shard-tglu}:       [FAIL][108] ([i915#1888]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-tglu-6/igt@gem_exec_balancer@bonded-pair.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglu-3/igt@gem_exec_balancer@bonded-pair.html

  * igt@gem_exec_balancer@parallel:
    - shard-iclb:         [SKIP][110] ([i915#4525]) -> [PASS][111] +3 similar issues
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-iclb5/igt@gem_exec_balancer@parallel.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-iclb4/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [FAIL][112] ([i915#2842]) -> [PASS][113]
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-apl:          [FAIL][114] ([i915#2842]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-apl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-apl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-kbl:          [FAIL][116] ([i915#2842]) -> [PASS][117] +1 similar issue
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_exec_fence@expired-history:
    - {shard-rkl}:        [DMESG-WARN][118] -> ([PASS][119], [PASS][120])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-rkl-5/igt@gem_exec_fence@expired-history.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-rkl-4/igt@gem_exec_fence@expired-history.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-rkl-1/igt@gem_exec_fence@expired-history.html

  * igt@gem_exec_whisper@basic-normal-all:
    - {shard-rkl}:        ([PASS][121], [FAIL][122]) -> [PASS][123]
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-rkl-4/igt@gem_exec_whisper@basic-normal-all.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-rkl-5/igt@gem_exec_whisper@basic-normal-all.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-rkl-1/igt@gem_exec_whisper@basic-normal-all.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [SKIP][124] ([i915#2190]) -> [PASS][125]
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-tglb7/igt@gem_huc_copy@huc-copy.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-tglb2/igt@gem_huc_copy@huc-copy.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-skl:          [DMESG-WARN][126] ([i915#1436] / [i915#716]) -> [PASS][127]
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-skl9/igt@gen9_exec_parse@allowed-all.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-skl10/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [FAIL][128] ([i915#454]) -> [PASS][129] +1 similar issue
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-iclb2/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_selftest@live@hangcheck:
    - shard-snb:          [INCOMPLETE][130] ([i915#3921]) -> [PASS][131]
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-snb7/igt@i915_selftest@live@hangcheck.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-snb5/igt@i915_selftest@live@hangcheck.html

  * igt@kms_big_fb@linear-32bpp-rotate-0:
    - shard-glk:          [DMESG-WARN][132] ([i915#118]) -> [PASS][133]
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-glk8/igt@kms_big_fb@linear-32bpp-rotate-0.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-glk7/igt@kms_big_fb@linear-32bpp-rotate-0.html

  * igt@kms_color@pipe-c-invalid-gamma-lut-sizes:
    - {shard-rkl}:        [SKIP][134] ([i915#4070]) -> ([PASS][135], [PASS][136])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-rkl-6/igt@kms_color@pipe-c-invalid-gamma-lut-sizes.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-rkl-5/igt@kms_color@pipe-c-invalid-gamma-lut-sizes.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-rkl-4/igt@kms_color@pipe-c-invalid-gamma-lut-sizes.html

  * igt@kms_cursor_legacy@pipe-c-forked-move:
    - {shard-rkl}:        [SKIP][137] ([i915#4070]) -> [PASS][138]
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11053/shard-rkl-2/igt@kms_cursor_legacy@pipe-c-forked-move.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/shard-rkl-5/igt@kms_cursor_legacy@pipe-c-forked-move.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-skl:          [FAIL][139] ([i915#79]) -> [PASS][140]
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21939/index.html

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^ permalink raw reply	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2022-01-10  9:59 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-01-07  9:49 [Intel-gfx] [PATCH 1/3] drm/i915: split out PCI config space registers from i915_reg.h Jani Nikula
2022-01-07  9:49 ` [Intel-gfx] [PATCH 2/3] drm/i915: move VGA registers to intel_vga.c Jani Nikula
2022-01-07 17:24   ` Matt Roper
2022-01-10  9:58     ` Jani Nikula
2022-01-07  9:49 ` [Intel-gfx] [PATCH 3/3] drm/i915: split out vlv sideband registers from i915_reg.h Jani Nikula
2022-01-07 17:30   ` Matt Roper
2022-01-07 10:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: split out PCI config space " Patchwork
2022-01-07 10:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-01-07 10:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-07 17:10 ` [Intel-gfx] [PATCH 1/3] " Matt Roper
2022-01-10  9:59   ` Jani Nikula
2022-01-07 17:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] " Patchwork

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