From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54239C433EF for ; Fri, 12 Nov 2021 09:33:08 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1455E60EE2 for ; Fri, 12 Nov 2021 09:33:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1455E60EE2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0849889B20; Fri, 12 Nov 2021 09:33:07 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id BEAD589A86; Fri, 12 Nov 2021 09:33:05 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10165"; a="220315094" X-IronPort-AV: E=Sophos;i="5.87,229,1631602800"; d="scan'208";a="220315094" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2021 01:33:05 -0800 X-IronPort-AV: E=Sophos;i="5.87,229,1631602800"; d="scan'208";a="504821187" Received: from sbacanu-mobl1.ger.corp.intel.com (HELO localhost) ([10.251.217.145]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2021 01:33:03 -0800 From: Jani Nikula To: Matt Roper , intel-gfx@lists.freedesktop.org In-Reply-To: <20211111215644.1123373-2-matthew.d.roper@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20211111215644.1123373-1-matthew.d.roper@intel.com> <20211111215644.1123373-2-matthew.d.roper@intel.com> Date: Fri, 12 Nov 2021 11:33:00 +0200 Message-ID: <87a6i94t2r.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915/dg2: Add Wa_14010547955 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, 11 Nov 2021, Matt Roper wrote: > This workaround is documented a bit strangely in the bspec; it's listed > as an A0 workaround, but the description clarifies that the workaround > is implicitly handled by the hardware and what the driver really needs > to do is program a chicken bit to reenable some internal behavior. > > Signed-off-by: Matt Roper > --- > drivers/gpu/drm/i915/display/intel_display.c | 4 ++++ > drivers/gpu/drm/i915/i915_reg.h | 5 +++-- > 2 files changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 0ceee8ac6671..5d50d06f4eb7 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -988,6 +988,10 @@ static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) > else if (DISPLAY_VER(dev_priv) >= 13) > tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; > > + /* Wa_14010547955:dg2 */ > + if (IS_DG2_DISP_STEP(dev_priv, STEP_B0, STEP_FOREVER)) How did we end up with _DISP_ for DG2 when everything else has _DISPLAY_? BR, Jani. > + tmp |= DG2_RENDER_CCSTAG_4_3_EN; > + > intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); > } > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 07d6cf76c389..680ace373e00 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -8480,8 +8480,9 @@ enum { > _PIPEB_CHICKEN) > #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30) > #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30) > -#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15) > -#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) > +#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15) > +#define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12) > +#define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7) > > #define FF_MODE2 _MMIO(0x6604) > #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) -- Jani Nikula, Intel Open Source Graphics Center