From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH 1/2] drm/i915/edp: read edp display control registers unconditionally Date: Mon, 30 Oct 2017 11:55:53 +0200 Message-ID: <87a809gdsm.fsf@intel.com> References: <20171026142932.17737-1-jani.nikula@intel.com> <20171026194058.GD19276@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 882D56E349 for ; Mon, 30 Oct 2017 09:54:27 +0000 (UTC) In-Reply-To: <20171026194058.GD19276@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Manasi Navare Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org T24gVGh1LCAyNiBPY3QgMjAxNywgTWFuYXNpIE5hdmFyZSA8bWFuYXNpLmQubmF2YXJlQGludGVs LmNvbT4gd3JvdGU6Cj4gVGhpcyBpcyB0aGUgc2Vjb25kIHdpZXJkIGVEUCBwYW5lbCBjYXNlL2J1 ZyB0aGF0IEkgaGF2ZSBzZWVuIHJlY2VudGx5Cj4gd2hlcmUgaXQgZG9lc250IG5vdCBiZWhhdmUg YXMgcGVyIHRoZSBzcGVjLgoKSXQnbGwgdGVhY2ggeW91IHRvIHRyZWF0IHRoZSBkaXNwbGF5cyBh cyBleHRlcm5hbCBkZXZpY2VzIHRoYXQgdHJ5IHRvCmZ1enogb3VyIGRyaXZlci4uLiBhbmQgdGhl cmUncyBhIGZpbmUgYmFsYW5jZSBiZXR3ZWVuIGJlaW5nIGRlZmVuc2l2ZQphbmQgeWV0IHRyeWlu ZyB0byBnZXQgYSBwaWN0dXJlIG9uIHNjcmVlbiBubyBtYXR0ZXIgd2hhdC4KCkJSLApKYW5pLgoK LS0gCkphbmkgTmlrdWxhLCBJbnRlbCBPcGVuIFNvdXJjZSBUZWNobm9sb2d5IENlbnRlcgpfX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpJbnRlbC1nZnggbWFp bGluZyBsaXN0CkludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5m cmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK