From: Jani Nikula <jani.nikula@intel.com>
To: Madhav Chauhan <madhav.chauhan@intel.com>,
intel-gfx@lists.freedesktop.org
Cc: ander.conselvan.de.oliveira@intel.com, Deepak M <m.deepak@intel.com>
Subject: Re: [GLK MIPI DSI V5 4/8] drm/i915: Set the Z inversion overlap field
Date: Thu, 16 Feb 2017 17:18:14 +0200 [thread overview]
Message-ID: <87a89mmafd.fsf@intel.com> (raw)
In-Reply-To: <1487078180-15147-5-git-send-email-madhav.chauhan@intel.com>
On Tue, 14 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Deepak M <m.deepak@intel.com>
>
> Dual link Z-inversion overlap field is present
> in MIPI_CTRL register unlike the older platforms,
> hence setting the same in this patch.
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Pushed this one patch to dinq. This one is really bxt specific, and
should have been first in the series.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 17 +++++++++++++----
> 1 file changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index a72a10f..ef643c1 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -561,12 +561,21 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>
> if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> u32 temp;
> -
> - temp = I915_READ(VLV_CHICKEN_3);
> - temp &= ~PIXEL_OVERLAP_CNT_MASK |
> + if (IS_GEN9_LP(dev_priv)) {
> + for_each_dsi_port(port, intel_dsi->ports) {
> + temp = I915_READ(MIPI_CTRL(port));
> + temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
> + intel_dsi->pixel_overlap <<
> + BXT_PIXEL_OVERLAP_CNT_SHIFT;
> + I915_WRITE(MIPI_CTRL(port), temp);
> + }
> + } else {
> + temp = I915_READ(VLV_CHICKEN_3);
> + temp &= ~PIXEL_OVERLAP_CNT_MASK |
> intel_dsi->pixel_overlap <<
> PIXEL_OVERLAP_CNT_SHIFT;
> - I915_WRITE(VLV_CHICKEN_3, temp);
> + I915_WRITE(VLV_CHICKEN_3, temp);
> + }
> }
>
> for_each_dsi_port(port, intel_dsi->ports) {
--
Jani Nikula, Intel Open Source Technology Center
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next prev parent reply other threads:[~2017-02-16 15:18 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-14 13:16 [GLK MIPI DSI V5 0/8] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
2017-02-14 13:16 ` [GLK MIPI DSI V5 1/8] drm/i915/glk: Program dphy param reg for GLK Madhav Chauhan
2017-02-16 14:47 ` Jani Nikula
2017-02-14 13:16 ` [GLK MIPI DSI V5 2/8] drm/i915/glk: Program new MIPI DSI PHY registers " Madhav Chauhan
2017-02-16 14:50 ` Jani Nikula
2017-02-14 13:16 ` [GLK MIPI DSI V5 3/8] drm/i915/glk: Add MIPIIO Enable/disable sequence Madhav Chauhan
2017-02-16 15:07 ` Jani Nikula
2017-02-17 5:23 ` Chauhan, Madhav
2017-02-14 13:16 ` [GLK MIPI DSI V5 4/8] drm/i915: Set the Z inversion overlap field Madhav Chauhan
2017-02-16 15:18 ` Jani Nikula [this message]
2017-02-14 13:16 ` [GLK MIPI DSI V5 5/8] drm/i915/glk: Add DSI PLL divider range for glk Madhav Chauhan
2017-02-16 15:13 ` Jani Nikula
2017-02-14 13:16 ` [GLK MIPI DSI V5 6/8] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT Madhav Chauhan
2017-02-16 15:15 ` Jani Nikula
2017-02-14 13:16 ` [GLK MIPI DSI V5 7/8] drm/i915/glk: Program txesc clock divider for GLK Madhav Chauhan
2017-02-14 13:16 ` [GLK MIPI DSI V5 8/8] drm/i915/glk: Validate only DSI PORT A PLL divider Madhav Chauhan
2017-02-14 16:32 ` ✗ Fi.CI.BAT: failure for GLK MIPI DSI VIDEO MODE PATCHES (rev5) Patchwork
2017-02-16 15:19 ` Jani Nikula
2017-02-16 16:05 ` Chauhan, Madhav
2017-02-16 18:14 ` Jani Nikula
2017-02-17 7:36 ` Chauhan, Madhav
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