From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Sanchez, AdolfoX" <adolfox.sanchez@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: force DP lane count on Broadwell platform
Date: Wed, 18 May 2016 09:37:54 +0300 [thread overview]
Message-ID: <87a8jnrhvh.fsf@intel.com> (raw)
In-Reply-To: <56B36C37A8AFDD43BD486A5FC41A6D991E228425@CRSMSX101.amr.corp.intel.com>
On Wed, 18 May 2016, "Sanchez, AdolfoX" <adolfox.sanchez@intel.com> wrote:
> What PRM registers should be modified to force the source lanes to
> report 2 lanes maximum? Is it enough to modify the registers
> DP_TP_CTL and DDI_BUF_CTL, or should any other register be modified?
You should probably look at intel_ddi_init() in intel_ddi.c, and set
intel_dig_port->max_lanes to 2. Then it should limit the source to two
lanes wherever it's needed.
Of course, I should ask you why you need this; maybe you should be
asking a different question. ;)
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
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next prev parent reply other threads:[~2016-05-18 6:37 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-18 0:08 force DP lane count on Broadwell platform Sanchez, AdolfoX
2016-05-18 6:37 ` Jani Nikula [this message]
2016-05-18 19:21 ` Sanchez, AdolfoX
2016-05-19 6:31 ` Jani Nikula
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