Re: [PATCH] drm/i915/skl+: Fix Watermark calculation for Broxton

From: Jani Nikula <jani.nikula@linux.intel.com>
To: Daniel Vetter <daniel@ffwll.ch>, Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/skl+: Fix Watermark calculation for Broxton
Date: Tue, 17 Nov 2015 16:52:06 +0200	[thread overview]
Message-ID: <87a8qcel0p.fsf@intel.com> (raw)
In-Reply-To: <20151117141947.GC16848@phenom.ffwll.local>

On Tue, 17 Nov 2015, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Fri, Oct 23, 2015 at 09:53:35AM -0700, Matt Roper wrote:
>> On Mon, Sep 21, 2015 at 11:41:18PM +0530, Kumar, Mahesh wrote:
>> > In case of Y-Tiling, "plane_blocks_per_line" calculation is different
>> > than X/None-Tiling case.
>> > This patch corrects this calculation according to Bspec.
>> > plane blocks per line = Plane memory format is Y tile ?
>> > 		ceiling[4 * plane bytes per line / 512]/4 :
>> >                 	ceiling[plane bytes per line / 512]
>> > As per BSpec Don't increment selected "result_blocks" & "result_lines"
>> > in case of BROXTON.
>> > 
>> > Signed-off-by: Kumar, Mahesh <mahesh1.kumar@intel.com>
>> 
>> Confirmed both changes against bspec.  Note that your first hunk here is
>> technically a fix for both SKL and BXT, only the second one is a
>> BXT-specific fix.
>> 
>> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
> This needs to be rebased (p_params is gone).

And we already have this for skl

commit 0fda65680e92545caea5be7805a7f0a617fb6c20
Author: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date:   Fri Feb 27 15:12:35 2015 +0000

    drm/i915/skl: Update watermarks for Y tiling

Mahesh, please check if you still need to make changes for BXT.

BR,
Jani.

> -Daniel
>> 
>> > ---
>> >  drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++--
>> >  1 file changed, 8 insertions(+), 2 deletions(-)
>> > 
>> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> > index a1ed920..5cfb5d9 100644
>> > --- a/drivers/gpu/drm/i915/intel_pm.c
>> > +++ b/drivers/gpu/drm/i915/intel_pm.c
>> > @@ -3247,7 +3247,13 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>> >  				 latency);
>> >  
>> >  	plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
>> > -	plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
>> > +
>> > +	if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
>> > +	    p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
>> > +		plane_blocks_per_line = DIV_ROUND_UP(4 * plane_bytes_per_line, 512);
>> > +		plane_blocks_per_line /= 4;
>> > +	} else
>> > +		plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
>> >  
>> >  	if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
>> >  	    p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
>> > @@ -3277,7 +3283,7 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>> >  	res_blocks = selected_result + 1;
>> >  	res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
>> >  
>> > -	if (level >= 1 && level <= 7) {
>> > +	if (level >= 1 && level <= 7 && !IS_BROXTON(dev_priv->dev)) {
>> >  		if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
>> >  		    p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
>> >  			res_lines += 4;
>> > -- 
>> > 1.9.1
>> > 
>> 
>> -- 
>> Matt Roper
>> Graphics Software Engineer
>> IoTG Platform Enabling & Development
>> Intel Corporation
>> (916) 356-2795
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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