* [PATCH] drm/i915: Reduce frequency of unspecific HSW reg debugging
@ 2015-08-26 7:52 Chris Wilson
2015-08-26 15:27 ` Mika Kuoppala
0 siblings, 1 reply; 8+ messages in thread
From: Chris Wilson @ 2015-08-26 7:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter, Mika Kuoppala
Delay the expensive read on the FPGA_DBG register from once per mmio to
once per forcewake section when we are doing the general wellbeing
check rather than the targetted error detection. This almost reduces
the overhead of the debug facility (for example when submitting execlists)
to zero whilst keeping the debug checks around.
v2: Enable one-shot mmio debugging from the interrupt check as well as a
safeguard to catch invalid display writes from outside the powerwell.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 56 ++++++++++++++++++++-----------------
1 file changed, 30 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 9d3c2e420d2b..05c50cc87d1d 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -149,6 +149,30 @@ fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_doma
}
static void
+hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
+{
+ static bool mmio_debug_once = true;
+
+ if (i915.mmio_debug || !mmio_debug_once)
+ return;
+
+ if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
+ DRM_DEBUG("Unclaimed register detected, "
+ "enabling oneshot unclaimed register reporting. "
+ "Please use i915.mmio_debug=N for more information.\n");
+ __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
+ i915.mmio_debug = mmio_debug_once--;
+ }
+}
+
+static void
+fw_domains_put_debug(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
+{
+ hsw_unclaimed_reg_detect(dev_priv);
+ fw_domains_put(dev_priv, fw_domains);
+}
+
+static void
fw_domains_posting_read(struct drm_i915_private *dev_priv)
{
struct intel_uncore_forcewake_domain *d;
@@ -623,23 +647,6 @@ hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
}
}
-static void
-hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
-{
- static bool mmio_debug_once = true;
-
- if (i915.mmio_debug || !mmio_debug_once)
- return;
-
- if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
- DRM_DEBUG("Unclaimed register detected, "
- "enabling oneshot unclaimed register reporting. "
- "Please use i915.mmio_debug=N for more information.\n");
- __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
- i915.mmio_debug = mmio_debug_once--;
- }
-}
-
#define GEN2_READ_HEADER(x) \
u##x val = 0; \
assert_device_not_suspended(dev_priv);
@@ -891,7 +898,6 @@ hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace)
gen6_gt_check_fifodbg(dev_priv); \
} \
hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
- hsw_unclaimed_reg_detect(dev_priv); \
GEN6_WRITE_FOOTER; \
}
@@ -933,7 +939,6 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
__force_wake_get(dev_priv, FORCEWAKE_RENDER); \
__raw_i915_write##x(dev_priv, reg, val); \
hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
- hsw_unclaimed_reg_detect(dev_priv); \
GEN6_WRITE_FOOTER; \
}
@@ -1182,6 +1187,10 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
FORCEWAKE, FORCEWAKE_ACK);
}
+ if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
+ dev_priv->uncore.funcs.force_wake_put == fw_domains_put)
+ dev_priv->uncore.funcs.force_wake_put = fw_domains_put_debug;
+
/* All future platforms are expected to require complex power gating */
WARN_ON(dev_priv->uncore.fw_domains == 0);
}
@@ -1545,11 +1554,6 @@ bool intel_has_gpu_reset(struct drm_device *dev)
void intel_uncore_check_errors(struct drm_device *dev)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
-
- if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
- (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
- DRM_ERROR("Unclaimed register before interrupt\n");
- __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
- }
+ if (HAS_FPGA_DBG_UNCLAIMED(dev))
+ hsw_unclaimed_reg_detect(to_i915(dev));
}
--
2.5.0
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^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915: Reduce frequency of unspecific HSW reg debugging
2015-08-26 7:52 [PATCH] drm/i915: Reduce frequency of unspecific HSW reg debugging Chris Wilson
@ 2015-08-26 15:27 ` Mika Kuoppala
2015-08-26 15:49 ` Chris Wilson
0 siblings, 1 reply; 8+ messages in thread
From: Mika Kuoppala @ 2015-08-26 15:27 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Daniel Vetter
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Delay the expensive read on the FPGA_DBG register from once per mmio to
> once per forcewake section when we are doing the general wellbeing
> check rather than the targetted error detection. This almost reduces
> the overhead of the debug facility (for example when submitting execlists)
> to zero whilst keeping the debug checks around.
>
> v2: Enable one-shot mmio debugging from the interrupt check as well as a
> safeguard to catch invalid display writes from outside the powerwell.
>
Not a particular problem with this patch, but I noticed that
on skl, we lose the concents of the FPGA_DBG register
immediately when we clear the forcewake. Without explicit
write to clear the bit, which is claimed to be sticky.
On re aquiring forcewake, the register contents is zero :(
-Mika
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 56 ++++++++++++++++++++-----------------
> 1 file changed, 30 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 9d3c2e420d2b..05c50cc87d1d 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -149,6 +149,30 @@ fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_doma
> }
>
> static void
> +hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
> +{
> + static bool mmio_debug_once = true;
> +
> + if (i915.mmio_debug || !mmio_debug_once)
> + return;
> +
> + if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
> + DRM_DEBUG("Unclaimed register detected, "
> + "enabling oneshot unclaimed register reporting. "
> + "Please use i915.mmio_debug=N for more information.\n");
> + __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
> + i915.mmio_debug = mmio_debug_once--;
> + }
> +}
> +
> +static void
> +fw_domains_put_debug(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
> +{
> + hsw_unclaimed_reg_detect(dev_priv);
> + fw_domains_put(dev_priv, fw_domains);
> +}
> +
> +static void
> fw_domains_posting_read(struct drm_i915_private *dev_priv)
> {
> struct intel_uncore_forcewake_domain *d;
> @@ -623,23 +647,6 @@ hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
> }
> }
>
> -static void
> -hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
> -{
> - static bool mmio_debug_once = true;
> -
> - if (i915.mmio_debug || !mmio_debug_once)
> - return;
> -
> - if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
> - DRM_DEBUG("Unclaimed register detected, "
> - "enabling oneshot unclaimed register reporting. "
> - "Please use i915.mmio_debug=N for more information.\n");
> - __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
> - i915.mmio_debug = mmio_debug_once--;
> - }
> -}
> -
> #define GEN2_READ_HEADER(x) \
> u##x val = 0; \
> assert_device_not_suspended(dev_priv);
> @@ -891,7 +898,6 @@ hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace)
> gen6_gt_check_fifodbg(dev_priv); \
> } \
> hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
> - hsw_unclaimed_reg_detect(dev_priv); \
> GEN6_WRITE_FOOTER; \
> }
>
> @@ -933,7 +939,6 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
> __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
> __raw_i915_write##x(dev_priv, reg, val); \
> hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
> - hsw_unclaimed_reg_detect(dev_priv); \
> GEN6_WRITE_FOOTER; \
> }
>
> @@ -1182,6 +1187,10 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
> FORCEWAKE, FORCEWAKE_ACK);
> }
>
> + if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
> + dev_priv->uncore.funcs.force_wake_put == fw_domains_put)
> + dev_priv->uncore.funcs.force_wake_put = fw_domains_put_debug;
> +
> /* All future platforms are expected to require complex power gating */
> WARN_ON(dev_priv->uncore.fw_domains == 0);
> }
> @@ -1545,11 +1554,6 @@ bool intel_has_gpu_reset(struct drm_device *dev)
>
> void intel_uncore_check_errors(struct drm_device *dev)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> -
> - if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
> - (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
> - DRM_ERROR("Unclaimed register before interrupt\n");
> - __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
> - }
> + if (HAS_FPGA_DBG_UNCLAIMED(dev))
> + hsw_unclaimed_reg_detect(to_i915(dev));
> }
> --
> 2.5.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915: Reduce frequency of unspecific HSW reg debugging
2015-08-26 15:27 ` Mika Kuoppala
@ 2015-08-26 15:49 ` Chris Wilson
0 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2015-08-26 15:49 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: Daniel Vetter, intel-gfx
On Wed, Aug 26, 2015 at 06:27:36PM +0300, Mika Kuoppala wrote:
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > Delay the expensive read on the FPGA_DBG register from once per mmio to
> > once per forcewake section when we are doing the general wellbeing
> > check rather than the targetted error detection. This almost reduces
> > the overhead of the debug facility (for example when submitting execlists)
> > to zero whilst keeping the debug checks around.
> >
> > v2: Enable one-shot mmio debugging from the interrupt check as well as a
> > safeguard to catch invalid display writes from outside the powerwell.
> >
>
> Not a particular problem with this patch, but I noticed that
> on skl, we lose the concents of the FPGA_DBG register
> immediately when we clear the forcewake. Without explicit
> write to clear the bit, which is claimed to be sticky.
>
> On re aquiring forcewake, the register contents is zero :(
Doesn't that defeat the purpose of using the dbg register to detect
accesses outside of the powerwell? I'd ask whether the new behaviour is
documented/intended...
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] drm/i915: Reduce frequency of unspecific HSW reg debugging
@ 2015-03-22 15:41 Chris Wilson
2015-03-22 18:38 ` shuang.he
2015-03-23 9:35 ` Daniel Vetter
0 siblings, 2 replies; 8+ messages in thread
From: Chris Wilson @ 2015-03-22 15:41 UTC (permalink / raw)
To: intel-gfx; +Cc: Mika Kuoppala, Paulo Zanoni
Delay the expensive read on the FPGA_DBG register from once per mmio to
once per forcewake section when we are doing the general wellbeing
check rather than the targetted error detection. This almost reduces
the overhead of the debug facility (for example when submitting execlists)
to zero whilst keeping the debug checks around.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 47 ++++++++++++++++++++-----------------
1 file changed, 26 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index ab5cc94588e1..6b065592aede 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -149,6 +149,30 @@ fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_doma
}
static void
+hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
+{
+ static bool mmio_debug_once = true;
+
+ if (i915.mmio_debug || !mmio_debug_once)
+ return;
+
+ if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
+ DRM_DEBUG("Unclaimed register detected, "
+ "enabling oneshot unclaimed register reporting. "
+ "Please use i915.mmio_debug=N for more information.\n");
+ __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
+ i915.mmio_debug = mmio_debug_once--;
+ }
+}
+
+static void
+fw_domains_put_debug(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
+{
+ hsw_unclaimed_reg_detect(dev_priv);
+ fw_domains_put(dev_priv, fw_domains);
+}
+
+static void
fw_domains_posting_read(struct drm_i915_private *dev_priv)
{
struct intel_uncore_forcewake_domain *d;
@@ -561,23 +585,6 @@ hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
}
}
-static void
-hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
-{
- static bool mmio_debug_once = true;
-
- if (i915.mmio_debug || !mmio_debug_once)
- return;
-
- if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
- DRM_DEBUG("Unclaimed register detected, "
- "enabling oneshot unclaimed register reporting. "
- "Please use i915.mmio_debug=N for more information.\n");
- __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
- i915.mmio_debug = mmio_debug_once--;
- }
-}
-
#define GEN2_READ_HEADER(x) \
u##x val = 0; \
assert_device_not_suspended(dev_priv);
@@ -829,7 +836,6 @@ hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace)
gen6_gt_check_fifodbg(dev_priv); \
} \
hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
- hsw_unclaimed_reg_detect(dev_priv); \
GEN6_WRITE_FOOTER; \
}
@@ -871,7 +877,6 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
__force_wake_get(dev_priv, FORCEWAKE_RENDER); \
__raw_i915_write##x(dev_priv, reg, val); \
hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
- hsw_unclaimed_reg_detect(dev_priv); \
GEN6_WRITE_FOOTER; \
}
@@ -1043,7 +1048,7 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
if (IS_GEN9(dev)) {
dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
- dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
+ dev_priv->uncore.funcs.force_wake_put = fw_domains_put_debug;
fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
FORCEWAKE_RENDER_GEN9,
FORCEWAKE_ACK_RENDER_GEN9);
@@ -1066,7 +1071,7 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
dev_priv->uncore.funcs.force_wake_get =
fw_domains_get_with_thread_status;
- dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
+ dev_priv->uncore.funcs.force_wake_put = fw_domains_put_debug;
fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
} else if (IS_IVYBRIDGE(dev)) {
--
2.1.4
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^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915: Reduce frequency of unspecific HSW reg debugging
2015-03-22 15:41 Chris Wilson
@ 2015-03-22 18:38 ` shuang.he
2015-03-23 9:35 ` Daniel Vetter
1 sibling, 0 replies; 8+ messages in thread
From: shuang.he @ 2015-03-22 18:38 UTC (permalink / raw)
To: shuang.he, ethan.gao, intel-gfx, chris
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6023
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -4 272/272 268/272
ILK 303/303 303/303
SNB 304/304 304/304
IVB 344/344 344/344
BYT 287/287 287/287
HSW 362/362 362/362
BDW 308/308 308/308
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
PNV igt_gem_userptr_blits_minor-unsync-interruptible DMESG_WARN(1)PASS(1) DMESG_WARN(1)PASS(1)
PNV igt_gen3_render_mixed_blits FAIL(1)PASS(2) FAIL(2)
*PNV igt_gen3_render_tiledy_blits PASS(2) FAIL(2)
*PNV igt_gem_tiled_pread_pwrite PASS(1) FAIL(2)
Note: You need to pay more attention to line start with '*'
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: Reduce frequency of unspecific HSW reg debugging
2015-03-22 15:41 Chris Wilson
2015-03-22 18:38 ` shuang.he
@ 2015-03-23 9:35 ` Daniel Vetter
2015-03-23 9:43 ` Chris Wilson
1 sibling, 1 reply; 8+ messages in thread
From: Daniel Vetter @ 2015-03-23 9:35 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx, Paulo Zanoni, Mika Kuoppala
On Sun, Mar 22, 2015 at 03:41:04PM +0000, Chris Wilson wrote:
> Delay the expensive read on the FPGA_DBG register from once per mmio to
> once per forcewake section when we are doing the general wellbeing
> check rather than the targetted error detection. This almost reduces
> the overhead of the debug facility (for example when submitting execlists)
> to zero whilst keeping the debug checks around.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Unfortunately the unclaimed reg stuff is most useful for debugging display
power well issues (it catches those while nothing else really does), and
this removes that facility. Can't we do tricks with using raw reads/writes
for forcewaked registers or something like that?
-Daniel
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 47 ++++++++++++++++++++-----------------
> 1 file changed, 26 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index ab5cc94588e1..6b065592aede 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -149,6 +149,30 @@ fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_doma
> }
>
> static void
> +hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
> +{
> + static bool mmio_debug_once = true;
> +
> + if (i915.mmio_debug || !mmio_debug_once)
> + return;
> +
> + if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
> + DRM_DEBUG("Unclaimed register detected, "
> + "enabling oneshot unclaimed register reporting. "
> + "Please use i915.mmio_debug=N for more information.\n");
> + __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
> + i915.mmio_debug = mmio_debug_once--;
> + }
> +}
> +
> +static void
> +fw_domains_put_debug(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
> +{
> + hsw_unclaimed_reg_detect(dev_priv);
> + fw_domains_put(dev_priv, fw_domains);
> +}
> +
> +static void
> fw_domains_posting_read(struct drm_i915_private *dev_priv)
> {
> struct intel_uncore_forcewake_domain *d;
> @@ -561,23 +585,6 @@ hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
> }
> }
>
> -static void
> -hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
> -{
> - static bool mmio_debug_once = true;
> -
> - if (i915.mmio_debug || !mmio_debug_once)
> - return;
> -
> - if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
> - DRM_DEBUG("Unclaimed register detected, "
> - "enabling oneshot unclaimed register reporting. "
> - "Please use i915.mmio_debug=N for more information.\n");
> - __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
> - i915.mmio_debug = mmio_debug_once--;
> - }
> -}
> -
> #define GEN2_READ_HEADER(x) \
> u##x val = 0; \
> assert_device_not_suspended(dev_priv);
> @@ -829,7 +836,6 @@ hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace)
> gen6_gt_check_fifodbg(dev_priv); \
> } \
> hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
> - hsw_unclaimed_reg_detect(dev_priv); \
> GEN6_WRITE_FOOTER; \
> }
>
> @@ -871,7 +877,6 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
> __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
> __raw_i915_write##x(dev_priv, reg, val); \
> hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
> - hsw_unclaimed_reg_detect(dev_priv); \
> GEN6_WRITE_FOOTER; \
> }
>
> @@ -1043,7 +1048,7 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
>
> if (IS_GEN9(dev)) {
> dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
> - dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
> + dev_priv->uncore.funcs.force_wake_put = fw_domains_put_debug;
> fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
> FORCEWAKE_RENDER_GEN9,
> FORCEWAKE_ACK_RENDER_GEN9);
> @@ -1066,7 +1071,7 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
> } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> dev_priv->uncore.funcs.force_wake_get =
> fw_domains_get_with_thread_status;
> - dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
> + dev_priv->uncore.funcs.force_wake_put = fw_domains_put_debug;
> fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
> FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
> } else if (IS_IVYBRIDGE(dev)) {
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915: Reduce frequency of unspecific HSW reg debugging
2015-03-23 9:35 ` Daniel Vetter
@ 2015-03-23 9:43 ` Chris Wilson
2015-03-23 9:47 ` Chris Wilson
0 siblings, 1 reply; 8+ messages in thread
From: Chris Wilson @ 2015-03-23 9:43 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, Paulo Zanoni, Mika Kuoppala
On Mon, Mar 23, 2015 at 10:35:16AM +0100, Daniel Vetter wrote:
> On Sun, Mar 22, 2015 at 03:41:04PM +0000, Chris Wilson wrote:
> > Delay the expensive read on the FPGA_DBG register from once per mmio to
> > once per forcewake section when we are doing the general wellbeing
> > check rather than the targetted error detection. This almost reduces
> > the overhead of the debug facility (for example when submitting execlists)
> > to zero whilst keeping the debug checks around.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Unfortunately the unclaimed reg stuff is most useful for debugging display
> power well issues (it catches those while nothing else really does), and
> this removes that facility. Can't we do tricks with using raw reads/writes
> for forcewaked registers or something like that?
How about beefing up intel_uncore_check_errors() to enable one-shot
mmio_debug as well? Then if it is an i915 error we would catch it on the
next cycle.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: Reduce frequency of unspecific HSW reg debugging
2015-03-23 9:43 ` Chris Wilson
@ 2015-03-23 9:47 ` Chris Wilson
0 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2015-03-23 9:47 UTC (permalink / raw)
To: Daniel Vetter, intel-gfx, Mika Kuoppala, Paulo Zanoni
On Mon, Mar 23, 2015 at 09:43:19AM +0000, Chris Wilson wrote:
> On Mon, Mar 23, 2015 at 10:35:16AM +0100, Daniel Vetter wrote:
> > On Sun, Mar 22, 2015 at 03:41:04PM +0000, Chris Wilson wrote:
> > > Delay the expensive read on the FPGA_DBG register from once per mmio to
> > > once per forcewake section when we are doing the general wellbeing
> > > check rather than the targetted error detection. This almost reduces
> > > the overhead of the debug facility (for example when submitting execlists)
> > > to zero whilst keeping the debug checks around.
> > >
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >
> > Unfortunately the unclaimed reg stuff is most useful for debugging display
> > power well issues (it catches those while nothing else really does), and
> > this removes that facility. Can't we do tricks with using raw reads/writes
> > for forcewaked registers or something like that?
>
> How about beefing up intel_uncore_check_errors() to enable one-shot
> mmio_debug as well? Then if it is an i915 error we would catch it on the
> next cycle.
So something like:
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 6b065592aede..a10bf6a5c55b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1416,11 +1416,6 @@ int intel_gpu_reset(struct drm_device *dev)
void intel_uncore_check_errors(struct drm_device *dev)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
-
- if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
- (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
- DRM_ERROR("Unclaimed register before interrupt\n");
- __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
- }
+ if (HAS_FPGA_DBG_UNCLAIMED(dev))
+ hsw_unclaimed_reg_detect(to_i915(dev));
}
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2015-08-26 15:49 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-08-26 7:52 [PATCH] drm/i915: Reduce frequency of unspecific HSW reg debugging Chris Wilson
2015-08-26 15:27 ` Mika Kuoppala
2015-08-26 15:49 ` Chris Wilson
-- strict thread matches above, loose matches on Subject: below --
2015-03-22 15:41 Chris Wilson
2015-03-22 18:38 ` shuang.he
2015-03-23 9:35 ` Daniel Vetter
2015-03-23 9:43 ` Chris Wilson
2015-03-23 9:47 ` Chris Wilson
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