* [PATCH i-g-t] quick_dump/skl: Add more pipe/plane registers @ 2015-05-11 18:36 Damien Lespiau 2015-05-12 6:50 ` Daniel Vetter 0 siblings, 1 reply; 5+ messages in thread From: Damien Lespiau @ 2015-05-11 18:36 UTC (permalink / raw) To: intel-gfx With the recent developments, add scaler and NV12 registers to the dump. Also add the cursor registers that were missing in the first batch. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> --- tools/quick_dump/skl_display.txt | 97 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/tools/quick_dump/skl_display.txt b/tools/quick_dump/skl_display.txt index 29f6524..37c7d99 100644 --- a/tools/quick_dump/skl_display.txt +++ b/tools/quick_dump/skl_display.txt @@ -20,6 +20,9 @@ ('PLANE_BUF_CFG_1_A', '0x7027c', '') ('PLANE_BUF_CFG_2_A', '0x7037c', '') ('PLANE_BUF_CFG_3_A', '0x7047c', '') +('PLANE_NV12_BUF_CFG_1_A', '0x70278', '') +('PLANE_NV12_BUF_CFG_2_A', '0x70378', '') +('PLANE_NV12_BUF_CFG_3_A', '0x70478', '') ('PLANE_CTL_1_A', '0x70180', '') ('PLANE_CTL_2_A', '0x70280', '') ('PLANE_CTL_3_A', '0x70380', '') @@ -35,6 +38,9 @@ ('PLANE_OFFSET_1_A', '0x701a4', '') ('PLANE_OFFSET_2_A', '0x702a4', '') ('PLANE_OFFSET_3_A', '0x703a4', '') +('PLANE_AUX_OFFSET_1_A', '0x701c4', '') +('PLANE_AUX_OFFSET_2_A', '0x702c4', '') +('PLANE_AUX_OFFSET_3_A', '0x703c4', '') ('PLANE_POS_1_A', '0x7018c', '') ('PLANE_POS_2_A', '0x7028c', '') ('PLANE_POS_3_A', '0x7038c', '') @@ -77,10 +83,42 @@ ('PLANE_WM_TRANS_1_A', '0x70268', '') ('PLANE_WM_TRANS_2_A', '0x70368', '') ('PLANE_WM_TRANS_3_A', '0x70468', '') +# PIPE_A_CURSOR_PLANE +('CUR_BUF_CFG_A', '0x7017c', '') +('CUR_BASE_A', '0x70084', '') +('CUR_CTL_A', '0x70080', '') +('CUR_FBC_CTL_A', '0x700a0', '') +('CUR_PAL_A_*', '0x70090', '') +('CUR_POS_A', '0x70088', '') +('CUR_SURFLIVE_A', '0x700ac', '') +('CUR_WM_A_*', '0x70140', '') +('CUR_WM_TRANS_A', '0x70168', '') +# PIPE_SCALER_A +('PS_CTRL_1_A', '0x68180', '') +('PS_CTRL_2_A', '0x68280', '') +('PS_ECC_STAT_1_A', '0x681d0', '') +('PS_ECC_STAT_2_A', '0x682d0', '') +('PS_HPHASE_1_A', '0x68194', '') +('PS_HPHASE_2_A', '0x68294', '') +('PS_HSCALE_1_A', '0x68190', '') +('PS_HSCALE_2_A', '0x68290', '') +('PS_PWR_GATE_1_A', '0x68160', '') +('PS_PWR_GATE_2_A', '0x68260', '') +('PS_VPHASE_1_A', '0x68188', '') +('PS_VPHASE_2_A', '0x68288', '') +('PS_VSCALE_1_A', '0x68184', '') +('PS_VSCALE_2_A', '0x68284', '') +('PS_WIN_POS_1_A', '0x68170', '') +('PS_WIN_POS_2_A', '0x68270', '') +('PS_WIN_SZ_1_A', '0x68174', '') +('PS_WIN_SZ_2_A', '0x68274', '') # PIPE_B_PLANE ('PLANE_BUF_CFG_1_B', '0x7127c', '') ('PLANE_BUF_CFG_2_B', '0x7137c', '') ('PLANE_BUF_CFG_3_B', '0x7147c', '') +('PLANE_NV12_BUF_CFG_1_B', '0x71278', '') +('PLANE_NV12_BUF_CFG_2_B', '0x71378', '') +('PLANE_NV12_BUF_CFG_3_B', '0x71478', '') ('PLANE_CTL_1_B', '0x71180', '') ('PLANE_CTL_2_B', '0x71280', '') ('PLANE_CTL_3_B', '0x71380', '') @@ -96,6 +134,9 @@ ('PLANE_OFFSET_1_B', '0x711a4', '') ('PLANE_OFFSET_2_B', '0x712a4', '') ('PLANE_OFFSET_3_B', '0x713a4', '') +('PLANE_AUX_OFFSET_1_B', '0x711c4', '') +('PLANE_AUX_OFFSET_2_B', '0x712c4', '') +('PLANE_AUX_OFFSET_3_B', '0x713c4', '') ('PLANE_POS_1_B', '0x7118c', '') ('PLANE_POS_2_B', '0x7128c', '') ('PLANE_POS_3_B', '0x7138c', '') @@ -138,10 +179,43 @@ ('PLANE_WM_TRANS_1_B', '0x71268', '') ('PLANE_WM_TRANS_2_B', '0x71368', '') ('PLANE_WM_TRANS_3_B', '0x71468', '') +# PIPE_B_CURSOR_PLANE +('CUR_BUF_CFG_B', '0x7117c', '') +('CUR_BASE_B', '0x71084', '') +('CUR_CTL_B', '0x71080', '') +('CUR_FBC_CTL_B', '0x710a0', '') +('CUR_PAL_B_*', '0x71090', '') +('CUR_POS_B', '0x71088', '') +('CUR_SURFLIVE_B', '0x710ac', '') +('CUR_WM_B_*', '0x71140', '') +('CUR_WM_TRANS_B', '0x71168', '') +# PIPE_SCALER_B +('PS_CTRL_1_B', '0x68980', '') +('PS_CTRL_2_B', '0x68a80', '') +('PS_ECC_STAT_1_B', '0x689d0', '') +('PS_ECC_STAT_2_B', '0x68ad0', '') +('PS_HPHASE_1_B', '0x68994', '') +('PS_HPHASE_2_B', '0x68a94', '') +('PS_HSCALE_1_B', '0x68990', '') +('PS_HSCALE_2_B', '0x68a90', '') +('PS_PWR_GATE_1_B', '0x68960', '') +('PS_PWR_GATE_2_B', '0x68a60', '') +('PS_VPHASE_1_B', '0x68988', '') +('PS_VPHASE_2_B', '0x68a88', '') +('PS_VSCALE_1_B', '0x68984', '') +('PS_VSCALE_2_B', '0x68a84', '') +('PS_WIN_POS_1_B', '0x68970', '') +('PS_WIN_POS_2_B', '0x68a70', '') # PIPE_C_PLANE ('PLANE_BUF_CFG_1_C', '0x7227c', '') ('PLANE_BUF_CFG_2_C', '0x7237c', '') ('PLANE_BUF_CFG_3_C', '0x7247c', '') +('PLANE_NV12_BUF_CFG_1_C', '0x72278', '') +('PLANE_NV12_BUF_CFG_2_C', '0x72378', '') +('PLANE_NV12_BUF_CFG_3_C', '0x72478', '') +('PLANE_AUX_DIST_1_C', '0x721c0', '') +('PLANE_AUX_DIST_2_C', '0x722c0', '') +('PLANE_AUX_DIST_3_C', '0x723c0', '') ('PLANE_CTL_1_C', '0x72180', '') ('PLANE_CTL_2_C', '0x72280', '') ('PLANE_CTL_3_C', '0x72380', '') @@ -157,6 +231,9 @@ ('PLANE_OFFSET_1_C', '0x721a4', '') ('PLANE_OFFSET_2_C', '0x722a4', '') ('PLANE_OFFSET_3_C', '0x723a4', '') +('PLANE_AUX_OFFSET_1_C', '0x721c4', '') +('PLANE_AUX_OFFSET_2_C', '0x722c4', '') +('PLANE_AUX_OFFSET_3_C', '0x723c4', '') ('PLANE_POS_1_C', '0x7218c', '') ('PLANE_POS_2_C', '0x7228c', '') ('PLANE_POS_3_C', '0x7238c', '') @@ -199,6 +276,26 @@ ('PLANE_WM_TRANS_1_C', '0x72268', '') ('PLANE_WM_TRANS_2_C', '0x72368', '') ('PLANE_WM_TRANS_3_C', '0x72468', '') +# PIPE_C_CURSOR_PLANE +('CUR_BUF_CFG_C', '0x7217c', '') +('CUR_BASE_C', '0x72084', '') +('CUR_CTL_C', '0x72080', '') +('CUR_FBC_CTL_C', '0x720a0', '') +('CUR_PAL_C_*', '0x72090', '') +('CUR_POS_C', '0x72088', '') +('CUR_SURFLIVE_C', '0x720ac', '') +('CUR_WM_C_*', '0x72140', '') +('CUR_WM_TRANS_C', '0x72168', '') +# PIPE_SCALER_C +('PS_CTRL_1_C', '0x69180', '') +('PS_ECC_STAT_1_C', '0x691d0', '') +('PS_HPHASE_1_C', '0x69194', '') +('PS_HSCALE_1_C', '0x69190', '') +('PS_PWR_GATE_1_C', '0x69160', '') +('PS_VPHASE_1_C', '0x69188', '') +('PS_VSCALE_1_C', '0x69184', '') +('PS_WIN_POS_1_C', '0x69170', '') +('PS_WIN_SZ_1_C', '0x69174', '') # TRANSCODER_EDP_CONTROL ('TRANS_CONF_EDP', '0x7f008', '') # TRANSCODER_EDP_TIMING -- 2.1.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH i-g-t] quick_dump/skl: Add more pipe/plane registers 2015-05-11 18:36 [PATCH i-g-t] quick_dump/skl: Add more pipe/plane registers Damien Lespiau @ 2015-05-12 6:50 ` Daniel Vetter 2015-05-12 8:58 ` Jani Nikula 0 siblings, 1 reply; 5+ messages in thread From: Daniel Vetter @ 2015-05-12 6:50 UTC (permalink / raw) To: Damien Lespiau; +Cc: intel-gfx On Mon, May 11, 2015 at 07:36:07PM +0100, Damien Lespiau wrote: > With the recent developments, add scaler and NV12 registers to the dump. > Also add the cursor registers that were missing in the first batch. > > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Jani has this shiny new swiss army knive tool now ... -Daniel > --- > tools/quick_dump/skl_display.txt | 97 ++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 97 insertions(+) > > diff --git a/tools/quick_dump/skl_display.txt b/tools/quick_dump/skl_display.txt > index 29f6524..37c7d99 100644 > --- a/tools/quick_dump/skl_display.txt > +++ b/tools/quick_dump/skl_display.txt > @@ -20,6 +20,9 @@ > ('PLANE_BUF_CFG_1_A', '0x7027c', '') > ('PLANE_BUF_CFG_2_A', '0x7037c', '') > ('PLANE_BUF_CFG_3_A', '0x7047c', '') > +('PLANE_NV12_BUF_CFG_1_A', '0x70278', '') > +('PLANE_NV12_BUF_CFG_2_A', '0x70378', '') > +('PLANE_NV12_BUF_CFG_3_A', '0x70478', '') > ('PLANE_CTL_1_A', '0x70180', '') > ('PLANE_CTL_2_A', '0x70280', '') > ('PLANE_CTL_3_A', '0x70380', '') > @@ -35,6 +38,9 @@ > ('PLANE_OFFSET_1_A', '0x701a4', '') > ('PLANE_OFFSET_2_A', '0x702a4', '') > ('PLANE_OFFSET_3_A', '0x703a4', '') > +('PLANE_AUX_OFFSET_1_A', '0x701c4', '') > +('PLANE_AUX_OFFSET_2_A', '0x702c4', '') > +('PLANE_AUX_OFFSET_3_A', '0x703c4', '') > ('PLANE_POS_1_A', '0x7018c', '') > ('PLANE_POS_2_A', '0x7028c', '') > ('PLANE_POS_3_A', '0x7038c', '') > @@ -77,10 +83,42 @@ > ('PLANE_WM_TRANS_1_A', '0x70268', '') > ('PLANE_WM_TRANS_2_A', '0x70368', '') > ('PLANE_WM_TRANS_3_A', '0x70468', '') > +# PIPE_A_CURSOR_PLANE > +('CUR_BUF_CFG_A', '0x7017c', '') > +('CUR_BASE_A', '0x70084', '') > +('CUR_CTL_A', '0x70080', '') > +('CUR_FBC_CTL_A', '0x700a0', '') > +('CUR_PAL_A_*', '0x70090', '') > +('CUR_POS_A', '0x70088', '') > +('CUR_SURFLIVE_A', '0x700ac', '') > +('CUR_WM_A_*', '0x70140', '') > +('CUR_WM_TRANS_A', '0x70168', '') > +# PIPE_SCALER_A > +('PS_CTRL_1_A', '0x68180', '') > +('PS_CTRL_2_A', '0x68280', '') > +('PS_ECC_STAT_1_A', '0x681d0', '') > +('PS_ECC_STAT_2_A', '0x682d0', '') > +('PS_HPHASE_1_A', '0x68194', '') > +('PS_HPHASE_2_A', '0x68294', '') > +('PS_HSCALE_1_A', '0x68190', '') > +('PS_HSCALE_2_A', '0x68290', '') > +('PS_PWR_GATE_1_A', '0x68160', '') > +('PS_PWR_GATE_2_A', '0x68260', '') > +('PS_VPHASE_1_A', '0x68188', '') > +('PS_VPHASE_2_A', '0x68288', '') > +('PS_VSCALE_1_A', '0x68184', '') > +('PS_VSCALE_2_A', '0x68284', '') > +('PS_WIN_POS_1_A', '0x68170', '') > +('PS_WIN_POS_2_A', '0x68270', '') > +('PS_WIN_SZ_1_A', '0x68174', '') > +('PS_WIN_SZ_2_A', '0x68274', '') > # PIPE_B_PLANE > ('PLANE_BUF_CFG_1_B', '0x7127c', '') > ('PLANE_BUF_CFG_2_B', '0x7137c', '') > ('PLANE_BUF_CFG_3_B', '0x7147c', '') > +('PLANE_NV12_BUF_CFG_1_B', '0x71278', '') > +('PLANE_NV12_BUF_CFG_2_B', '0x71378', '') > +('PLANE_NV12_BUF_CFG_3_B', '0x71478', '') > ('PLANE_CTL_1_B', '0x71180', '') > ('PLANE_CTL_2_B', '0x71280', '') > ('PLANE_CTL_3_B', '0x71380', '') > @@ -96,6 +134,9 @@ > ('PLANE_OFFSET_1_B', '0x711a4', '') > ('PLANE_OFFSET_2_B', '0x712a4', '') > ('PLANE_OFFSET_3_B', '0x713a4', '') > +('PLANE_AUX_OFFSET_1_B', '0x711c4', '') > +('PLANE_AUX_OFFSET_2_B', '0x712c4', '') > +('PLANE_AUX_OFFSET_3_B', '0x713c4', '') > ('PLANE_POS_1_B', '0x7118c', '') > ('PLANE_POS_2_B', '0x7128c', '') > ('PLANE_POS_3_B', '0x7138c', '') > @@ -138,10 +179,43 @@ > ('PLANE_WM_TRANS_1_B', '0x71268', '') > ('PLANE_WM_TRANS_2_B', '0x71368', '') > ('PLANE_WM_TRANS_3_B', '0x71468', '') > +# PIPE_B_CURSOR_PLANE > +('CUR_BUF_CFG_B', '0x7117c', '') > +('CUR_BASE_B', '0x71084', '') > +('CUR_CTL_B', '0x71080', '') > +('CUR_FBC_CTL_B', '0x710a0', '') > +('CUR_PAL_B_*', '0x71090', '') > +('CUR_POS_B', '0x71088', '') > +('CUR_SURFLIVE_B', '0x710ac', '') > +('CUR_WM_B_*', '0x71140', '') > +('CUR_WM_TRANS_B', '0x71168', '') > +# PIPE_SCALER_B > +('PS_CTRL_1_B', '0x68980', '') > +('PS_CTRL_2_B', '0x68a80', '') > +('PS_ECC_STAT_1_B', '0x689d0', '') > +('PS_ECC_STAT_2_B', '0x68ad0', '') > +('PS_HPHASE_1_B', '0x68994', '') > +('PS_HPHASE_2_B', '0x68a94', '') > +('PS_HSCALE_1_B', '0x68990', '') > +('PS_HSCALE_2_B', '0x68a90', '') > +('PS_PWR_GATE_1_B', '0x68960', '') > +('PS_PWR_GATE_2_B', '0x68a60', '') > +('PS_VPHASE_1_B', '0x68988', '') > +('PS_VPHASE_2_B', '0x68a88', '') > +('PS_VSCALE_1_B', '0x68984', '') > +('PS_VSCALE_2_B', '0x68a84', '') > +('PS_WIN_POS_1_B', '0x68970', '') > +('PS_WIN_POS_2_B', '0x68a70', '') > # PIPE_C_PLANE > ('PLANE_BUF_CFG_1_C', '0x7227c', '') > ('PLANE_BUF_CFG_2_C', '0x7237c', '') > ('PLANE_BUF_CFG_3_C', '0x7247c', '') > +('PLANE_NV12_BUF_CFG_1_C', '0x72278', '') > +('PLANE_NV12_BUF_CFG_2_C', '0x72378', '') > +('PLANE_NV12_BUF_CFG_3_C', '0x72478', '') > +('PLANE_AUX_DIST_1_C', '0x721c0', '') > +('PLANE_AUX_DIST_2_C', '0x722c0', '') > +('PLANE_AUX_DIST_3_C', '0x723c0', '') > ('PLANE_CTL_1_C', '0x72180', '') > ('PLANE_CTL_2_C', '0x72280', '') > ('PLANE_CTL_3_C', '0x72380', '') > @@ -157,6 +231,9 @@ > ('PLANE_OFFSET_1_C', '0x721a4', '') > ('PLANE_OFFSET_2_C', '0x722a4', '') > ('PLANE_OFFSET_3_C', '0x723a4', '') > +('PLANE_AUX_OFFSET_1_C', '0x721c4', '') > +('PLANE_AUX_OFFSET_2_C', '0x722c4', '') > +('PLANE_AUX_OFFSET_3_C', '0x723c4', '') > ('PLANE_POS_1_C', '0x7218c', '') > ('PLANE_POS_2_C', '0x7228c', '') > ('PLANE_POS_3_C', '0x7238c', '') > @@ -199,6 +276,26 @@ > ('PLANE_WM_TRANS_1_C', '0x72268', '') > ('PLANE_WM_TRANS_2_C', '0x72368', '') > ('PLANE_WM_TRANS_3_C', '0x72468', '') > +# PIPE_C_CURSOR_PLANE > +('CUR_BUF_CFG_C', '0x7217c', '') > +('CUR_BASE_C', '0x72084', '') > +('CUR_CTL_C', '0x72080', '') > +('CUR_FBC_CTL_C', '0x720a0', '') > +('CUR_PAL_C_*', '0x72090', '') > +('CUR_POS_C', '0x72088', '') > +('CUR_SURFLIVE_C', '0x720ac', '') > +('CUR_WM_C_*', '0x72140', '') > +('CUR_WM_TRANS_C', '0x72168', '') > +# PIPE_SCALER_C > +('PS_CTRL_1_C', '0x69180', '') > +('PS_ECC_STAT_1_C', '0x691d0', '') > +('PS_HPHASE_1_C', '0x69194', '') > +('PS_HSCALE_1_C', '0x69190', '') > +('PS_PWR_GATE_1_C', '0x69160', '') > +('PS_VPHASE_1_C', '0x69188', '') > +('PS_VSCALE_1_C', '0x69184', '') > +('PS_WIN_POS_1_C', '0x69170', '') > +('PS_WIN_SZ_1_C', '0x69174', '') > # TRANSCODER_EDP_CONTROL > ('TRANS_CONF_EDP', '0x7f008', '') > # TRANSCODER_EDP_TIMING > -- > 2.1.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH i-g-t] quick_dump/skl: Add more pipe/plane registers 2015-05-12 6:50 ` Daniel Vetter @ 2015-05-12 8:58 ` Jani Nikula 2015-06-10 10:30 ` [PATCH i-g-t] intel_reg: install and load the register files Thomas Wood 0 siblings, 1 reply; 5+ messages in thread From: Jani Nikula @ 2015-05-12 8:58 UTC (permalink / raw) To: Daniel Vetter, Damien Lespiau; +Cc: intel-gfx, Wood, Thomas On Tue, 12 May 2015, Daniel Vetter <daniel@ffwll.ch> wrote: > On Mon, May 11, 2015 at 07:36:07PM +0100, Damien Lespiau wrote: >> With the recent developments, add scaler and NV12 registers to the dump. >> Also add the cursor registers that were missing in the first batch. >> >> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> > > Jani has this shiny new swiss army knive tool now ... ...which reuses the quick dump register definitions. I wonder if we should a) install the quick dump definitions, and b) have intel_reg check the install location for the files (this should be a trivial modification). Thomas? BR, Jani. > -Daniel > >> --- >> tools/quick_dump/skl_display.txt | 97 ++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 97 insertions(+) >> >> diff --git a/tools/quick_dump/skl_display.txt b/tools/quick_dump/skl_display.txt >> index 29f6524..37c7d99 100644 >> --- a/tools/quick_dump/skl_display.txt >> +++ b/tools/quick_dump/skl_display.txt >> @@ -20,6 +20,9 @@ >> ('PLANE_BUF_CFG_1_A', '0x7027c', '') >> ('PLANE_BUF_CFG_2_A', '0x7037c', '') >> ('PLANE_BUF_CFG_3_A', '0x7047c', '') >> +('PLANE_NV12_BUF_CFG_1_A', '0x70278', '') >> +('PLANE_NV12_BUF_CFG_2_A', '0x70378', '') >> +('PLANE_NV12_BUF_CFG_3_A', '0x70478', '') >> ('PLANE_CTL_1_A', '0x70180', '') >> ('PLANE_CTL_2_A', '0x70280', '') >> ('PLANE_CTL_3_A', '0x70380', '') >> @@ -35,6 +38,9 @@ >> ('PLANE_OFFSET_1_A', '0x701a4', '') >> ('PLANE_OFFSET_2_A', '0x702a4', '') >> ('PLANE_OFFSET_3_A', '0x703a4', '') >> +('PLANE_AUX_OFFSET_1_A', '0x701c4', '') >> +('PLANE_AUX_OFFSET_2_A', '0x702c4', '') >> +('PLANE_AUX_OFFSET_3_A', '0x703c4', '') >> ('PLANE_POS_1_A', '0x7018c', '') >> ('PLANE_POS_2_A', '0x7028c', '') >> ('PLANE_POS_3_A', '0x7038c', '') >> @@ -77,10 +83,42 @@ >> ('PLANE_WM_TRANS_1_A', '0x70268', '') >> ('PLANE_WM_TRANS_2_A', '0x70368', '') >> ('PLANE_WM_TRANS_3_A', '0x70468', '') >> +# PIPE_A_CURSOR_PLANE >> +('CUR_BUF_CFG_A', '0x7017c', '') >> +('CUR_BASE_A', '0x70084', '') >> +('CUR_CTL_A', '0x70080', '') >> +('CUR_FBC_CTL_A', '0x700a0', '') >> +('CUR_PAL_A_*', '0x70090', '') >> +('CUR_POS_A', '0x70088', '') >> +('CUR_SURFLIVE_A', '0x700ac', '') >> +('CUR_WM_A_*', '0x70140', '') >> +('CUR_WM_TRANS_A', '0x70168', '') >> +# PIPE_SCALER_A >> +('PS_CTRL_1_A', '0x68180', '') >> +('PS_CTRL_2_A', '0x68280', '') >> +('PS_ECC_STAT_1_A', '0x681d0', '') >> +('PS_ECC_STAT_2_A', '0x682d0', '') >> +('PS_HPHASE_1_A', '0x68194', '') >> +('PS_HPHASE_2_A', '0x68294', '') >> +('PS_HSCALE_1_A', '0x68190', '') >> +('PS_HSCALE_2_A', '0x68290', '') >> +('PS_PWR_GATE_1_A', '0x68160', '') >> +('PS_PWR_GATE_2_A', '0x68260', '') >> +('PS_VPHASE_1_A', '0x68188', '') >> +('PS_VPHASE_2_A', '0x68288', '') >> +('PS_VSCALE_1_A', '0x68184', '') >> +('PS_VSCALE_2_A', '0x68284', '') >> +('PS_WIN_POS_1_A', '0x68170', '') >> +('PS_WIN_POS_2_A', '0x68270', '') >> +('PS_WIN_SZ_1_A', '0x68174', '') >> +('PS_WIN_SZ_2_A', '0x68274', '') >> # PIPE_B_PLANE >> ('PLANE_BUF_CFG_1_B', '0x7127c', '') >> ('PLANE_BUF_CFG_2_B', '0x7137c', '') >> ('PLANE_BUF_CFG_3_B', '0x7147c', '') >> +('PLANE_NV12_BUF_CFG_1_B', '0x71278', '') >> +('PLANE_NV12_BUF_CFG_2_B', '0x71378', '') >> +('PLANE_NV12_BUF_CFG_3_B', '0x71478', '') >> ('PLANE_CTL_1_B', '0x71180', '') >> ('PLANE_CTL_2_B', '0x71280', '') >> ('PLANE_CTL_3_B', '0x71380', '') >> @@ -96,6 +134,9 @@ >> ('PLANE_OFFSET_1_B', '0x711a4', '') >> ('PLANE_OFFSET_2_B', '0x712a4', '') >> ('PLANE_OFFSET_3_B', '0x713a4', '') >> +('PLANE_AUX_OFFSET_1_B', '0x711c4', '') >> +('PLANE_AUX_OFFSET_2_B', '0x712c4', '') >> +('PLANE_AUX_OFFSET_3_B', '0x713c4', '') >> ('PLANE_POS_1_B', '0x7118c', '') >> ('PLANE_POS_2_B', '0x7128c', '') >> ('PLANE_POS_3_B', '0x7138c', '') >> @@ -138,10 +179,43 @@ >> ('PLANE_WM_TRANS_1_B', '0x71268', '') >> ('PLANE_WM_TRANS_2_B', '0x71368', '') >> ('PLANE_WM_TRANS_3_B', '0x71468', '') >> +# PIPE_B_CURSOR_PLANE >> +('CUR_BUF_CFG_B', '0x7117c', '') >> +('CUR_BASE_B', '0x71084', '') >> +('CUR_CTL_B', '0x71080', '') >> +('CUR_FBC_CTL_B', '0x710a0', '') >> +('CUR_PAL_B_*', '0x71090', '') >> +('CUR_POS_B', '0x71088', '') >> +('CUR_SURFLIVE_B', '0x710ac', '') >> +('CUR_WM_B_*', '0x71140', '') >> +('CUR_WM_TRANS_B', '0x71168', '') >> +# PIPE_SCALER_B >> +('PS_CTRL_1_B', '0x68980', '') >> +('PS_CTRL_2_B', '0x68a80', '') >> +('PS_ECC_STAT_1_B', '0x689d0', '') >> +('PS_ECC_STAT_2_B', '0x68ad0', '') >> +('PS_HPHASE_1_B', '0x68994', '') >> +('PS_HPHASE_2_B', '0x68a94', '') >> +('PS_HSCALE_1_B', '0x68990', '') >> +('PS_HSCALE_2_B', '0x68a90', '') >> +('PS_PWR_GATE_1_B', '0x68960', '') >> +('PS_PWR_GATE_2_B', '0x68a60', '') >> +('PS_VPHASE_1_B', '0x68988', '') >> +('PS_VPHASE_2_B', '0x68a88', '') >> +('PS_VSCALE_1_B', '0x68984', '') >> +('PS_VSCALE_2_B', '0x68a84', '') >> +('PS_WIN_POS_1_B', '0x68970', '') >> +('PS_WIN_POS_2_B', '0x68a70', '') >> # PIPE_C_PLANE >> ('PLANE_BUF_CFG_1_C', '0x7227c', '') >> ('PLANE_BUF_CFG_2_C', '0x7237c', '') >> ('PLANE_BUF_CFG_3_C', '0x7247c', '') >> +('PLANE_NV12_BUF_CFG_1_C', '0x72278', '') >> +('PLANE_NV12_BUF_CFG_2_C', '0x72378', '') >> +('PLANE_NV12_BUF_CFG_3_C', '0x72478', '') >> +('PLANE_AUX_DIST_1_C', '0x721c0', '') >> +('PLANE_AUX_DIST_2_C', '0x722c0', '') >> +('PLANE_AUX_DIST_3_C', '0x723c0', '') >> ('PLANE_CTL_1_C', '0x72180', '') >> ('PLANE_CTL_2_C', '0x72280', '') >> ('PLANE_CTL_3_C', '0x72380', '') >> @@ -157,6 +231,9 @@ >> ('PLANE_OFFSET_1_C', '0x721a4', '') >> ('PLANE_OFFSET_2_C', '0x722a4', '') >> ('PLANE_OFFSET_3_C', '0x723a4', '') >> +('PLANE_AUX_OFFSET_1_C', '0x721c4', '') >> +('PLANE_AUX_OFFSET_2_C', '0x722c4', '') >> +('PLANE_AUX_OFFSET_3_C', '0x723c4', '') >> ('PLANE_POS_1_C', '0x7218c', '') >> ('PLANE_POS_2_C', '0x7228c', '') >> ('PLANE_POS_3_C', '0x7238c', '') >> @@ -199,6 +276,26 @@ >> ('PLANE_WM_TRANS_1_C', '0x72268', '') >> ('PLANE_WM_TRANS_2_C', '0x72368', '') >> ('PLANE_WM_TRANS_3_C', '0x72468', '') >> +# PIPE_C_CURSOR_PLANE >> +('CUR_BUF_CFG_C', '0x7217c', '') >> +('CUR_BASE_C', '0x72084', '') >> +('CUR_CTL_C', '0x72080', '') >> +('CUR_FBC_CTL_C', '0x720a0', '') >> +('CUR_PAL_C_*', '0x72090', '') >> +('CUR_POS_C', '0x72088', '') >> +('CUR_SURFLIVE_C', '0x720ac', '') >> +('CUR_WM_C_*', '0x72140', '') >> +('CUR_WM_TRANS_C', '0x72168', '') >> +# PIPE_SCALER_C >> +('PS_CTRL_1_C', '0x69180', '') >> +('PS_ECC_STAT_1_C', '0x691d0', '') >> +('PS_HPHASE_1_C', '0x69194', '') >> +('PS_HSCALE_1_C', '0x69190', '') >> +('PS_PWR_GATE_1_C', '0x69160', '') >> +('PS_VPHASE_1_C', '0x69188', '') >> +('PS_VSCALE_1_C', '0x69184', '') >> +('PS_WIN_POS_1_C', '0x69170', '') >> +('PS_WIN_SZ_1_C', '0x69174', '') >> # TRANSCODER_EDP_CONTROL >> ('TRANS_CONF_EDP', '0x7f008', '') >> # TRANSCODER_EDP_TIMING >> -- >> 2.1.0 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH i-g-t] intel_reg: install and load the register files 2015-05-12 8:58 ` Jani Nikula @ 2015-06-10 10:30 ` Thomas Wood 2015-06-15 13:12 ` Thomas Wood 0 siblings, 1 reply; 5+ messages in thread From: Thomas Wood @ 2015-06-10 10:30 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Thomas Wood <thomas.wood@intel.com> --- configure.ac | 5 +++-- tools/Makefile.am | 3 ++- tools/intel_reg.c | 4 ++-- tools/quick_dump/Makefile.am | 13 ++++++++----- 4 files changed, 15 insertions(+), 10 deletions(-) diff --git a/configure.ac b/configure.ac index c370ec3..33caddc 100644 --- a/configure.ac +++ b/configure.ac @@ -230,9 +230,10 @@ AC_DEFINE_UNQUOTED(TARGET_CPU_PLATFORM, ["$host_cpu"], [Target platform]) files="broadwell cherryview haswell ivybridge sandybridge valleyview skylake" for file in $files; do - QUICK_DUMP_EXTRA_DIST="$QUICK_DUMP_EXTRA_DIST $file `tr '\n' ' ' < $srcdir/tools/quick_dump/$file`" + REGSPECFILES="$REGSPECFILES $file `cat $srcdir/tools/quick_dump/$file`" done -AC_SUBST(QUICK_DUMP_EXTRA_DIST) +REGSPECFILES=`echo $REGSPECFILES | tr ' ' '\n' | sort -u | tr '\n' ' '` +AC_SUBST(REGSPECFILES) AC_CONFIG_FILES([ Makefile diff --git a/tools/Makefile.am b/tools/Makefile.am index 04bfd12..f673f3c 100644 --- a/tools/Makefile.am +++ b/tools/Makefile.am @@ -7,6 +7,7 @@ SUBDIRS += quick_dump endif AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/lib -AM_CFLAGS = $(DRM_CFLAGS) $(PCIACCESS_CFLAGS) $(CWARNFLAGS) $(CAIRO_CFLAGS) $(LIBUNWIND_CFLAGS) +AM_CFLAGS = $(DRM_CFLAGS) $(PCIACCESS_CFLAGS) $(CWARNFLAGS) $(CAIRO_CFLAGS) \ + $(LIBUNWIND_CFLAGS) -DREGSPECDIR=\"$(pkgdatadir)/registers\" LDADD = $(top_builddir)/lib/libintel_tools.la $(DRM_LIBS) $(PCIACCESS_LIBS) $(CAIRO_LIBS) $(LIBUDEV_LIBS) $(LIBUNWIND_LIBS) diff --git a/tools/intel_reg.c b/tools/intel_reg.c index 090cc25..66ec485 100644 --- a/tools/intel_reg.c +++ b/tools/intel_reg.c @@ -698,7 +698,7 @@ static int get_reg_spec_file(char *buf, size_t buflen, const char *dir, static int read_reg_spec(struct config *config) { char buf[PATH_MAX]; - char *path; + const char *path; struct stat st; int r; @@ -707,7 +707,7 @@ static int read_reg_spec(struct config *config) path = getenv("INTEL_REG_SPEC"); if (!path) - goto builtin; + path = REGSPECDIR; r = stat(path, &st); if (r) { diff --git a/tools/quick_dump/Makefile.am b/tools/quick_dump/Makefile.am index 3d0bd23..b526d19 100644 --- a/tools/quick_dump/Makefile.am +++ b/tools/quick_dump/Makefile.am @@ -25,9 +25,12 @@ chipset_wrap_python.c: chipset.i all-local: I915ChipsetPython.la $(LN_S) -f .libs/I915ChipsetPython.so _chipset.so +regspecdir = $(pkgdatadir)/registers +dist_regspec_DATA = $(REGSPECFILES) \ + base_interrupt.txt base_other.txt base_power.txt \ + base_rings.txt + CLEANFILES = chipset_wrap_python.c chipset.py _chipset.so -EXTRA_DIST = $(QUICK_DUMP_EXTRA_DIST) \ - base_interrupt.txt base_other.txt base_power.txt base_rings.txt \ - quick_dump.py \ - reg_access.py \ - chipset.i +EXTRA_DIST = quick_dump.py \ + reg_access.py \ + chipset.i -- 2.4.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH i-g-t] intel_reg: install and load the register files 2015-06-10 10:30 ` [PATCH i-g-t] intel_reg: install and load the register files Thomas Wood @ 2015-06-15 13:12 ` Thomas Wood 0 siblings, 0 replies; 5+ messages in thread From: Thomas Wood @ 2015-06-15 13:12 UTC (permalink / raw) To: Intel Graphics Development; +Cc: Jani Nikula On 10 June 2015 at 11:30, Thomas Wood <thomas.wood@intel.com> wrote: > Cc: Jani Nikula <jani.nikula@intel.com> > Signed-off-by: Thomas Wood <thomas.wood@intel.com> I haven't pushed this yet because there seems to be a discrepancy between the built in register list and that from the quick_dump files. Jani also suggested it may be a better idea to use the files to update the built in list so that the definitions are always included with the binary. > --- > configure.ac | 5 +++-- > tools/Makefile.am | 3 ++- > tools/intel_reg.c | 4 ++-- > tools/quick_dump/Makefile.am | 13 ++++++++----- > 4 files changed, 15 insertions(+), 10 deletions(-) > > diff --git a/configure.ac b/configure.ac > index c370ec3..33caddc 100644 > --- a/configure.ac > +++ b/configure.ac > @@ -230,9 +230,10 @@ AC_DEFINE_UNQUOTED(TARGET_CPU_PLATFORM, ["$host_cpu"], [Target platform]) > > files="broadwell cherryview haswell ivybridge sandybridge valleyview skylake" > for file in $files; do > - QUICK_DUMP_EXTRA_DIST="$QUICK_DUMP_EXTRA_DIST $file `tr '\n' ' ' < $srcdir/tools/quick_dump/$file`" > + REGSPECFILES="$REGSPECFILES $file `cat $srcdir/tools/quick_dump/$file`" > done > -AC_SUBST(QUICK_DUMP_EXTRA_DIST) > +REGSPECFILES=`echo $REGSPECFILES | tr ' ' '\n' | sort -u | tr '\n' ' '` > +AC_SUBST(REGSPECFILES) > > AC_CONFIG_FILES([ > Makefile > diff --git a/tools/Makefile.am b/tools/Makefile.am > index 04bfd12..f673f3c 100644 > --- a/tools/Makefile.am > +++ b/tools/Makefile.am > @@ -7,6 +7,7 @@ SUBDIRS += quick_dump > endif > > AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/lib > -AM_CFLAGS = $(DRM_CFLAGS) $(PCIACCESS_CFLAGS) $(CWARNFLAGS) $(CAIRO_CFLAGS) $(LIBUNWIND_CFLAGS) > +AM_CFLAGS = $(DRM_CFLAGS) $(PCIACCESS_CFLAGS) $(CWARNFLAGS) $(CAIRO_CFLAGS) \ > + $(LIBUNWIND_CFLAGS) -DREGSPECDIR=\"$(pkgdatadir)/registers\" > LDADD = $(top_builddir)/lib/libintel_tools.la $(DRM_LIBS) $(PCIACCESS_LIBS) $(CAIRO_LIBS) $(LIBUDEV_LIBS) $(LIBUNWIND_LIBS) > > diff --git a/tools/intel_reg.c b/tools/intel_reg.c > index 090cc25..66ec485 100644 > --- a/tools/intel_reg.c > +++ b/tools/intel_reg.c > @@ -698,7 +698,7 @@ static int get_reg_spec_file(char *buf, size_t buflen, const char *dir, > static int read_reg_spec(struct config *config) > { > char buf[PATH_MAX]; > - char *path; > + const char *path; > struct stat st; > int r; > > @@ -707,7 +707,7 @@ static int read_reg_spec(struct config *config) > path = getenv("INTEL_REG_SPEC"); > > if (!path) > - goto builtin; > + path = REGSPECDIR; > > r = stat(path, &st); > if (r) { > diff --git a/tools/quick_dump/Makefile.am b/tools/quick_dump/Makefile.am > index 3d0bd23..b526d19 100644 > --- a/tools/quick_dump/Makefile.am > +++ b/tools/quick_dump/Makefile.am > @@ -25,9 +25,12 @@ chipset_wrap_python.c: chipset.i > all-local: I915ChipsetPython.la > $(LN_S) -f .libs/I915ChipsetPython.so _chipset.so > > +regspecdir = $(pkgdatadir)/registers > +dist_regspec_DATA = $(REGSPECFILES) \ > + base_interrupt.txt base_other.txt base_power.txt \ > + base_rings.txt > + > CLEANFILES = chipset_wrap_python.c chipset.py _chipset.so > -EXTRA_DIST = $(QUICK_DUMP_EXTRA_DIST) \ > - base_interrupt.txt base_other.txt base_power.txt base_rings.txt \ > - quick_dump.py \ > - reg_access.py \ > - chipset.i > +EXTRA_DIST = quick_dump.py \ > + reg_access.py \ > + chipset.i > -- > 2.4.2 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2015-06-15 13:13 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-05-11 18:36 [PATCH i-g-t] quick_dump/skl: Add more pipe/plane registers Damien Lespiau 2015-05-12 6:50 ` Daniel Vetter 2015-05-12 8:58 ` Jani Nikula 2015-06-10 10:30 ` [PATCH i-g-t] intel_reg: install and load the register files Thomas Wood 2015-06-15 13:12 ` Thomas Wood
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