Re: [PATCH] drm/i915/hsw: Disable L3 caching of atomic memory operations.

From: Eric Anholt <eric@anholt.net>
To: Daniel Vetter <daniel@ffwll.ch>, Francisco Jerez <currojerez@riseup.net>
Cc: intel-gfx <intel-gfx@lists.freedesktop.org>,
	Ben Widawsky <ben@bwidawsk.net>
Subject: Re: [PATCH] drm/i915/hsw: Disable L3 caching of atomic memory operations.
Date: Wed, 02 Oct 2013 18:36:11 -0700	[thread overview]
Message-ID: <87a9ircf04.fsf@eliezer.anholt.net> (raw)
In-Reply-To: <CAKMK7uErnpuPgvw3smAtbpH6TvH_K8VjqS59c0rtQ+yW1yxwFw@mail.gmail.com>

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Daniel Vetter <daniel@ffwll.ch> writes:

> On Thu, Oct 3, 2013 at 12:03 AM, Francisco Jerez <currojerez@riseup.net> wrote:
>> +       case I915_PARAM_HAS_ATOMICS:
>> +               value = 1;
>> +               break;
>
> Generally when we do kernel fixes for gpu hangs like that we don't add
> parameters (would drown in them otherwise) but simply queue it up to
> -fixes and slap a cc: stable on it. Gpu hang fixes are critical enough
> imo for that treatment, even when it's for brand new userspace code.
>
> Any specific reason why we shouldn't follow this approach here? I'd
> make the patch simpler and we could dump a bit of userspace code, too.

Well, what it means is that people who pull new mesa on their old kernel
will reliably get GPU hangs when running piglit, which is something
we've avoided in the past when enabling new features
(I915_PARAM_HAS_GEN7_SOL_RESET for example).

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