From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jani Nikula <jani.nikula@linux.intel.com>
Subject: Re: [PATCH] drm/i915: Apply post-sync write for pipe
	control invalidates
Date: Fri, 10 Aug 2012 13:46:17 +0300
Message-ID: <87a9y3ja86.fsf@intel.com>
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To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
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On Fri, 10 Aug 2012, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Fri, 10 Aug 2012 12:57:59 +0300, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>> On Fri, 10 Aug 2012, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>> > When invalidating the TLBs it is documentated as requiring a post-sync
>> > write. Failure to do so seems to result in a GPU hang.
>> >
>> > Exposure to this hang on IVB seems to be a result of removing the extra
>> > stalls required for SNB pipecontrol workarounds:
>> 
>> Hi Chris, AFAICT TLB invalidate requires PIPE_CONTROL_CS_STALL set per
>> the spec. I can't find a mention of the post-sync write, though. Could
>> you double check, please?
>
> Considering replacing it with a CS_STALL just hard hung my box, I remain
> unconvinced. :-p

I meant you could check the spec, not actually try it! ;) But I accept
that's a good reason not to use it.

BR,
Jani.