From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5CB4CCD183 for ; Thu, 16 Oct 2025 20:07:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4B63910E0FE; Thu, 16 Oct 2025 20:07:20 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="AmJpvt3O"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id DECF210E0FE for ; Thu, 16 Oct 2025 20:07:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1760645240; x=1792181240; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=+y0dtcx2YCF4VenYwkwpR1XUs+AepRoSvUMh4BS/R/w=; b=AmJpvt3O1du6zrPn3Sell2QSf/rirgtldh7KPikkdh15MO1tLLsXAawY KRaxitUp24imnpcspSdlBs3llVluo4isiml/cToqlTTM9ZuSkW7vR02Kp e7WwYojQcOp0gVRf3UfHNyM0eFWDmzOm7u84VZodOvqsN7qRc6uSy2yZZ oio0eehUqIlD5SdDVT+AO6aJoN/nSeRDOaCwcGLWgh4NkxYJog5VEFU9j FjS2Q4SyRaUlEgZYaLLtvh12J6+8++MYrYCQmCcT5KjUyw+DHZU61svtx 5tTRi+7jlYPdYImv6SI0GqBy/pY3uIvmAAuU8LNBzD3rwpDcKhkjZPSws A==; X-CSE-ConnectionGUID: htuwf8gmQQ6a4zVslU2qDA== X-CSE-MsgGUID: cJV1gLQMQpy2RgJrdL4zLw== X-IronPort-AV: E=McAfee;i="6800,10657,11531"; a="66684430" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="66684430" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2025 13:07:19 -0700 X-CSE-ConnectionGUID: DkZ1kg8ATrG8JQPxE3A3Cw== X-CSE-MsgGUID: vDK6lfoTSnuNyic4REq2Yw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,234,1754982000"; d="scan'208";a="186812558" Received: from ticela-or-567.amr.corp.intel.com (HELO adixit-MOBL3.intel.com) ([10.125.98.196]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2025 13:07:18 -0700 Date: Thu, 16 Oct 2025 13:07:17 -0700 Message-ID: <87bjm6ipai.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Umesh Nerlige Ramappa Cc: , Subject: Re: [PATCH] drm/i915: Fix conversion between clock ticks and nanoseconds In-Reply-To: <20251016000350.1152382-2-umesh.nerlige.ramappa@intel.com> References: <20251016000350.1152382-2-umesh.nerlige.ramappa@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, 15 Oct 2025 17:03:51 -0700, Umesh Nerlige Ramappa wrote: > > When tick values are large, the multiplication by NSEC_PER_SEC is larger > than 64 bits and results in bad conversions. > > The issue is seen in PMU busyness counters that look like they have > wrapped around due to bad conversion. i915 PMU implementation returns > monotonically increasing counters. If a count is lesser than previous > one, it will only return the larger value until the smaller value > catches up. The user will see this as zero delta between two > measurements even though the engines are busy. > > Fix it by using mul_u64_u32_div() Reviewed-by: Ashutosh Dixit > Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14955 > Signed-off-by: Umesh Nerlige Ramappa > --- > v2: > - Fix divide by zero for Gen11 (Andi) > - Update commit message > > v3: > - Drop GCD and use mul_u64_u32_div() instead (Ashutosh) > --- > drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c > index 88b147fa5cb1..c90b35881a26 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c > @@ -205,7 +205,7 @@ static u64 div_u64_roundup(u64 nom, u32 den) > > u64 intel_gt_clock_interval_to_ns(const struct intel_gt *gt, u64 count) > { > - return div_u64_roundup(count * NSEC_PER_SEC, gt->clock_frequency); > + return mul_u64_u32_div(count, NSEC_PER_SEC, gt->clock_frequency); > } > > u64 intel_gt_pm_interval_to_ns(const struct intel_gt *gt, u64 count) > @@ -215,7 +215,7 @@ u64 intel_gt_pm_interval_to_ns(const struct intel_gt *gt, u64 count) > > u64 intel_gt_ns_to_clock_interval(const struct intel_gt *gt, u64 ns) > { > - return div_u64_roundup(gt->clock_frequency * ns, NSEC_PER_SEC); > + return mul_u64_u32_div(ns, gt->clock_frequency, NSEC_PER_SEC); > } > > u64 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u64 ns) > -- > 2.43.0 >