From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6E52C77B7C for ; Tue, 9 May 2023 17:28:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 563F010E3BF; Tue, 9 May 2023 17:28:17 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id DFA5810E3BF for ; Tue, 9 May 2023 17:28:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683653295; x=1715189295; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=vwy6VXu8OR/nvDqLPxPtlR0yP6VxfoI0ec4bzBJoqJI=; b=Ji1hv4u9kUgITr+T+W0KuLT82cQlltO07DuIzWpnbBC9FqkQc+uMaCW3 Z7kl1FWJWJxOzuPi5d5HGT4+3llgbh+JfNHVKJSRjuaXoWP7I54Im0f5Y nSl+vB67qP/9Y8vK+HMFJtuDqkDfWbUbXaHkfaK1nkIs0Pd6N19fL/Epg gdkOZk4SD7Vf+4w21HGrN7KLRBfIL1+UELT8XrxXizB/Sr4AH9FmOQPC+ U+u3ECyPco/H09MLi90ptqLkydasbhDzCmU9seFvRS6ZG8cw31bSsv36d 8ZGeKSKCfEEG5+ZPkiIda/SQWvQ5Z16UPjf2PBXd0YC5yirQmTNBavicu g==; X-IronPort-AV: E=McAfee;i="6600,9927,10705"; a="339234180" X-IronPort-AV: E=Sophos;i="5.99,262,1677571200"; d="scan'208";a="339234180" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2023 10:25:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10705"; a="763944000" X-IronPort-AV: E=Sophos;i="5.99,262,1677571200"; d="scan'208";a="763944000" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.238.213]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2023 10:25:17 -0700 Date: Tue, 09 May 2023 10:25:16 -0700 Message-ID: <87bkitxvr7.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Umesh Nerlige Ramappa In-Reply-To: <20230506005816.1891043-5-umesh.nerlige.ramappa@intel.com> References: <20230506005816.1891043-1-umesh.nerlige.ramappa@intel.com> <20230506005816.1891043-5-umesh.nerlige.ramappa@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, 05 May 2023 17:58:14 -0700, Umesh Nerlige Ramappa wrote: > > From: Tvrtko Ursulin > > We do not want to have timers per tile and waste CPU cycles and energy via > multiple wake-up sources, for a relatively un-important task of PMU > sampling, so keeping a single timer works well. But we also do not want > the first GT which goes idle to turn off the timer. Apart from this efficiency, what is the reason for having a device level PMU (which monitors gt level events), rather than independent gt level PMU's (each of which monitor events from that gt)? Wouldn't independent gt level PMU's be simpler? And user space tools (say intel-gpu-top) would hook into events from a gt and treat each gt independently? So my question really is what is the reason for keeping the PMU device level rather than per gt? Thanks. -- Ashutosh