Re: [PATCH 06/27] drm/i915/icl: Prepare for more rings

Oscar Mateo
2018-02-07T22:03:49Z

On 1/9/2018 3:23 PM, Paulo Zanoni wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Gen11 will add more VCS and VECS rings so prepare the
> infrastructure to support that.
>
> Bspec: 7021
>
> v2: Rebase.
> v3: Rebase.
> v4: Rebase.
> v5: Rebase.
> v6:
> - Update for POR changes. (Daniele Ceraolo Spurio)
> - Add provisional guc engine ids - to be checked and confirmed.
> v7:
> - Rebased.
> - Added the new ring masks.
> - Added the new HW ids.
> v8:
> - Introduce I915_MAX_VCS/VECS to avoid magic numbers (Michal)
>
> v9: increase MAX_ENGINE_INSTANCE to 3
>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>

My r-b stands. I also have an s-o-b, but IIRC the only thing I did to
this patch was rebasing it on upstream at some point.

> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 +++
> drivers/gpu/drm/i915/i915_gem.h | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 5 ++++-
> drivers/gpu/drm/i915/intel_device_info.c | 3 +++
> drivers/gpu/drm/i915/intel_device_info.h | 4 +++-
> drivers/gpu/drm/i915/intel_ringbuffer.h | 9 ++++++++-
> 6 files changed, 22 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 016920f58ae6..bcd8301456f7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2719,6 +2719,9 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define BLT_RING ENGINE_MASK(BCS)
> #define VEBOX_RING ENGINE_MASK(VECS)
> #define BSD2_RING ENGINE_MASK(VCS2)
> +#define BSD3_RING ENGINE_MASK(VCS3)
> +#define BSD4_RING ENGINE_MASK(VCS4)
> +#define VEBOX2_RING ENGINE_MASK(VECS2)
> #define ALL_ENGINES (~0)
>
> #define HAS_ENGINE(dev_priv, id) \
> diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
> index e920dab7f1b8..1b61b7f8c2ec 100644
> --- a/drivers/gpu/drm/i915/i915_gem.h
> +++ b/drivers/gpu/drm/i915/i915_gem.h
> @@ -54,6 +54,6 @@
> #define GEM_TRACE(...) do { } while (0)
> #endif
>
> -#define I915_NUM_ENGINES 5
> +#define I915_NUM_ENGINES 8
>
> #endif /* __I915_GEM_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 039ad46a4434..b342d30152ca 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -178,6 +178,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define BCS_HW 2
> #define VECS_HW 3
> #define VCS2_HW 4
> +#define VCS3_HW 6
> +#define VCS4_HW 7
> +#define VECS2_HW 12
>
> /* Engine class */
>
> @@ -188,7 +191,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define OTHER_CLASS 4
> #define MAX_ENGINE_CLASS 4
>
> -#define MAX_ENGINE_INSTANCE 1
> +#define MAX_ENGINE_INSTANCE 3
>
> /* PCI config space */
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index a2c16140169f..25448e38ee76 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -489,6 +489,9 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
> info->num_scalers[PIPE_C] = 1;
> }
>
> + BUILD_BUG_ON(I915_NUM_ENGINES >
> + sizeof(intel_ring_mask_t) * BITS_PER_BYTE);
> +
> /*
> * Skylake and Broxton currently don't expose the topmost plane as its
> * use is exclusive with the legacy cursor and we only want to expose
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 9542018d11d0..980893a9e5e9 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -125,6 +125,8 @@ struct sseu_dev_info {
> u8 has_eu_pg:1;
> };
>
> +typedef u8 intel_ring_mask_t;
> +
> struct intel_device_info {
> u16 device_id;
> u16 gen_mask;
> @@ -132,7 +134,7 @@ struct intel_device_info {
> u8 gen;
> u8 gt; /* GT number, 0 if undefined */
> u8 num_rings;
> - u8 ring_mask; /* Rings supported by the HW */
> + intel_ring_mask_t ring_mask; /* Rings supported by the HW */
>
> enum intel_platform platform;
> u32 platform_mask;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index c5ff203e42d6..d0b22753d26e 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -158,6 +158,9 @@ struct i915_ctx_workarounds {
>
> struct drm_i915_gem_request;
>
> +#define I915_MAX_VCS 4
> +#define I915_MAX_VECS 2
> +
> /*
> * Engine IDs definitions.
> * Keep instances of the same type engine together.
> @@ -167,8 +170,12 @@ enum intel_engine_id {
> BCS,
> VCS,
> VCS2,
> + VCS3,
> + VCS4,
> #define _VCS(n) (VCS + (n))
> - VECS
> + VECS,
> + VECS2
> +#define _VECS(n) (VECS + (n))
> };
>
> struct i915_priolist {