Re: [PATCH 27/27] drm/i915/gen11: add support for reading the timestamp frequency

Lionel Landwerlin
2018-03-28T11:34:51Z

On 09/01/18 23:28, Paulo Zanoni wrote:
> The only thing that differs here is that the crystal clock freq now
> has four possible values.
>
> This patch gets rid of the "Unknown gen, unable to compute..." message
> at boot for gen11.
>
> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

Still

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 +++
> drivers/gpu/drm/i915/intel_device_info.c | 71 +++++++++++++++++++++++++-------
> 2 files changed, 61 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eb6c7dcd4db0..fde88cd91ef1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1138,6 +1138,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
> #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0
> #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1
> +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
> +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
> +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0
> +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1
> +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2
> +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3
> #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
> #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 895c41ef4abf..168f6ba83ddd 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -395,6 +395,52 @@ static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
> return base_freq + frac_freq;
> }
>
> +static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
> + u32 rpm_config_reg)
> +{
> + u32 f19_2_mhz = 19200;
> + u32 f24_mhz = 24000;
> + u32 crystal_clock = (rpm_config_reg &
> + GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
> + GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
> +
> + switch (crystal_clock) {
> + case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
> + return f19_2_mhz;
> + case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
> + return f24_mhz;
> + default:
> + MISSING_CASE(crystal_clock);
> + return 0;
> + }
> +}
> +
> +static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
> + u32 rpm_config_reg)
> +{
> + u32 f19_2_mhz = 19200;
> + u32 f24_mhz = 24000;
> + u32 f25_mhz = 25000;
> + u32 f38_4_mhz = 38400;
> + u32 crystal_clock = (rpm_config_reg &
> + GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
> + GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
> +
> + switch (crystal_clock) {
> + case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
> + return f24_mhz;
> + case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
> + return f19_2_mhz;
> + case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:
> + return f38_4_mhz;
> + case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:
> + return f25_mhz;
> + default:
> + MISSING_CASE(crystal_clock);
> + return 0;
> + }
> +}
> +
> static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
> {
> u32 f12_5_mhz = 12500;
> @@ -435,10 +481,9 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
> }
>
> return freq;
> - } else if (INTEL_GEN(dev_priv) <= 10) {
> + } else if (INTEL_GEN(dev_priv) <= 11) {
> u32 ctc_reg = I915_READ(CTC_MODE);
> u32 freq = 0;
> - u32 rpm_config_reg = 0;
>
> /* First figure out the reference frequency. There are 2 ways
> * we can compute the frequency, either through the
> @@ -448,20 +493,14 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
> if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
> freq = read_reference_ts_freq(dev_priv);
> } else {
> - u32 crystal_clock;
> -
> - rpm_config_reg = I915_READ(RPM_CONFIG0);
> - crystal_clock = (rpm_config_reg &
> - GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
> - GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
> - switch (crystal_clock) {
> - case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
> - freq = f19_2_mhz;
> - break;
> - case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
> - freq = f24_mhz;
> - break;
> - }
> + u32 rpm_config_reg = I915_READ(RPM_CONFIG0);
> +
> + if (INTEL_GEN(dev_priv) <= 10)
> + freq = gen10_get_crystal_clock_freq(dev_priv,
> + rpm_config_reg);
> + else
> + freq = gen11_get_crystal_clock_freq(dev_priv,
> + rpm_config_reg);
>
> /* Now figure out how the command stream's timestamp
> * register increments from this frequency (it might