From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Clint Taylor" <clinton.a.taylor@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 04/10] drm/i915: CHV DDR DVFS support and another watermark rewrite
Date: Mon, 29 Jun 2015 11:03:04 +0300 [thread overview]
Message-ID: <87bnfzym9z.fsf@intel.com> (raw)
In-Reply-To: <20150626194812.GD5176@intel.com>
On Fri, 26 Jun 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Fri, Jun 26, 2015 at 10:56:33AM -0700, Clint Taylor wrote:
>> On 06/24/2015 12:00 PM, ville.syrjala@linux.intel.com wrote:
>> > + if (IS_CHERRYVIEW(dev_priv)) {
>> > + dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
>> > + dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
>>
>> nit #defines for these magic values please
>
> What's the point of doing that? These values are not repeated anywhere
> else.
Documentation.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
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next prev parent reply other threads:[~2015-06-29 8:00 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-24 19:00 [PATCH 00/10] drm/i915: Another WM rewrite to enable DDR DVFS on CHV ville.syrjala
2015-06-24 19:00 ` [PATCH 01/10] drm/i915: POSTING_READ() in intel_set_memory_cxsr() ville.syrjala
2015-06-26 20:22 ` Clint Taylor
2015-06-24 19:00 ` [PATCH 02/10] drm/i915: Split atomic wm update to pre and post variants ville.syrjala
2015-06-26 20:22 ` Clint Taylor
2015-06-24 19:00 ` [PATCH 03/10] drm/i915: Read wm values from hardware at init on CHV ville.syrjala
2015-06-26 20:23 ` Clint Taylor
2015-06-24 19:00 ` [PATCH 04/10] drm/i915: CHV DDR DVFS support and another watermark rewrite ville.syrjala
2015-06-26 17:56 ` Clint Taylor
2015-06-26 19:48 ` Ville Syrjälä
2015-06-26 20:21 ` Clint Taylor
2015-06-29 8:03 ` Jani Nikula [this message]
2015-06-29 8:54 ` Daniel Vetter
2015-06-24 19:00 ` [PATCH 05/10] drm/i915: Compute display FIFO split dynamically for CHV ville.syrjala
2015-06-26 20:23 ` Clint Taylor
2015-06-24 19:00 ` [PATCH 06/10] drm/i915: Use the memory latency based WM computation on VLV too ville.syrjala
2015-06-26 20:23 ` Clint Taylor
2015-06-24 19:00 ` [PATCH 07/10] drm/i915: Try to make sure cxsr is disabled around plane enable/disable ville.syrjala
2015-06-26 20:23 ` Clint Taylor
2015-07-01 19:13 ` [PATCH v2 " ville.syrjala
2015-07-01 19:36 ` Paulo Zanoni
2015-07-01 20:38 ` Matt Roper
2015-06-24 19:00 ` [PATCH 08/10] drm/i915: Don't do PM5/DDR DVFS with multiple pipes ville.syrjala
2015-06-26 20:23 ` Clint Taylor
2015-06-24 19:00 ` [PATCH 09/10] drm/i915: Add debugfs knobs for VLVCHV memory latency values ville.syrjala
2015-06-26 20:24 ` Clint Taylor
2015-06-24 19:00 ` [PATCH 10/10] drm/i915: Zero unused WM1 watermarks on VLV/CHV ville.syrjala
2015-06-26 20:24 ` Clint Taylor
2015-06-29 9:00 ` Daniel Vetter
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