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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Damien Lespiau <damien.lespiau@intel.com>, ville.syrjala@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/3] drm/i915: Apply WaDisableAsyncFlipPerfMode via LRIs on gen8
Date: Wed, 03 Jun 2015 14:18:37 +0300	[thread overview]
Message-ID: <87bngxca5u.fsf@intel.com> (raw)
In-Reply-To: <20150603102619.GB24081@strange.ger.corp.intel.com>

On Wed, 03 Jun 2015, Damien Lespiau <damien.lespiau@intel.com> wrote:
> On Tue, Jun 02, 2015 at 03:37:37PM +0300, ville.syrjala@linux.intel.com wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> 
>> MI_MODE is saved in the logical context so WaDisableAsyncFlipPerfMode
>> must be applied using LRIs on gen8.
>> 
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

Thanks, pushed all patches to drm-intel-next-queued.

BR,
Jani.


>
> -- 
> Damien
>
>> ---
>>  drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++++++++--
>>  1 file changed, 8 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index 06f4b22..b70d25b 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -802,6 +802,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
>>  
>>  	WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
>>  
>> +	/* WaDisableAsyncFlipPerfMode:bdw */
>> +	WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
>> +
>>  	/* WaDisablePartialInstShootdown:bdw */
>>  	/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
>>  	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>> @@ -865,6 +868,9 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
>>  
>>  	WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
>>  
>> +	/* WaDisableAsyncFlipPerfMode:chv */
>> +	WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
>> +
>>  	/* WaDisablePartialInstShootdown:chv */
>>  	/* WaDisableThreadStallDopClockGating:chv */
>>  	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>> @@ -1109,9 +1115,9 @@ static int init_render_ring(struct intel_engine_cs *ring)
>>  	 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
>>  	 * programmed to '1' on all products.
>>  	 *
>> -	 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
>> +	 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
>>  	 */
>> -	if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
>> +	if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
>>  		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
>>  
>>  	/* Required for the hardware to program scanline values for waiting */
>> -- 
>> 2.3.6
>> 
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2015-06-03 11:17 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-02 12:37 [PATCH 1/3] drm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv code ville.syrjala
2015-06-02 12:37 ` [PATCH 2/3] drm/i915: Set INSTPM_FORCE_ORDERING via LRI on gen8, drop it on gen9+ ville.syrjala
2015-06-03 10:25   ` Damien Lespiau
2015-06-02 12:37 ` [PATCH 3/3] drm/i915: Apply WaDisableAsyncFlipPerfMode via LRIs on gen8 ville.syrjala
2015-06-02 22:31   ` shuang.he
2015-06-03 10:26   ` Damien Lespiau
2015-06-03 11:18     ` Jani Nikula [this message]
2015-06-02 12:53 ` [PATCH 1/3] drm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv code Damien Lespiau
2015-06-03  7:45   ` Jani Nikula
2015-06-04 11:22     ` Jani Nikula

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