[PATCH] drm/i915: Cancel vdd off work before suspend

[PATCH] drm/i915: Cancel vdd off work before suspend

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we just make sure vdd is off before suspending, but we don't
cancel the vdd off work. The work wil not touch vdd if
want_panel_vdd==false so in theory this is fine.

In the past that was perfectly fine since the vdd off work didn't do
anything when want_panel_vdd==false, so even if the work would have been
run during system resume before i915 has resumed, nothing would happen.

However since pps_lock() will now grab the power domain references before
it can check want_panel_vdd, we may end up toggling the power wells on/off
already before the driver has resumed. That is not really acceptable, so
cancel the vdd off work when suspending the encoder.

The problem appeared when pps_lock() was introduced in:
 commit 773538e86081d146e0020435d614f4b96996c1f9
 Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
 Date:   Thu Sep 4 14:54:56 2014 +0300

    drm/i915: Reset power sequencer pipe tracking when disp2d is off

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 46731da..d2529ec 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4335,6 +4335,7 @@ static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
 	 * vdd might still be enabled do to the delayed vdd off.
 	 * Make sure vdd is actually turned off here.
 	 */
+	cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
 	pps_lock(intel_dp);
 	edp_panel_vdd_off_sync(intel_dp);
 	pps_unlock(intel_dp);
-- 
2.0.4

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Re: [PATCH] drm/i915: Cancel vdd off work before suspend

[Imre Deak]

On Tue, 2014-11-25 at 15:43 +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently we just make sure vdd is off before suspending, but we don't
> cancel the vdd off work. The work wil not touch vdd if
> want_panel_vdd==false so in theory this is fine.
> 
> In the past that was perfectly fine since the vdd off work didn't do
> anything when want_panel_vdd==false, so even if the work would have been
> run during system resume before i915 has resumed, nothing would happen.
> 
> However since pps_lock() will now grab the power domain references before
> it can check want_panel_vdd, we may end up toggling the power wells on/off
> already before the driver has resumed. That is not really acceptable, so
> cancel the vdd off work when suspending the encoder.
> 
> The problem appeared when pps_lock() was introduced in:
>  commit 773538e86081d146e0020435d614f4b96996c1f9
>  Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
>  Date:   Thu Sep 4 14:54:56 2014 +0300
> 
>     drm/i915: Reset power sequencer pipe tracking when disp2d is off
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 46731da..d2529ec 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4335,6 +4335,7 @@ static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
>  	 * vdd might still be enabled do to the delayed vdd off.
>  	 * Make sure vdd is actually turned off here.
>  	 */
> +	cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
>  	pps_lock(intel_dp);
>  	edp_panel_vdd_off_sync(intel_dp);
>  	pps_unlock(intel_dp);


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Re: [PATCH] drm/i915: Cancel vdd off work before suspend

[Jani Nikula]

On Tue, 25 Nov 2014, Imre Deak <imre.deak@intel.com> wrote:
> On Tue, 2014-11-25 at 15:43 +0200, ville.syrjala@linux.intel.com wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> 
>> Currently we just make sure vdd is off before suspending, but we don't
>> cancel the vdd off work. The work wil not touch vdd if
>> want_panel_vdd==false so in theory this is fine.
>> 
>> In the past that was perfectly fine since the vdd off work didn't do
>> anything when want_panel_vdd==false, so even if the work would have been
>> run during system resume before i915 has resumed, nothing would happen.
>> 
>> However since pps_lock() will now grab the power domain references before
>> it can check want_panel_vdd, we may end up toggling the power wells on/off
>> already before the driver has resumed. That is not really acceptable, so
>> cancel the vdd off work when suspending the encoder.
>> 
>> The problem appeared when pps_lock() was introduced in:
>>  commit 773538e86081d146e0020435d614f4b96996c1f9
>>  Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>  Date:   Thu Sep 4 14:54:56 2014 +0300
>> 
>>     drm/i915: Reset power sequencer pipe tracking when disp2d is off
>> 
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: Imre Deak <imre.deak@intel.com>

Pushed to drm-intel-fixes, thanks for the patch and review.

BR,
Jani.

>
>> ---
>>  drivers/gpu/drm/i915/intel_dp.c | 1 +
>>  1 file changed, 1 insertion(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 46731da..d2529ec 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -4335,6 +4335,7 @@ static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
>>  	 * vdd might still be enabled do to the delayed vdd off.
>>  	 * Make sure vdd is actually turned off here.
>>  	 */
>> +	cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
>>  	pps_lock(intel_dp);
>>  	edp_panel_vdd_off_sync(intel_dp);
>>  	pps_unlock(intel_dp);
>
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH] drm/i915: Cancel vdd off work before suspend

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  366/366              366/366
ILK                 -8              371/371              363/371
SNB                                  450/450              450/450
IVB                 -4              498/498              494/498
BYT                                  289/289              289/289
HSW                 -1              564/564              563/564
BDW                                  417/417              417/417
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 ILK  igt_gem_reset_stats_close-pending-fork-render      TIMEOUT(20, M37M26)PASS(1, M26)      TIMEOUT(1, M26)
 ILK  igt_kms_3d      DMESG_WARN(2, M26)PASS(5, M37M26)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_flip-vs-dpms-off-vs-modeset      DMESG_WARN(1, M26)PASS(3, M37M26)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_rcs-flip-vs-panning-interruptible      DMESG_WARN(1, M26)PASS(3, M37M26)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_rcs-wf_vblank-vs-modeset      DMESG_WARN(1, M26)PASS(4, M37M26)      DMESG_WARN(1, M26)
*ILK  igt_kms_flip_flip-vs-dpms-interruptible      PASS(4, M37M26)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_plain-flip      DMESG_WARN(2, M26)PASS(4, M37M26)      DMESG_WARN(1, M26)
 ILK  igt_kms_flip_vblank-vs-hang      TIMEOUT(19, M37M26)PASS(1, M26)      TIMEOUT(1, M26)
*IVB  igt_kms_plane_plane-panning-bottom-right-pipe-C-plane-2      PASS(4, M21M34)      DMESG_WARN(1, M34)
*IVB  igt_kms_plane_plane-panning-top-left-pipe-C-plane-2      PASS(2, M21M34)      DMESG_WARN(1, M34)
*IVB  igt_kms_plane_plane-position-covered-pipe-C-plane-2      PASS(2, M21M34)      DMESG_WARN(1, M34)
*IVB  igt_kms_plane_plane-position-hole-pipe-C-plane-1      PASS(5, M21M34)      DMESG_WARN(1, M34)
*HSW  igt_kms_fence_pin_leak      PASS(6, M20M19)      DMESG_WARN(1, M19)
Note: You need to pay more attention to line start with '*'
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