From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mika Kuoppala Subject: Re: [PATCH v2 1/2] drm/i915: add render state initialization Date: Tue, 06 May 2014 17:34:30 +0300 Message-ID: <87bnvbj7rd.fsf@gaia.fi.intel.com> References: <1399382766-25116-1-git-send-email-mika.kuoppala@intel.com> <1399382766-25116-2-git-send-email-mika.kuoppala@intel.com> <20140506134153.GA476@nuc-i3427.alporthouse.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 0EC696E36D for ; Tue, 6 May 2014 07:35:25 -0700 (PDT) In-Reply-To: <20140506134153.GA476@nuc-i3427.alporthouse.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org, miku@iki.fi, ben@bwidawsk.net, kristen@linux.intel.com List-Id: intel-gfx@lists.freedesktop.org Chris Wilson writes: > On Tue, May 06, 2014 at 04:26:05PM +0300, Mika Kuoppala wrote: >> HW guys say that it is not a cool idea to let device >> go into rc6 without proper 3d pipeline state. > > * shrug > > What's improper 3d state and what prevents userspace from triggering > badness later? I would guess improver is 'whats is there after powerup'. But yes, we dont even know (yet?) what is the proper minimal state :P What comes to userspace triggering badness later is that the ring will hang and hangcheck will cleanup the mess. > The only problem I see in the patch is that you don't move the so->obj > to the GPU before execution - the code is only coherent thanks to LLC > atm. Fixed in v3. Thanks, -Mika > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre