Re: [PATCH 4/8] drm/i915: Move i9xx_crtc_clock_get() and ironlake_crtc_clock_get() earlier

[Jani Nikula <jani.nikula@linux.intel.com>]

On Wed, 04 Sep 2013, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move i9xx_crtc_clock_get() and ironlake_crtc_clock_get() around to avoid
> forward declarations, as we will soon call these directly from
> i9xx_get_pipe_config() and ironlake_get_pipe_config() respectively,
>
> No functional changes.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 262 +++++++++++++++++------------------
>  1 file changed, 131 insertions(+), 131 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b991acd..74affb1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4985,6 +4985,92 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
>  			I915_READ(LVDS) & LVDS_BORDER_ENABLE;
>  }
>  
> +/* Returns the clock of the currently programmed mode of the given pipe. */
> +static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
> +				struct intel_crtc_config *pipe_config)
> +{
> +	struct drm_device *dev = crtc->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int pipe = pipe_config->cpu_transcoder;
> +	u32 dpll = I915_READ(DPLL(pipe));
> +	u32 fp;
> +	intel_clock_t clock;
> +
> +	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
> +		fp = I915_READ(FP0(pipe));
> +	else
> +		fp = I915_READ(FP1(pipe));
> +
> +	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
> +	if (IS_PINEVIEW(dev)) {
> +		clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
> +		clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
> +	} else {
> +		clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
> +		clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
> +	}
> +
> +	if (!IS_GEN2(dev)) {
> +		if (IS_PINEVIEW(dev))
> +			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
> +				DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
> +		else
> +			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
> +			       DPLL_FPA01_P1_POST_DIV_SHIFT);
> +
> +		switch (dpll & DPLL_MODE_MASK) {
> +		case DPLLB_MODE_DAC_SERIAL:
> +			clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
> +				5 : 10;
> +			break;
> +		case DPLLB_MODE_LVDS:
> +			clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
> +				7 : 14;
> +			break;
> +		default:
> +			DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
> +				  "mode\n", (int)(dpll & DPLL_MODE_MASK));
> +			pipe_config->adjusted_mode.clock = 0;
> +			return;
> +		}
> +
> +		if (IS_PINEVIEW(dev))
> +			pineview_clock(96000, &clock);
> +		else
> +			i9xx_clock(96000, &clock);
> +	} else {
> +		bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
> +
> +		if (is_lvds) {
> +			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
> +				       DPLL_FPA01_P1_POST_DIV_SHIFT);
> +			clock.p2 = 14;
> +
> +			if ((dpll & PLL_REF_INPUT_MASK) ==
> +			    PLLB_REF_INPUT_SPREADSPECTRUMIN) {
> +				/* XXX: might not be 66MHz */
> +				i9xx_clock(66000, &clock);
> +			} else
> +				i9xx_clock(48000, &clock);
> +		} else {
> +			if (dpll & PLL_P1_DIVIDE_BY_TWO)
> +				clock.p1 = 2;
> +			else {
> +				clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
> +					    DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
> +			}
> +			if (dpll & PLL_P2_DIVIDE_BY_4)
> +				clock.p2 = 4;
> +			else
> +				clock.p2 = 2;
> +
> +			i9xx_clock(48000, &clock);
> +		}
> +	}
> +
> +	pipe_config->adjusted_mode.clock = clock.dot;
> +}
> +
>  static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  				 struct intel_crtc_config *pipe_config)
>  {
> @@ -5901,6 +5987,51 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
>  	}
>  }
>  
> +static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
> +				    struct intel_crtc_config *pipe_config)
> +{
> +	struct drm_device *dev = crtc->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> +	int link_freq;
> +	u64 clock;
> +	u32 link_m, link_n;
> +
> +	/*
> +	 * The calculation for the data clock is:
> +	 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
> +	 * But we want to avoid losing precison if possible, so:
> +	 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
> +	 *
> +	 * and the link clock is simpler:
> +	 * link_clock = (m * link_clock) / n
> +	 */
> +
> +	/*
> +	 * We need to get the FDI or DP link clock here to derive
> +	 * the M/N dividers.
> +	 *
> +	 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
> +	 * For DP, it's either 1.62GHz or 2.7GHz.
> +	 * We do our calculations in 10*MHz since we don't need much precison.
> +	 */
> +	if (pipe_config->has_pch_encoder)
> +		link_freq = intel_fdi_link_freq(dev) * 10000;
> +	else
> +		link_freq = pipe_config->port_clock;
> +
> +	link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
> +	link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
> +
> +	if (!link_m || !link_n)
> +		return;
> +
> +	clock = ((u64)link_m * (u64)link_freq);
> +	do_div(clock, link_n);
> +
> +	pipe_config->adjusted_mode.clock = clock;
> +}
> +
>  static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
>  				     struct intel_crtc_config *pipe_config)
>  {
> @@ -7280,137 +7411,6 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
>  	mutex_unlock(&crtc->mutex);
>  }
>  
> -/* Returns the clock of the currently programmed mode of the given pipe. */
> -static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
> -				struct intel_crtc_config *pipe_config)
> -{
> -	struct drm_device *dev = crtc->base.dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	int pipe = pipe_config->cpu_transcoder;
> -	u32 dpll = I915_READ(DPLL(pipe));
> -	u32 fp;
> -	intel_clock_t clock;
> -
> -	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
> -		fp = I915_READ(FP0(pipe));
> -	else
> -		fp = I915_READ(FP1(pipe));
> -
> -	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
> -	if (IS_PINEVIEW(dev)) {
> -		clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
> -		clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
> -	} else {
> -		clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
> -		clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
> -	}
> -
> -	if (!IS_GEN2(dev)) {
> -		if (IS_PINEVIEW(dev))
> -			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
> -				DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
> -		else
> -			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
> -			       DPLL_FPA01_P1_POST_DIV_SHIFT);
> -
> -		switch (dpll & DPLL_MODE_MASK) {
> -		case DPLLB_MODE_DAC_SERIAL:
> -			clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
> -				5 : 10;
> -			break;
> -		case DPLLB_MODE_LVDS:
> -			clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
> -				7 : 14;
> -			break;
> -		default:
> -			DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
> -				  "mode\n", (int)(dpll & DPLL_MODE_MASK));
> -			pipe_config->adjusted_mode.clock = 0;
> -			return;
> -		}
> -
> -		if (IS_PINEVIEW(dev))
> -			pineview_clock(96000, &clock);
> -		else
> -			i9xx_clock(96000, &clock);
> -	} else {
> -		bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
> -
> -		if (is_lvds) {
> -			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
> -				       DPLL_FPA01_P1_POST_DIV_SHIFT);
> -			clock.p2 = 14;
> -
> -			if ((dpll & PLL_REF_INPUT_MASK) ==
> -			    PLLB_REF_INPUT_SPREADSPECTRUMIN) {
> -				/* XXX: might not be 66MHz */
> -				i9xx_clock(66000, &clock);
> -			} else
> -				i9xx_clock(48000, &clock);
> -		} else {
> -			if (dpll & PLL_P1_DIVIDE_BY_TWO)
> -				clock.p1 = 2;
> -			else {
> -				clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
> -					    DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
> -			}
> -			if (dpll & PLL_P2_DIVIDE_BY_4)
> -				clock.p2 = 4;
> -			else
> -				clock.p2 = 2;
> -
> -			i9xx_clock(48000, &clock);
> -		}
> -	}
> -
> -	pipe_config->adjusted_mode.clock = clock.dot;
> -}
> -
> -static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
> -				    struct intel_crtc_config *pipe_config)
> -{
> -	struct drm_device *dev = crtc->base.dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> -	int link_freq;
> -	u64 clock;
> -	u32 link_m, link_n;
> -
> -	/*
> -	 * The calculation for the data clock is:
> -	 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
> -	 * But we want to avoid losing precison if possible, so:
> -	 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
> -	 *
> -	 * and the link clock is simpler:
> -	 * link_clock = (m * link_clock) / n
> -	 */
> -
> -	/*
> -	 * We need to get the FDI or DP link clock here to derive
> -	 * the M/N dividers.
> -	 *
> -	 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
> -	 * For DP, it's either 1.62GHz or 2.7GHz.
> -	 * We do our calculations in 10*MHz since we don't need much precison.
> -	 */
> -	if (pipe_config->has_pch_encoder)
> -		link_freq = intel_fdi_link_freq(dev) * 10000;
> -	else
> -		link_freq = pipe_config->port_clock;
> -
> -	link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
> -	link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
> -
> -	if (!link_m || !link_n)
> -		return;
> -
> -	clock = ((u64)link_m * (u64)link_freq);
> -	do_div(clock, link_n);
> -
> -	pipe_config->adjusted_mode.clock = clock;
> -}
> -
>  /** Returns the currently programmed mode of the given pipe. */
>  struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
>  					     struct drm_crtc *crtc)
> -- 
> 1.8.1.5
>
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-- 
Jani Nikula, Intel Open Source Technology Center
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