* [PATCH 1/8] drm/i915: Don't factor in pixel multplier when deriving dotclock from link clock and M/N values
2013-09-04 11:14 [PATCH 0/8] drm/i915: adjusted_mode.clock vs. port_clock v2 ville.syrjala
@ 2013-09-04 11:14 ` ville.syrjala
2013-09-04 13:22 ` Jani Nikula
2013-09-04 11:14 ` [PATCH 2/8] drm/i915: Make adjusted_mode.clock non-pixel multiplied ville.syrjala
` (6 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: ville.syrjala @ 2013-09-04 11:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We feed the non-multiplied clock to intel_link_compute_m_n(), so the
opposite operation should use the same order of operations. So we just
multiply by pixel_multiplier in the end now.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d88057e..b45c6e6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7340,20 +7340,18 @@ static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
- int link_freq, repeat;
+ int link_freq;
u64 clock;
u32 link_m, link_n;
- repeat = pipe_config->pixel_multiplier;
-
/*
* The calculation for the data clock is:
- * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
+ * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
* But we want to avoid losing precison if possible, so:
- * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
+ * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
*
* and the link clock is simpler:
- * link_clock = (m * link_clock * repeat) / n
+ * link_clock = (m * link_clock) / n
*/
/*
@@ -7375,10 +7373,11 @@ static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
if (!link_m || !link_n)
return;
- clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
+ clock = ((u64)link_m * (u64)link_freq);
do_div(clock, link_n);
- pipe_config->adjusted_mode.clock = clock;
+ pipe_config->adjusted_mode.clock = clock *
+ pipe_config->pixel_multiplier;
}
/** Returns the currently programmed mode of the given pipe. */
--
1.8.1.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 1/8] drm/i915: Don't factor in pixel multplier when deriving dotclock from link clock and M/N values
2013-09-04 11:14 ` [PATCH 1/8] drm/i915: Don't factor in pixel multplier when deriving dotclock from link clock and M/N values ville.syrjala
@ 2013-09-04 13:22 ` Jani Nikula
0 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2013-09-04 13:22 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Wed, 04 Sep 2013, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We feed the non-multiplied clock to intel_link_compute_m_n(), so the
> opposite operation should use the same order of operations. So we just
> multiply by pixel_multiplier in the end now.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 15 +++++++--------
> 1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d88057e..b45c6e6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7340,20 +7340,18 @@ static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> - int link_freq, repeat;
> + int link_freq;
> u64 clock;
> u32 link_m, link_n;
>
> - repeat = pipe_config->pixel_multiplier;
> -
> /*
> * The calculation for the data clock is:
> - * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
> + * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
> * But we want to avoid losing precison if possible, so:
> - * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
> + * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
> *
> * and the link clock is simpler:
> - * link_clock = (m * link_clock * repeat) / n
> + * link_clock = (m * link_clock) / n
> */
>
> /*
> @@ -7375,10 +7373,11 @@ static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
> if (!link_m || !link_n)
> return;
>
> - clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
> + clock = ((u64)link_m * (u64)link_freq);
> do_div(clock, link_n);
>
> - pipe_config->adjusted_mode.clock = clock;
> + pipe_config->adjusted_mode.clock = clock *
> + pipe_config->pixel_multiplier;
> }
>
> /** Returns the currently programmed mode of the given pipe. */
> --
> 1.8.1.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 2/8] drm/i915: Make adjusted_mode.clock non-pixel multiplied
2013-09-04 11:14 [PATCH 0/8] drm/i915: adjusted_mode.clock vs. port_clock v2 ville.syrjala
2013-09-04 11:14 ` [PATCH 1/8] drm/i915: Don't factor in pixel multplier when deriving dotclock from link clock and M/N values ville.syrjala
@ 2013-09-04 11:14 ` ville.syrjala
2013-09-04 11:14 ` [PATCH 3/8] drm/i915: Add support for pipe_bpp readout ville.syrjala
` (5 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: ville.syrjala @ 2013-09-04 11:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
It would be easier if adjusted_mode.clock would be the pipe pixel clock,
and it actually is, except for the cases where pixel_multiplier > 1.
So let's change intel_sdvo to use port_clock as the multiplied clock,
and then we can leave adjusted_mode.clock as pipe pixel clock.
v2: Improve port_clock documentation
Rebased on top of SDVO pixel_multiplier fixes
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 7 +++----
drivers/gpu/drm/i915/intel_drv.h | 5 ++++-
drivers/gpu/drm/i915/intel_sdvo.c | 4 +---
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b45c6e6..2aac205 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4062,7 +4062,6 @@ retry:
link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
fdi_dotclock = adjusted_mode->clock;
- fdi_dotclock /= pipe_config->pixel_multiplier;
lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
pipe_config->pipe_bpp);
@@ -7376,8 +7375,7 @@ static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
clock = ((u64)link_m * (u64)link_freq);
do_div(clock, link_n);
- pipe_config->adjusted_mode.clock = clock *
- pipe_config->pixel_multiplier;
+ pipe_config->adjusted_mode.clock = clock;
}
/** Returns the currently programmed mode of the given pipe. */
@@ -8322,7 +8320,8 @@ encoder_retry:
/* Set default port clock if not overwritten by the encoder. Needs to be
* done afterwards in case the encoder adjusts the mode. */
if (!pipe_config->port_clock)
- pipe_config->port_clock = pipe_config->adjusted_mode.clock;
+ pipe_config->port_clock = pipe_config->adjusted_mode.clock *
+ pipe_config->pixel_multiplier;
ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
if (ret < 0) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ea97c23..dbf04be 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -212,6 +212,8 @@ struct intel_crtc_config {
unsigned long quirks;
struct drm_display_mode requested_mode;
+ /* Actual pipe timings ie. what we program into the pipe timing
+ * registers. adjusted_mode.clock is the pipe pixel clock. */
struct drm_display_mode adjusted_mode;
/* Whether to set up the PCH/FDI. Note that we never allow sharing
* between pch encoders and cpu encoders. */
@@ -266,7 +268,8 @@ struct intel_crtc_config {
/*
* Frequence the dpll for the port should run at. Differs from the
- * adjusted dotclock e.g. for DP or 12bpc hdmi mode.
+ * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
+ * already multiplied by pixel_multiplier.
*/
int port_clock;
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 85037b9..74042c6 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1059,7 +1059,7 @@ intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config)
{
- unsigned dotclock = pipe_config->adjusted_mode.clock;
+ unsigned dotclock = pipe_config->port_clock;
struct dpll *clock = &pipe_config->dpll;
/* SDVO TV has fixed PLL values depend on its clock range,
@@ -1124,7 +1124,6 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
*/
pipe_config->pixel_multiplier =
intel_sdvo_get_pixel_multiplier(adjusted_mode);
- adjusted_mode->clock *= pipe_config->pixel_multiplier;
if (intel_sdvo->color_range_auto) {
/* See CEA-861-E - 5.1 Default Encoding Parameters */
@@ -1212,7 +1211,6 @@ static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
* adjusted_mode.
*/
intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
- input_dtd.part1.clock /= crtc->config.pixel_multiplier;
if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
--
1.8.1.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 3/8] drm/i915: Add support for pipe_bpp readout
2013-09-04 11:14 [PATCH 0/8] drm/i915: adjusted_mode.clock vs. port_clock v2 ville.syrjala
2013-09-04 11:14 ` [PATCH 1/8] drm/i915: Don't factor in pixel multplier when deriving dotclock from link clock and M/N values ville.syrjala
2013-09-04 11:14 ` [PATCH 2/8] drm/i915: Make adjusted_mode.clock non-pixel multiplied ville.syrjala
@ 2013-09-04 11:14 ` ville.syrjala
2013-09-06 13:18 ` [PATCH v2] " ville.syrjala
2013-09-04 11:14 ` [PATCH 4/8] drm/i915: Move i9xx_crtc_clock_get() and ironlake_crtc_clock_get() earlier ville.syrjala
` (4 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: ville.syrjala @ 2013-09-04 11:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
On CTG+ read out the pipe bpp setting from hardware and fill it into
pipe config. Also check it appropriately.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 17 +++++++++++++++++
drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++++++++++++
2 files changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 060ea50..9305fb6 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1268,6 +1268,23 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
flags |= DRM_MODE_FLAG_NVSYNC;
pipe_config->adjusted_mode.flags |= flags;
+
+ switch (temp & TRANS_DDI_BPC_MASK) {
+ case TRANS_DDI_BPC_6:
+ pipe_config->pipe_bpp = 18;
+ break;
+ case TRANS_DDI_BPC_8:
+ pipe_config->pipe_bpp = 24;
+ break;
+ case TRANS_DDI_BPC_10:
+ pipe_config->pipe_bpp = 30;
+ break;
+ case TRANS_DDI_BPC_12:
+ pipe_config->pipe_bpp = 36;
+ break;
+ default:
+ break;
+ }
}
static void intel_ddi_destroy(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2aac205..b991acd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5031,6 +5031,22 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
DPLL_PORTB_READY_MASK);
}
+ if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
+ switch (I915_READ(PIPECONF(crtc->pipe)) & PIPECONF_BPC_MASK) {
+ case PIPECONF_6BPC:
+ pipe_config->pipe_bpp = 18;
+ break;
+ case PIPECONF_8BPC:
+ pipe_config->pipe_bpp = 24;
+ break;
+ case PIPECONF_10BPC:
+ pipe_config->pipe_bpp = 30;
+ break;
+ default:
+ break;
+ }
+ }
+
return true;
}
@@ -5930,6 +5946,23 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
pipe_config->pixel_multiplier =
((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
>> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
+
+ switch (I915_READ(PIPECONF(crtc->pipe)) & PIPECONF_BPC_MASK) {
+ case PIPECONF_6BPC:
+ pipe_config->pipe_bpp = 18;
+ break;
+ case PIPECONF_8BPC:
+ pipe_config->pipe_bpp = 24;
+ break;
+ case PIPECONF_10BPC:
+ pipe_config->pipe_bpp = 30;
+ break;
+ case PIPECONF_12BPC:
+ pipe_config->pipe_bpp = 36;
+ break;
+ default:
+ break;
+ }
} else {
pipe_config->pixel_multiplier = 1;
}
@@ -8630,6 +8663,9 @@ intel_pipe_config_compare(struct drm_device *dev,
PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
+ if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
+ PIPE_CONF_CHECK_I(pipe_bpp);
+
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
#undef PIPE_CONF_CHECK_FLAGS
--
1.8.1.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2] drm/i915: Add support for pipe_bpp readout
2013-09-04 11:14 ` [PATCH 3/8] drm/i915: Add support for pipe_bpp readout ville.syrjala
@ 2013-09-06 13:18 ` ville.syrjala
0 siblings, 0 replies; 14+ messages in thread
From: ville.syrjala @ 2013-09-06 13:18 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
On CTG+ read out the pipe bpp setting from hardware and fill it into
pipe config. Also check it appropriately.
v2: Don't do the pipe_bpp extraction inside the PCH only code block on
ILK+.
Avoid the PIPECONF read as we already have read it for the
PIPECONF_EANBLE check.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 17 +++++++++++++++++
drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++++++++++++
2 files changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 060ea50..9305fb6 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1268,6 +1268,23 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
flags |= DRM_MODE_FLAG_NVSYNC;
pipe_config->adjusted_mode.flags |= flags;
+
+ switch (temp & TRANS_DDI_BPC_MASK) {
+ case TRANS_DDI_BPC_6:
+ pipe_config->pipe_bpp = 18;
+ break;
+ case TRANS_DDI_BPC_8:
+ pipe_config->pipe_bpp = 24;
+ break;
+ case TRANS_DDI_BPC_10:
+ pipe_config->pipe_bpp = 30;
+ break;
+ case TRANS_DDI_BPC_12:
+ pipe_config->pipe_bpp = 36;
+ break;
+ default:
+ break;
+ }
}
static void intel_ddi_destroy(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2aac205..35ad910 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4999,6 +4999,22 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
if (!(tmp & PIPECONF_ENABLE))
return false;
+ if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
+ switch (tmp & PIPECONF_BPC_MASK) {
+ case PIPECONF_6BPC:
+ pipe_config->pipe_bpp = 18;
+ break;
+ case PIPECONF_8BPC:
+ pipe_config->pipe_bpp = 24;
+ break;
+ case PIPECONF_10BPC:
+ pipe_config->pipe_bpp = 30;
+ break;
+ default:
+ break;
+ }
+ }
+
intel_get_pipe_timings(crtc, pipe_config);
i9xx_get_pfit_config(crtc, pipe_config);
@@ -5899,6 +5915,23 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
if (!(tmp & PIPECONF_ENABLE))
return false;
+ switch (tmp & PIPECONF_BPC_MASK) {
+ case PIPECONF_6BPC:
+ pipe_config->pipe_bpp = 18;
+ break;
+ case PIPECONF_8BPC:
+ pipe_config->pipe_bpp = 24;
+ break;
+ case PIPECONF_10BPC:
+ pipe_config->pipe_bpp = 30;
+ break;
+ case PIPECONF_12BPC:
+ pipe_config->pipe_bpp = 36;
+ break;
+ default:
+ break;
+ }
+
if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
struct intel_shared_dpll *pll;
@@ -8630,6 +8663,9 @@ intel_pipe_config_compare(struct drm_device *dev,
PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
+ if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
+ PIPE_CONF_CHECK_I(pipe_bpp);
+
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
#undef PIPE_CONF_CHECK_FLAGS
--
1.8.1.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/8] drm/i915: Move i9xx_crtc_clock_get() and ironlake_crtc_clock_get() earlier
2013-09-04 11:14 [PATCH 0/8] drm/i915: adjusted_mode.clock vs. port_clock v2 ville.syrjala
` (2 preceding siblings ...)
2013-09-04 11:14 ` [PATCH 3/8] drm/i915: Add support for pipe_bpp readout ville.syrjala
@ 2013-09-04 11:14 ` ville.syrjala
2013-09-04 13:22 ` Jani Nikula
2013-09-04 11:14 ` [PATCH 5/8] drm/i915: Fix port_clock readout for SDVO and HDMI 12bpc cases ville.syrjala
` (3 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: ville.syrjala @ 2013-09-04 11:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move i9xx_crtc_clock_get() and ironlake_crtc_clock_get() around to avoid
forward declarations, as we will soon call these directly from
i9xx_get_pipe_config() and ironlake_get_pipe_config() respectively,
No functional changes.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 262 +++++++++++++++++------------------
1 file changed, 131 insertions(+), 131 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b991acd..74affb1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4985,6 +4985,92 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
I915_READ(LVDS) & LVDS_BORDER_ENABLE;
}
+/* Returns the clock of the currently programmed mode of the given pipe. */
+static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
+ struct intel_crtc_config *pipe_config)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int pipe = pipe_config->cpu_transcoder;
+ u32 dpll = I915_READ(DPLL(pipe));
+ u32 fp;
+ intel_clock_t clock;
+
+ if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
+ fp = I915_READ(FP0(pipe));
+ else
+ fp = I915_READ(FP1(pipe));
+
+ clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
+ if (IS_PINEVIEW(dev)) {
+ clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
+ clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
+ } else {
+ clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
+ clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
+ }
+
+ if (!IS_GEN2(dev)) {
+ if (IS_PINEVIEW(dev))
+ clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
+ DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
+ else
+ clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
+ DPLL_FPA01_P1_POST_DIV_SHIFT);
+
+ switch (dpll & DPLL_MODE_MASK) {
+ case DPLLB_MODE_DAC_SERIAL:
+ clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
+ 5 : 10;
+ break;
+ case DPLLB_MODE_LVDS:
+ clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
+ 7 : 14;
+ break;
+ default:
+ DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
+ "mode\n", (int)(dpll & DPLL_MODE_MASK));
+ pipe_config->adjusted_mode.clock = 0;
+ return;
+ }
+
+ if (IS_PINEVIEW(dev))
+ pineview_clock(96000, &clock);
+ else
+ i9xx_clock(96000, &clock);
+ } else {
+ bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
+
+ if (is_lvds) {
+ clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
+ DPLL_FPA01_P1_POST_DIV_SHIFT);
+ clock.p2 = 14;
+
+ if ((dpll & PLL_REF_INPUT_MASK) ==
+ PLLB_REF_INPUT_SPREADSPECTRUMIN) {
+ /* XXX: might not be 66MHz */
+ i9xx_clock(66000, &clock);
+ } else
+ i9xx_clock(48000, &clock);
+ } else {
+ if (dpll & PLL_P1_DIVIDE_BY_TWO)
+ clock.p1 = 2;
+ else {
+ clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
+ DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
+ }
+ if (dpll & PLL_P2_DIVIDE_BY_4)
+ clock.p2 = 4;
+ else
+ clock.p2 = 2;
+
+ i9xx_clock(48000, &clock);
+ }
+ }
+
+ pipe_config->adjusted_mode.clock = clock.dot;
+}
+
static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
struct intel_crtc_config *pipe_config)
{
@@ -5901,6 +5987,51 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
}
}
+static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
+ struct intel_crtc_config *pipe_config)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+ int link_freq;
+ u64 clock;
+ u32 link_m, link_n;
+
+ /*
+ * The calculation for the data clock is:
+ * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
+ * But we want to avoid losing precison if possible, so:
+ * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
+ *
+ * and the link clock is simpler:
+ * link_clock = (m * link_clock) / n
+ */
+
+ /*
+ * We need to get the FDI or DP link clock here to derive
+ * the M/N dividers.
+ *
+ * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
+ * For DP, it's either 1.62GHz or 2.7GHz.
+ * We do our calculations in 10*MHz since we don't need much precison.
+ */
+ if (pipe_config->has_pch_encoder)
+ link_freq = intel_fdi_link_freq(dev) * 10000;
+ else
+ link_freq = pipe_config->port_clock;
+
+ link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
+ link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
+
+ if (!link_m || !link_n)
+ return;
+
+ clock = ((u64)link_m * (u64)link_freq);
+ do_div(clock, link_n);
+
+ pipe_config->adjusted_mode.clock = clock;
+}
+
static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
struct intel_crtc_config *pipe_config)
{
@@ -7280,137 +7411,6 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
mutex_unlock(&crtc->mutex);
}
-/* Returns the clock of the currently programmed mode of the given pipe. */
-static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
-{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- int pipe = pipe_config->cpu_transcoder;
- u32 dpll = I915_READ(DPLL(pipe));
- u32 fp;
- intel_clock_t clock;
-
- if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
- fp = I915_READ(FP0(pipe));
- else
- fp = I915_READ(FP1(pipe));
-
- clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
- if (IS_PINEVIEW(dev)) {
- clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
- clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
- } else {
- clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
- clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
- }
-
- if (!IS_GEN2(dev)) {
- if (IS_PINEVIEW(dev))
- clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
- DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
- else
- clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
- DPLL_FPA01_P1_POST_DIV_SHIFT);
-
- switch (dpll & DPLL_MODE_MASK) {
- case DPLLB_MODE_DAC_SERIAL:
- clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
- 5 : 10;
- break;
- case DPLLB_MODE_LVDS:
- clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
- 7 : 14;
- break;
- default:
- DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
- "mode\n", (int)(dpll & DPLL_MODE_MASK));
- pipe_config->adjusted_mode.clock = 0;
- return;
- }
-
- if (IS_PINEVIEW(dev))
- pineview_clock(96000, &clock);
- else
- i9xx_clock(96000, &clock);
- } else {
- bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
-
- if (is_lvds) {
- clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
- DPLL_FPA01_P1_POST_DIV_SHIFT);
- clock.p2 = 14;
-
- if ((dpll & PLL_REF_INPUT_MASK) ==
- PLLB_REF_INPUT_SPREADSPECTRUMIN) {
- /* XXX: might not be 66MHz */
- i9xx_clock(66000, &clock);
- } else
- i9xx_clock(48000, &clock);
- } else {
- if (dpll & PLL_P1_DIVIDE_BY_TWO)
- clock.p1 = 2;
- else {
- clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
- DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
- }
- if (dpll & PLL_P2_DIVIDE_BY_4)
- clock.p2 = 4;
- else
- clock.p2 = 2;
-
- i9xx_clock(48000, &clock);
- }
- }
-
- pipe_config->adjusted_mode.clock = clock.dot;
-}
-
-static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
- struct intel_crtc_config *pipe_config)
-{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
- int link_freq;
- u64 clock;
- u32 link_m, link_n;
-
- /*
- * The calculation for the data clock is:
- * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
- * But we want to avoid losing precison if possible, so:
- * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
- *
- * and the link clock is simpler:
- * link_clock = (m * link_clock) / n
- */
-
- /*
- * We need to get the FDI or DP link clock here to derive
- * the M/N dividers.
- *
- * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
- * For DP, it's either 1.62GHz or 2.7GHz.
- * We do our calculations in 10*MHz since we don't need much precison.
- */
- if (pipe_config->has_pch_encoder)
- link_freq = intel_fdi_link_freq(dev) * 10000;
- else
- link_freq = pipe_config->port_clock;
-
- link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
- link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
-
- if (!link_m || !link_n)
- return;
-
- clock = ((u64)link_m * (u64)link_freq);
- do_div(clock, link_n);
-
- pipe_config->adjusted_mode.clock = clock;
-}
-
/** Returns the currently programmed mode of the given pipe. */
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
struct drm_crtc *crtc)
--
1.8.1.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 4/8] drm/i915: Move i9xx_crtc_clock_get() and ironlake_crtc_clock_get() earlier
2013-09-04 11:14 ` [PATCH 4/8] drm/i915: Move i9xx_crtc_clock_get() and ironlake_crtc_clock_get() earlier ville.syrjala
@ 2013-09-04 13:22 ` Jani Nikula
0 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2013-09-04 13:22 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Wed, 04 Sep 2013, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move i9xx_crtc_clock_get() and ironlake_crtc_clock_get() around to avoid
> forward declarations, as we will soon call these directly from
> i9xx_get_pipe_config() and ironlake_get_pipe_config() respectively,
>
> No functional changes.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 262 +++++++++++++++++------------------
> 1 file changed, 131 insertions(+), 131 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b991acd..74affb1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4985,6 +4985,92 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
> I915_READ(LVDS) & LVDS_BORDER_ENABLE;
> }
>
> +/* Returns the clock of the currently programmed mode of the given pipe. */
> +static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
> + struct intel_crtc_config *pipe_config)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + int pipe = pipe_config->cpu_transcoder;
> + u32 dpll = I915_READ(DPLL(pipe));
> + u32 fp;
> + intel_clock_t clock;
> +
> + if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
> + fp = I915_READ(FP0(pipe));
> + else
> + fp = I915_READ(FP1(pipe));
> +
> + clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
> + if (IS_PINEVIEW(dev)) {
> + clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
> + clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
> + } else {
> + clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
> + clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
> + }
> +
> + if (!IS_GEN2(dev)) {
> + if (IS_PINEVIEW(dev))
> + clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
> + DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
> + else
> + clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
> + DPLL_FPA01_P1_POST_DIV_SHIFT);
> +
> + switch (dpll & DPLL_MODE_MASK) {
> + case DPLLB_MODE_DAC_SERIAL:
> + clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
> + 5 : 10;
> + break;
> + case DPLLB_MODE_LVDS:
> + clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
> + 7 : 14;
> + break;
> + default:
> + DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
> + "mode\n", (int)(dpll & DPLL_MODE_MASK));
> + pipe_config->adjusted_mode.clock = 0;
> + return;
> + }
> +
> + if (IS_PINEVIEW(dev))
> + pineview_clock(96000, &clock);
> + else
> + i9xx_clock(96000, &clock);
> + } else {
> + bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
> +
> + if (is_lvds) {
> + clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
> + DPLL_FPA01_P1_POST_DIV_SHIFT);
> + clock.p2 = 14;
> +
> + if ((dpll & PLL_REF_INPUT_MASK) ==
> + PLLB_REF_INPUT_SPREADSPECTRUMIN) {
> + /* XXX: might not be 66MHz */
> + i9xx_clock(66000, &clock);
> + } else
> + i9xx_clock(48000, &clock);
> + } else {
> + if (dpll & PLL_P1_DIVIDE_BY_TWO)
> + clock.p1 = 2;
> + else {
> + clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
> + DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
> + }
> + if (dpll & PLL_P2_DIVIDE_BY_4)
> + clock.p2 = 4;
> + else
> + clock.p2 = 2;
> +
> + i9xx_clock(48000, &clock);
> + }
> + }
> +
> + pipe_config->adjusted_mode.clock = clock.dot;
> +}
> +
> static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> struct intel_crtc_config *pipe_config)
> {
> @@ -5901,6 +5987,51 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
> }
> }
>
> +static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
> + struct intel_crtc_config *pipe_config)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> + int link_freq;
> + u64 clock;
> + u32 link_m, link_n;
> +
> + /*
> + * The calculation for the data clock is:
> + * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
> + * But we want to avoid losing precison if possible, so:
> + * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
> + *
> + * and the link clock is simpler:
> + * link_clock = (m * link_clock) / n
> + */
> +
> + /*
> + * We need to get the FDI or DP link clock here to derive
> + * the M/N dividers.
> + *
> + * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
> + * For DP, it's either 1.62GHz or 2.7GHz.
> + * We do our calculations in 10*MHz since we don't need much precison.
> + */
> + if (pipe_config->has_pch_encoder)
> + link_freq = intel_fdi_link_freq(dev) * 10000;
> + else
> + link_freq = pipe_config->port_clock;
> +
> + link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
> + link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
> +
> + if (!link_m || !link_n)
> + return;
> +
> + clock = ((u64)link_m * (u64)link_freq);
> + do_div(clock, link_n);
> +
> + pipe_config->adjusted_mode.clock = clock;
> +}
> +
> static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
> struct intel_crtc_config *pipe_config)
> {
> @@ -7280,137 +7411,6 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
> mutex_unlock(&crtc->mutex);
> }
>
> -/* Returns the clock of the currently programmed mode of the given pipe. */
> -static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
> - struct intel_crtc_config *pipe_config)
> -{
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - int pipe = pipe_config->cpu_transcoder;
> - u32 dpll = I915_READ(DPLL(pipe));
> - u32 fp;
> - intel_clock_t clock;
> -
> - if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
> - fp = I915_READ(FP0(pipe));
> - else
> - fp = I915_READ(FP1(pipe));
> -
> - clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
> - if (IS_PINEVIEW(dev)) {
> - clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
> - clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
> - } else {
> - clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
> - clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
> - }
> -
> - if (!IS_GEN2(dev)) {
> - if (IS_PINEVIEW(dev))
> - clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
> - DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
> - else
> - clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
> - DPLL_FPA01_P1_POST_DIV_SHIFT);
> -
> - switch (dpll & DPLL_MODE_MASK) {
> - case DPLLB_MODE_DAC_SERIAL:
> - clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
> - 5 : 10;
> - break;
> - case DPLLB_MODE_LVDS:
> - clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
> - 7 : 14;
> - break;
> - default:
> - DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
> - "mode\n", (int)(dpll & DPLL_MODE_MASK));
> - pipe_config->adjusted_mode.clock = 0;
> - return;
> - }
> -
> - if (IS_PINEVIEW(dev))
> - pineview_clock(96000, &clock);
> - else
> - i9xx_clock(96000, &clock);
> - } else {
> - bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
> -
> - if (is_lvds) {
> - clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
> - DPLL_FPA01_P1_POST_DIV_SHIFT);
> - clock.p2 = 14;
> -
> - if ((dpll & PLL_REF_INPUT_MASK) ==
> - PLLB_REF_INPUT_SPREADSPECTRUMIN) {
> - /* XXX: might not be 66MHz */
> - i9xx_clock(66000, &clock);
> - } else
> - i9xx_clock(48000, &clock);
> - } else {
> - if (dpll & PLL_P1_DIVIDE_BY_TWO)
> - clock.p1 = 2;
> - else {
> - clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
> - DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
> - }
> - if (dpll & PLL_P2_DIVIDE_BY_4)
> - clock.p2 = 4;
> - else
> - clock.p2 = 2;
> -
> - i9xx_clock(48000, &clock);
> - }
> - }
> -
> - pipe_config->adjusted_mode.clock = clock.dot;
> -}
> -
> -static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
> - struct intel_crtc_config *pipe_config)
> -{
> - struct drm_device *dev = crtc->base.dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> - int link_freq;
> - u64 clock;
> - u32 link_m, link_n;
> -
> - /*
> - * The calculation for the data clock is:
> - * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
> - * But we want to avoid losing precison if possible, so:
> - * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
> - *
> - * and the link clock is simpler:
> - * link_clock = (m * link_clock) / n
> - */
> -
> - /*
> - * We need to get the FDI or DP link clock here to derive
> - * the M/N dividers.
> - *
> - * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
> - * For DP, it's either 1.62GHz or 2.7GHz.
> - * We do our calculations in 10*MHz since we don't need much precison.
> - */
> - if (pipe_config->has_pch_encoder)
> - link_freq = intel_fdi_link_freq(dev) * 10000;
> - else
> - link_freq = pipe_config->port_clock;
> -
> - link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
> - link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
> -
> - if (!link_m || !link_n)
> - return;
> -
> - clock = ((u64)link_m * (u64)link_freq);
> - do_div(clock, link_n);
> -
> - pipe_config->adjusted_mode.clock = clock;
> -}
> -
> /** Returns the currently programmed mode of the given pipe. */
> struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
> struct drm_crtc *crtc)
> --
> 1.8.1.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 5/8] drm/i915: Fix port_clock readout for SDVO and HDMI 12bpc cases
2013-09-04 11:14 [PATCH 0/8] drm/i915: adjusted_mode.clock vs. port_clock v2 ville.syrjala
` (3 preceding siblings ...)
2013-09-04 11:14 ` [PATCH 4/8] drm/i915: Move i9xx_crtc_clock_get() and ironlake_crtc_clock_get() earlier ville.syrjala
@ 2013-09-04 11:14 ` ville.syrjala
2013-09-06 13:24 ` [PATCH] drm/i915: Fix issues caused from get_clock elimination ville.syrjala
2013-09-04 11:14 ` [PATCH 6/8] drm/i915: Make intel_fuzzy_clock_check() take in arbitrary clocks ville.syrjala
` (2 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: ville.syrjala @ 2013-09-04 11:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Now that adjusted_mode.clock no longer contains the pixel_multiplier, we
can kill the get_clock() callback and instead read out the DPLL stuff in
get_pipe_config().
We start by filling out both adjusted_mode.clock and port_clock in
i9xx_crtc_clock_get() and ironlake_crtc_clock_get(). We must keep in
mind that now both clocks include pixel_multiplier on non-PCH
platforms, and on PCH platforms neither clock includes pixel_multiplier.
We fix that up in the encoders' get_config() functions after we've
determined the actual value of pixel_multiplier.
We can also use the pipe_bpp value to fix up port_clock for the 12bpc
HDMI case on PCH platforms.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_display.c | 32 +++++++++++++++-----------------
drivers/gpu/drm/i915/intel_hdmi.c | 3 +++
drivers/gpu/drm/i915/intel_sdvo.c | 11 +++++++++++
4 files changed, 29 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 769c138..09fc308 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -369,7 +369,6 @@ struct drm_i915_display_funcs {
* fills out the pipe-config with the hw state. */
bool (*get_pipe_config)(struct intel_crtc *,
struct intel_crtc_config *);
- void (*get_clock)(struct intel_crtc *, struct intel_crtc_config *);
int (*crtc_mode_set)(struct drm_crtc *crtc,
int x, int y,
struct drm_framebuffer *old_fb);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 74affb1..8fcb8db 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5068,7 +5068,12 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
}
}
- pipe_config->adjusted_mode.clock = clock.dot;
+ /*
+ * This value includes pixel_multiplier. We will fix
+ * adjusted_mode.clock in the encoder's get_config()
+ * function if necessary.
+ */
+ pipe_config->port_clock = pipe_config->adjusted_mode.clock = clock.dot;
}
static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
@@ -5133,6 +5138,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
}
}
+ i9xx_crtc_clock_get(crtc, pipe_config);
+
return true;
}
@@ -6029,7 +6036,11 @@ static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
clock = ((u64)link_m * (u64)link_freq);
do_div(clock, link_n);
- pipe_config->adjusted_mode.clock = clock;
+ /*
+ * This value does not include pixel_multiplier. We will fix
+ * port_clock in the encoder's get_config() function if necessary.
+ */
+ pipe_config->port_clock = pipe_config->adjusted_mode.clock = clock;
}
static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
@@ -6102,6 +6113,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
ironlake_get_pfit_config(crtc, pipe_config);
+ ironlake_crtc_clock_get(crtc, pipe_config);
+
return true;
}
@@ -8811,9 +8824,6 @@ check_crtc_state(struct drm_device *dev)
encoder->get_config(encoder, &pipe_config);
}
- if (dev_priv->display.get_clock)
- dev_priv->display.get_clock(crtc, &pipe_config);
-
WARN(crtc->active != active,
"crtc active state doesn't match with hw state "
"(expected %i, found %i)\n", crtc->active, active);
@@ -9839,7 +9849,6 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.update_plane = ironlake_update_plane;
} else if (HAS_PCH_SPLIT(dev)) {
dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
- dev_priv->display.get_clock = ironlake_crtc_clock_get;
dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
dev_priv->display.crtc_enable = ironlake_crtc_enable;
dev_priv->display.crtc_disable = ironlake_crtc_disable;
@@ -9847,7 +9856,6 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.update_plane = ironlake_update_plane;
} else if (IS_VALLEYVIEW(dev)) {
dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
- dev_priv->display.get_clock = i9xx_crtc_clock_get;
dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
dev_priv->display.crtc_enable = valleyview_crtc_enable;
dev_priv->display.crtc_disable = i9xx_crtc_disable;
@@ -9855,7 +9863,6 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.update_plane = i9xx_update_plane;
} else {
dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
- dev_priv->display.get_clock = i9xx_crtc_clock_get;
dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
dev_priv->display.crtc_enable = i9xx_crtc_enable;
dev_priv->display.crtc_disable = i9xx_crtc_disable;
@@ -10469,15 +10476,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
pipe);
}
- list_for_each_entry(crtc, &dev->mode_config.crtc_list,
- base.head) {
- if (!crtc->active)
- continue;
- if (dev_priv->display.get_clock)
- dev_priv->display.get_clock(crtc,
- &crtc->config);
- }
-
list_for_each_entry(connector, &dev->mode_config.connector_list,
base.head) {
if (connector->get_hw_state(connector)) {
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 4148cc8..3d833a3 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -727,6 +727,9 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
flags |= DRM_MODE_FLAG_NVSYNC;
pipe_config->adjusted_mode.flags |= flags;
+
+ if (pipe_config->pipe_bpp == 12*3)
+ pipe_config->port_clock = pipe_config->adjusted_mode.clock * 3 / 2;
}
static void intel_enable_hdmi(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 74042c6..4c1b9ac 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1357,6 +1357,17 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
>> SDVO_PORT_MULTIPLY_SHIFT) + 1;
}
+ /*
+ * On PCH platforms our clock doesn't yet include the pixel
+ * multiplier, whereas on non-PCH platforms it already does.
+ */
+ if (HAS_PCH_SPLIT(dev))
+ pipe_config->port_clock = pipe_config->adjusted_mode.clock *
+ pipe_config->pixel_multiplier;
+ else
+ pipe_config->adjusted_mode.clock = pipe_config->port_clock /
+ pipe_config->pixel_multiplier;
+
/* Cross check the port pixel multiplier with the sdvo encoder state. */
if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
&val, 1)) {
--
1.8.1.5
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH] drm/i915: Fix issues caused from get_clock elimination
2013-09-04 11:14 ` [PATCH 5/8] drm/i915: Fix port_clock readout for SDVO and HDMI 12bpc cases ville.syrjala
@ 2013-09-06 13:24 ` ville.syrjala
2013-09-06 16:00 ` Daniel Vetter
0 siblings, 1 reply; 14+ messages in thread
From: ville.syrjala @ 2013-09-06 13:24 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
For non-PCH encoders ironlake_crtc_clock_get() attempts to extract
adjusted_mode.clock from port_clock. But now that we call
ironlake_crtc_clock_get() before the encoders' get_config() that no
longer works.
To fix the problem also call ironlake_crtc_clock_get() before
get_config() for PCH encoders, and afterwards for non-PCH encoders.
Also be careful not to clobber port_clock when calling it afterwards.
The problem was introduced by:
"drm/i915: Fix port_clock readout for SDVO and HDMI 12bpc cases"
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
This could be squashed with the patch that caused the problem in the first
place, but I left it separate for now to solicit feedback on how ugly do
people think this is. I could of course leave the get_clock callback
in place, but only fill it in for ILK+ and add a has_pch_encoder check
there, otherwise we could keep the direct func call in get_pipe_config.
drivers/gpu/drm/i915/intel_display.c | 23 ++++++++++++++++++++---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5b8a437..3cfd99b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6040,7 +6040,14 @@ static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
* This value does not include pixel_multiplier. We will fix
* port_clock in the encoder's get_config() function if necessary.
*/
- pipe_config->port_clock = pipe_config->adjusted_mode.clock = clock;
+ pipe_config->adjusted_mode.clock = clock;
+
+ /*
+ * We get called before encoder get_config() for pch encoders,
+ * after for non-pch. Don't clobber port_clock in the latter case.
+ */
+ if (!pipe_config->port_clock)
+ pipe_config->port_clock = clock;
}
static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
@@ -6105,6 +6112,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
pipe_config->pixel_multiplier =
((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
>> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
+
+ ironlake_crtc_clock_get(crtc, pipe_config);
} else {
pipe_config->pixel_multiplier = 1;
}
@@ -6113,8 +6122,6 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
ironlake_get_pfit_config(crtc, pipe_config);
- ironlake_crtc_clock_get(crtc, pipe_config);
-
return true;
}
@@ -8827,6 +8834,9 @@ check_crtc_state(struct drm_device *dev)
encoder->get_config(encoder, &pipe_config);
}
+ if (HAS_PCH_SPLIT(dev) && !pipe_config.has_pch_encoder)
+ ironlake_crtc_clock_get(crtc, &pipe_config);
+
WARN(crtc->active != active,
"crtc active state doesn't match with hw state "
"(expected %i, found %i)\n", crtc->active, active);
@@ -10479,6 +10489,13 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
pipe);
}
+ if (HAS_PCH_SPLIT(dev)) {
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
+ if (!crtc->config.has_pch_encoder)
+ ironlake_crtc_clock_get(crtc, &crtc->config);
+ }
+ }
+
list_for_each_entry(connector, &dev->mode_config.connector_list,
base.head) {
if (connector->get_hw_state(connector)) {
--
1.8.1.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH] drm/i915: Fix issues caused from get_clock elimination
2013-09-06 13:24 ` [PATCH] drm/i915: Fix issues caused from get_clock elimination ville.syrjala
@ 2013-09-06 16:00 ` Daniel Vetter
0 siblings, 0 replies; 14+ messages in thread
From: Daniel Vetter @ 2013-09-06 16:00 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Fri, Sep 06, 2013 at 04:24:17PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> For non-PCH encoders ironlake_crtc_clock_get() attempts to extract
> adjusted_mode.clock from port_clock. But now that we call
> ironlake_crtc_clock_get() before the encoders' get_config() that no
> longer works.
>
> To fix the problem also call ironlake_crtc_clock_get() before
> get_config() for PCH encoders, and afterwards for non-PCH encoders.
> Also be careful not to clobber port_clock when calling it afterwards.
>
> The problem was introduced by:
> "drm/i915: Fix port_clock readout for SDVO and HDMI 12bpc cases"
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Plan B, since this is only a special case for the cpu edp encoder where
the port clock is stored in the encoder. What about we move the full
responsibility for computing the clocks for the cpu edp port to the
encoder callback? ironlake_crtc_get_clock would then more correctly just
be a ironlake_get_pch_clocks or so.
Note that the exact same issue happens for hsw ddi ports where also the
port itself selects the port clock (and as usual for dp with the m/n
stuff then the dotclock). So we need a notch more generic solution here
than just a hack.
Cheers, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 6/8] drm/i915: Make intel_fuzzy_clock_check() take in arbitrary clocks
2013-09-04 11:14 [PATCH 0/8] drm/i915: adjusted_mode.clock vs. port_clock v2 ville.syrjala
` (4 preceding siblings ...)
2013-09-04 11:14 ` [PATCH 5/8] drm/i915: Fix port_clock readout for SDVO and HDMI 12bpc cases ville.syrjala
@ 2013-09-04 11:14 ` ville.syrjala
2013-09-04 11:14 ` [PATCH v2 7/8] drm/i915: Add PIPE_CONF_CHECK_CLOCK_FUZZY() ville.syrjala
2013-09-04 11:14 ` [PATCH v2 8/8] drm/i915: Add fuzzy clock check for port_clock ville.syrjala
7 siblings, 0 replies; 14+ messages in thread
From: ville.syrjala @ 2013-09-04 11:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We want to do fuzzy clock checks for other things besides
adjusted_mode.clock, so just pass two two clocks to compare
to intel_fuzzy_clock_check().
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8fcb8db..2f484e9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8554,13 +8554,9 @@ intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
}
-static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
- struct intel_crtc_config *new)
+static bool intel_fuzzy_clock_check(int clock1, int clock2)
{
- int clock1, clock2, diff;
-
- clock1 = cur->adjusted_mode.clock;
- clock2 = new->adjusted_mode.clock;
+ int diff;
if (clock1 == clock2)
return true;
@@ -8685,7 +8681,8 @@ intel_pipe_config_compare(struct drm_device *dev,
#undef PIPE_CONF_QUIRK
if (!IS_HASWELL(dev)) {
- if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
+ if (!intel_fuzzy_clock_check(current_config->adjusted_mode.clock,
+ pipe_config->adjusted_mode.clock)) {
DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
current_config->adjusted_mode.clock,
pipe_config->adjusted_mode.clock);
--
1.8.1.5
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 7/8] drm/i915: Add PIPE_CONF_CHECK_CLOCK_FUZZY()
2013-09-04 11:14 [PATCH 0/8] drm/i915: adjusted_mode.clock vs. port_clock v2 ville.syrjala
` (5 preceding siblings ...)
2013-09-04 11:14 ` [PATCH 6/8] drm/i915: Make intel_fuzzy_clock_check() take in arbitrary clocks ville.syrjala
@ 2013-09-04 11:14 ` ville.syrjala
2013-09-04 11:14 ` [PATCH v2 8/8] drm/i915: Add fuzzy clock check for port_clock ville.syrjala
7 siblings, 0 replies; 14+ messages in thread
From: ville.syrjala @ 2013-09-04 11:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add a new pipe config check macro PIPE_CONF_CHECK_CLOCK_FUZZY() to make
it trivial and error proof to compare clocks in a fuzzy manner.
v2: Drop extra curly braces
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 23 +++++++++++++----------
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2f484e9..4f06992 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8610,6 +8610,15 @@ intel_pipe_config_compare(struct drm_device *dev,
return false; \
}
+#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
+ if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
+ DRM_ERROR("mismatch in " #name " " \
+ "(expected %i, found %i)\n", \
+ current_config->name, \
+ pipe_config->name); \
+ return false; \
+ }
+
#define PIPE_CONF_QUIRK(quirk) \
((current_config->quirks | pipe_config->quirks) & (quirk))
@@ -8675,21 +8684,15 @@ intel_pipe_config_compare(struct drm_device *dev,
if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
PIPE_CONF_CHECK_I(pipe_bpp);
+ if (!IS_HASWELL(dev))
+ PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.clock);
+
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
#undef PIPE_CONF_CHECK_FLAGS
+#undef PIPE_CONF_CHECK_CLOCK_FUZZY
#undef PIPE_CONF_QUIRK
- if (!IS_HASWELL(dev)) {
- if (!intel_fuzzy_clock_check(current_config->adjusted_mode.clock,
- pipe_config->adjusted_mode.clock)) {
- DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
- current_config->adjusted_mode.clock,
- pipe_config->adjusted_mode.clock);
- return false;
- }
- }
-
return true;
}
--
1.8.1.5
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 8/8] drm/i915: Add fuzzy clock check for port_clock
2013-09-04 11:14 [PATCH 0/8] drm/i915: adjusted_mode.clock vs. port_clock v2 ville.syrjala
` (6 preceding siblings ...)
2013-09-04 11:14 ` [PATCH v2 7/8] drm/i915: Add PIPE_CONF_CHECK_CLOCK_FUZZY() ville.syrjala
@ 2013-09-04 11:14 ` ville.syrjala
7 siblings, 0 replies; 14+ messages in thread
From: ville.syrjala @ 2013-09-04 11:14 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Check and dump for port_clock.
v2: Also dump port_clock
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4f06992..a4fe594 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8262,6 +8262,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
drm_mode_debug_printmodeline(&pipe_config->requested_mode);
DRM_DEBUG_KMS("adjusted mode:\n");
drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
+ DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
pipe_config->gmch_pfit.control,
pipe_config->gmch_pfit.pgm_ratios,
@@ -8684,8 +8685,10 @@ intel_pipe_config_compare(struct drm_device *dev,
if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
PIPE_CONF_CHECK_I(pipe_bpp);
- if (!IS_HASWELL(dev))
+ if (!IS_HASWELL(dev)) {
PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.clock);
+ PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
+ }
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
--
1.8.1.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread