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d="scan'208";a="82705017" Received: from lfiedoro-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.122]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 10:55:26 -0700 From: Jani Nikula To: Ville =?utf-8?B?U3lyasOkbMOk?= Cc: intel-gfx@lists.freedesktop.org Subject: Re: [PATCH 06/11] drm/i915/cdclk: Extract vlv_dsi_min_cdclk() In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20241029215217.3697-1-ville.syrjala@linux.intel.com> <20241029215217.3697-7-ville.syrjala@linux.intel.com> <87frodn7sh.fsf@intel.com> Date: Wed, 30 Oct 2024 19:55:23 +0200 Message-ID: <87cyjhlblg.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, 30 Oct 2024, Ville Syrj=C3=A4l=C3=A4 wrote: > On Wed, Oct 30, 2024 at 01:34:38PM +0200, Jani Nikula wrote: >> On Tue, 29 Oct 2024, Ville Syrjala wrote: >> > From: Ville Syrj=C3=A4l=C3=A4 >> > >> > Pull the DSI min cdclk calculation into a helper and hide >> > it inside vlv_dsi.c in order to keep most DSI related >> > details in one place. >> > >> > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 >> > --- >> > drivers/gpu/drm/i915/display/intel_cdclk.c | 23 ++------------------ >> > drivers/gpu/drm/i915/display/vlv_dsi.c | 25 ++++++++++++++++++++++ >> > drivers/gpu/drm/i915/display/vlv_dsi.h | 8 +++++++ >> > 3 files changed, 35 insertions(+), 21 deletions(-) >> > >> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/= drm/i915/display/intel_cdclk.c >> > index 89d12c521411..e10378744607 100644 >> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c >> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c >> > @@ -46,6 +46,7 @@ >> > #include "intel_vdsc.h" >> > #include "skl_watermark.h" >> > #include "skl_watermark_regs.h" >> > +#include "vlv_dsi.h" >> > #include "vlv_sideband.h" >> >=20=20 >> > /** >> > @@ -2849,8 +2850,6 @@ static int intel_vdsc_min_cdclk(const struct int= el_crtc_state *crtc_state) >> >=20=20 >> > int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_= state) >> > { >> > - struct intel_display *display =3D to_intel_display(crtc_state); >> > - struct drm_i915_private *dev_priv =3D to_i915(display->drm); >> > int min_cdclk; >> >=20=20 >> > if (!crtc_state->hw.enable) >> > @@ -2859,25 +2858,7 @@ int intel_crtc_compute_min_cdclk(const struct i= ntel_crtc_state *crtc_state) >> > min_cdclk =3D intel_pixel_rate_to_cdclk(crtc_state); >> > min_cdclk =3D max(hsw_ips_min_cdclk(crtc_state), min_cdclk); >> > min_cdclk =3D max(intel_audio_min_cdclk(crtc_state), min_cdclk); >> > - >> > - /* >> > - * On Valleyview some DSI panels lose (v|h)sync when the clock is lo= wer >> > - * than 320000KHz. >> > - */ >> > - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && >> > - IS_VALLEYVIEW(dev_priv)) >> > - min_cdclk =3D max(320000, min_cdclk); >> > - >> > - /* >> > - * On Geminilake once the CDCLK gets as low as 79200 >> > - * picture gets unstable, despite that values are >> > - * correct for DSI PLL and DE PLL. >> > - */ >> > - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && >> > - IS_GEMINILAKE(dev_priv)) >> > - min_cdclk =3D max(158400, min_cdclk); >> > - >> > - /* Account for additional needs from the planes */ >> > + min_cdclk =3D max(vlv_dsi_min_cdclk(crtc_state), min_cdclk); >> > min_cdclk =3D max(intel_planes_min_cdclk(crtc_state), min_cdclk); >> >=20=20 >> > if (crtc_state->dsc.compression_enable) >> > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/= i915/display/vlv_dsi.c >> > index 9383eedee2d4..49a895589150 100644 >> > --- a/drivers/gpu/drm/i915/display/vlv_dsi.c >> > +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c >> > @@ -1760,6 +1760,31 @@ static void vlv_dphy_param_init(struct intel_ds= i *intel_dsi) >> > intel_dsi_log_params(intel_dsi); >> > } >> >=20=20 >> > +int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state) >> > +{ >> > + struct drm_i915_private *dev_priv =3D to_i915(crtc_state->uapi.crtc-= >dev); >> > + int min_cdclk =3D 0; >> > + >> > + /* >> > + * On Valleyview some DSI panels lose (v|h)sync when the clock is lo= wer >> > + * than 320000KHz. >> > + */ >> > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && >> > + IS_VALLEYVIEW(dev_priv)) >> > + min_cdclk =3D max(320000, min_cdclk); >> > + >> > + /* >> > + * On Geminilake once the CDCLK gets as low as 79200 >> > + * picture gets unstable, despite that values are >> > + * correct for DSI PLL and DE PLL. >> > + */ >> > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && >> > + IS_GEMINILAKE(dev_priv)) >> > + min_cdclk =3D max(158400, min_cdclk); >> > + >> > + return min_cdclk; >> > +} >> > + >> > typedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *intel_dsi); >> >=20=20 >> > /* >> > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.h b/drivers/gpu/drm/= i915/display/vlv_dsi.h >> > index cf9d7b82f288..5f99059b4c48 100644 >> > --- a/drivers/gpu/drm/i915/display/vlv_dsi.h >> > +++ b/drivers/gpu/drm/i915/display/vlv_dsi.h >> > @@ -8,13 +8,17 @@ >> >=20=20 >> > #include >> >=20=20 >> > +#include >> > + >>=20 >> Huh, why is this required? At least it's unrelated to the patch. > > Sorry meant to note that in the commit msg, but forgot. > > xe fails to build without this: > ../drivers/gpu/drm/i915/display/vlv_dsi.h:28:42: error: return type is an= incomplete type > > It looks like a forward declaration is not enough for > return types of static inline functions. i915 on the other > hand builds fine. > > I suppose one alternative would be to declare is as just > 'int' for xe. I think I've actually snuck in some of those int usages in the past, because in the end it doesn't really matter for the inline stubs. BR, Jani. > >>=20 >> Other than that, >>=20 >> Reviewed-by: Jani Nikula >>=20 >>=20 >> > enum port; >> > struct drm_i915_private; >> > +struct intel_crtc_state; >> > struct intel_dsi; >> >=20=20 >> > #ifdef I915 >> > void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum po= rt port); >> > enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt); >> > +int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state); >> > void vlv_dsi_init(struct drm_i915_private *dev_priv); >> > #else >> > static inline void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *inte= l_dsi, enum port port) >> > @@ -24,6 +28,10 @@ static inline enum mipi_dsi_pixel_format pixel_form= at_from_register_bits(u32 fmt >> > { >> > return 0; >> > } >> > +static inline int vlv_dsi_min_cdclk(const struct intel_crtc_state *cr= tc_state) >> > +{ >> > + return 0; >> > +} >> > static inline void vlv_dsi_init(struct drm_i915_private *dev_priv) >> > { >> > } >>=20 >> --=20 >> Jani Nikula, Intel --=20 Jani Nikula, Intel