Re: [Intel-gfx] [PATCH 5/8] drm/i915/dp: rewrite DP 2.0 128b/132b link training based on errata

[Jani Nikula <jani.nikula@intel.com>]

On Thu, 27 Jan 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, Jan 25, 2022 at 07:03:43PM +0200, Jani Nikula wrote:
> <snip>
>> +static bool
>> +intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp,
>> +			   const struct intel_crtc_state *crtc_state,
>> +			   int lttpr_count)
>> +{
>> +	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>> +	u8 link_status[DP_LINK_STATUS_SIZE];
>> +	unsigned long deadline;
>> +
>> +	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
>> +			       DP_TRAINING_PATTERN_2_CDS) != 1) {
>> +		drm_err(&i915->drm,
>> +			"[ENCODER:%d:%s] Failed to start 128b/132b TPS2 CDS\n",
>> +			encoder->base.base.id, encoder->base.name);
>> +		return false;
>> +	}
>> +
>> +	deadline = jiffies + msecs_to_jiffies((lttpr_count + 1) * 20);
>> +	for (;;) {
>> +		usleep_range(2000, 3000);
>> +
>> +		if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
>> +			drm_err(&i915->drm,
>> +				"[ENCODER:%d:%s] Failed to read link status\n",
>> +				encoder->base.base.id, encoder->base.name);
>> +			return false;
>> +		}
>> +
>> +		if (drm_dp_128b132b_cds_interlane_align_done(link_status) &&
>> +		    drm_dp_128b132b_lane_symbol_locked(link_status, crtc_state->lane_count)) {
>
> I'm thinkin we want to check for both eq done and symbol locked here,
> just like we do with 8b10b.

I guess so, although I don't think the spec explicitly calls that out.

Fixed anyway.

>
>> +			drm_dbg_kms(&i915->drm,
>> +				    "[ENCODER:%d:%s] CDS interlane align done\n",
>> +				    encoder->base.base.id, encoder->base.name);
>> +			break;
>> +		}
>> +
>> +		if (drm_dp_128b132b_link_training_failed(link_status)) {
>> +			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
>> +			drm_err(&i915->drm,
>> +				"[ENCODER:%d:%s] Downstream link training failure\n",
>> +				encoder->base.base.id, encoder->base.name);
>> +			return false;
>> +		}
>> +
>> +		if (time_after(jiffies, deadline)) {
>> +			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
>> +			drm_err(&i915->drm,
>> +				"[ENCODER:%d:%s] CDS timeout\n",
>> +				encoder->base.base.id, encoder->base.name);
>> +			return false;
>> +		}
>> +	}
>> +
>> +	/* FIXME: Should DP_TRAINING_PATTERN_DISABLE be written first? */
>> +	if (intel_dp->set_idle_link_train)
>> +		intel_dp->set_idle_link_train(intel_dp, crtc_state);
>> +
>> +	return true;
>> +}

-- 
Jani Nikula, Intel Open Source Graphics Center