From: Jani Nikula <jani.nikula@intel.com>
To: Madhav Chauhan <madhav.chauhan@intel.com>,
intel-gfx@lists.freedesktop.org
Cc: ander.conselvan.de.oliveira@intel.com, Deepak M <m.deepak@intel.com>
Subject: Re: [GLK MIPI DSI V4 1/8] drm/i915/glk: Program dphy param reg for GLK
Date: Wed, 08 Feb 2017 16:53:44 +0200 [thread overview]
Message-ID: <87d1esu41z.fsf@intel.com> (raw)
In-Reply-To: <1486471392-1803-2-git-send-email-madhav.chauhan@intel.com>
On Tue, 07 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Deepak M <m.deepak@intel.com>
>
> For GEMINILAKE, dphy param reg values are programmed in terms
> of HS byte clock count while for older platforms in terms of
> HS ddr clk count.
>
> v2: Added comments to clarify ddr clock count calculation
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 45 ++++++++++++++++++++----------
> 1 file changed, 31 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 8f683b8..b3c495f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -674,11 +674,6 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
> break;
> }
>
> - /*
> - * ui(s) = 1/f [f in hz]
> - * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
> - */
> -
> /* in Kbps */
> ui_num = NS_KHZ_RATIO;
> ui_den = bitrate;
> @@ -692,19 +687,32 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
> */
> intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
>
> - /* count values in UI = (ns value) * (bitrate / (2 * 10^6))
> + /* DDR clock period = 2 * UI
> + * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
> + * UI(nsec) = 10^6 / bitrate
> + * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
> + * DDR clock count = ns_value / DDR clock period
> *
> - * Since txddrclkhs_i is 2xUI, all the count values programmed in
> - * DPHY param register are divided by 2
> + * For GEMINILAKE dphy_param_reg will be programmed in terms of
> + * HS byte clock count for other platform in HS ddr clock count
Please add something like,
int mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
and use ui_num * mul instead of spreading IS_GEMINILAKE() check
everywhere.
BR,
Jani.
> *
> * prepare count
> */
> ths_prepare_ns = max(mipi_config->ths_prepare,
> mipi_config->tclk_prepare);
> - prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
> + if (IS_GEMINILAKE(dev_priv))
> + prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 8);
> + else
> + prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
>
> /* exit zero count */
> - exit_zero_cnt = DIV_ROUND_UP(
> + if (IS_GEMINILAKE(dev_priv))
> + exit_zero_cnt = DIV_ROUND_UP(
> + (ths_prepare_hszero - ths_prepare_ns) * ui_den,
> + ui_num * 8
> + );
> + else
> + exit_zero_cnt = DIV_ROUND_UP(
> (ths_prepare_hszero - ths_prepare_ns) * ui_den,
> ui_num * 2
> );
> @@ -719,13 +727,22 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
> exit_zero_cnt += 1;
>
> /* clk zero count */
> - clk_zero_cnt = DIV_ROUND_UP(
> - (tclk_prepare_clkzero - ths_prepare_ns)
> - * ui_den, 2 * ui_num);
> + if (IS_GEMINILAKE(dev_priv))
> + clk_zero_cnt = DIV_ROUND_UP(
> + (tclk_prepare_clkzero - ths_prepare_ns)
> + * ui_den, 8 * ui_num);
> + else
> + clk_zero_cnt = DIV_ROUND_UP(
> + (tclk_prepare_clkzero - ths_prepare_ns)
> + * ui_den, 2 * ui_num);
>
> /* trail count */
> tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
> - trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
> +
> + if (IS_GEMINILAKE(dev_priv))
> + trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 8 * ui_num);
> + else
> + trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
>
> if (prepare_cnt > PREPARE_CNT_MAX ||
> exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2017-02-08 14:53 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-07 12:43 [GLK MIPI DSI V4 0/8] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 1/8] drm/i915/glk: Program dphy param reg for GLK Madhav Chauhan
2017-02-08 14:53 ` Jani Nikula [this message]
2017-02-08 17:27 ` Chauhan, Madhav
2017-02-07 12:43 ` [GLK MIPI DSI V4 2/8] drm/i915/glk: Program new MIPI DSI PHY registers " Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 3/8] drm/i915/glk: Add MIPIIO Enable/disable sequence Madhav Chauhan
2017-02-08 14:58 ` Jani Nikula
2017-02-08 17:51 ` Chauhan, Madhav
2017-02-07 12:43 ` [GLK MIPI DSI V4 4/8] drm/i915: Set the Z inversion overlap field Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 5/8] drm/i915/glk: Add DSI PLL divider range for glk Madhav Chauhan
2017-02-10 14:24 ` Ander Conselvan De Oliveira
2017-02-13 11:14 ` Chauhan, Madhav
2017-02-07 12:43 ` [GLK MIPI DSI V4 6/8] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 7/8] drm/i915/glk: Program txesc clock divider for GLK Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 8/8] drm/i915/glk: Validate only DSI PORT A PLL divider Madhav Chauhan
2017-02-07 13:24 ` ✗ Fi.CI.BAT: failure for GLK MIPI DSI VIDEO MODE PATCHES (rev4) Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87d1esu41z.fsf@intel.com \
--to=jani.nikula@intel.com \
--cc=ander.conselvan.de.oliveira@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=m.deepak@intel.com \
--cc=madhav.chauhan@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox