* [PATCH 1/3] drm/i915: remove parens around revision ids @ 2015-10-06 11:41 Jani Nikula 2015-10-06 11:41 ` [PATCH 2/3] drm/i915/bxt: add revision id for A1 stepping and use it Jani Nikula 2015-10-06 11:41 ` [PATCH 3/3] drm/i915: add helpers for platform specific revision id range checks Jani Nikula 0 siblings, 2 replies; 10+ messages in thread From: Jani Nikula @ 2015-10-06 11:41 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, Rodrigo Vivi Totally unnecessary. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 51eea2951c0f..a3b137715604 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2501,16 +2501,16 @@ struct drm_i915_cmd_table { #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) -#define SKL_REVID_A0 (0x0) -#define SKL_REVID_B0 (0x1) -#define SKL_REVID_C0 (0x2) -#define SKL_REVID_D0 (0x3) -#define SKL_REVID_E0 (0x4) -#define SKL_REVID_F0 (0x5) - -#define BXT_REVID_A0 (0x0) -#define BXT_REVID_B0 (0x3) -#define BXT_REVID_C0 (0x9) +#define SKL_REVID_A0 0x0 +#define SKL_REVID_B0 0x1 +#define SKL_REVID_C0 0x2 +#define SKL_REVID_D0 0x3 +#define SKL_REVID_E0 0x4 +#define SKL_REVID_F0 0x5 + +#define BXT_REVID_A0 0x0 +#define BXT_REVID_B0 0x3 +#define BXT_REVID_C0 0x9 /* * The genX designation typically refers to the render engine, so render -- 2.1.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/3] drm/i915/bxt: add revision id for A1 stepping and use it 2015-10-06 11:41 [PATCH 1/3] drm/i915: remove parens around revision ids Jani Nikula @ 2015-10-06 11:41 ` Jani Nikula 2015-10-06 12:29 ` Ville Syrjälä 2015-10-06 11:41 ` [PATCH 3/3] drm/i915: add helpers for platform specific revision id range checks Jani Nikula 1 sibling, 1 reply; 10+ messages in thread From: Jani Nikula @ 2015-10-06 11:41 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, Rodrigo Vivi Prefer inclusive ranges for revision checks rather than "below B0". Per specs A2 is not used, so revid <= A1 matches revid < B0. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/i915_guc_submission.c | 2 +- drivers/gpu/drm/i915/intel_ddi.c | 2 +- drivers/gpu/drm/i915/intel_dp.c | 2 +- drivers/gpu/drm/i915/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/intel_lrc.c | 8 ++++---- drivers/gpu/drm/i915/intel_pm.c | 6 +++--- drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++--- 9 files changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a3b137715604..9833a2055930 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2509,6 +2509,7 @@ struct drm_i915_cmd_table { #define SKL_REVID_F0 0x5 #define BXT_REVID_A0 0x0 +#define BXT_REVID_A1 0x1 #define BXT_REVID_B0 0x3 #define BXT_REVID_C0 0x9 diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index f0cfbb9ee12c..fd2d880656b2 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3757,7 +3757,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, * cacheline, whereas normally such cachelines would get * invalidated. */ - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) return -ENODEV; level = I915_CACHE_LLC; diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index 036b42bae827..863aa5c82466 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -161,7 +161,7 @@ static int host2guc_sample_forcewake(struct intel_guc *guc, data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE; /* WaRsDisableCoarsePowerGating:skl,bxt */ if (!intel_enable_rc6(dev_priv->dev) || - (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || + (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) || (IS_SKL_GT3(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)) || (IS_SKL_GT4(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0))) data[1] = 0; diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index b25e99a432fb..b80e0f5ec5dc 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -3247,7 +3247,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port) * On BXT A0/A1, sw needs to activate DDIA HPD logic and * interrupts to check the external panel connection. */ - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0) + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1) && port == PORT_B) dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port; else diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 8d34ca7b287a..8baf6fe06313 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -6087,7 +6087,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, break; case PORT_B: intel_encoder->hpd_pin = HPD_PORT_B; - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1)) intel_encoder->hpd_pin = HPD_PORT_A; break; case PORT_C: diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 03d85909c6ab..32e9117ee8e3 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -2068,7 +2068,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, * On BXT A0/A1, sw needs to activate DDIA HPD logic and * interrupts to check the external panel connection. */ - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1)) intel_encoder->hpd_pin = HPD_PORT_A; else intel_encoder->hpd_pin = HPD_PORT_B; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 825fa7a8df86..acd4fa332a80 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1986,7 +1986,7 @@ static int logical_render_ring_init(struct drm_device *dev) ring->init_hw = gen8_init_render_ring; ring->init_context = gen8_init_rcs_context; ring->cleanup = intel_fini_pipe_control; - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { ring->get_seqno = bxt_a_get_seqno; ring->set_seqno = bxt_a_set_seqno; } else { @@ -2038,7 +2038,7 @@ static int logical_bsd_ring_init(struct drm_device *dev) GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; ring->init_hw = gen8_init_common_ring; - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { ring->get_seqno = bxt_a_get_seqno; ring->set_seqno = bxt_a_set_seqno; } else { @@ -2093,7 +2093,7 @@ static int logical_blt_ring_init(struct drm_device *dev) GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; ring->init_hw = gen8_init_common_ring; - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { ring->get_seqno = bxt_a_get_seqno; ring->set_seqno = bxt_a_set_seqno; } else { @@ -2123,7 +2123,7 @@ static int logical_vebox_ring_init(struct drm_device *dev) GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; ring->init_hw = gen8_init_common_ring; - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { ring->get_seqno = bxt_a_get_seqno; ring->set_seqno = bxt_a_set_seqno; } else { diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 60d120c472ab..e25791e8748f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4348,7 +4348,7 @@ static void gen6_set_rps(struct drm_device *dev, u8 val) struct drm_i915_private *dev_priv = dev->dev_private; /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ - if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) return; WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); @@ -4672,7 +4672,7 @@ static void gen9_enable_rps(struct drm_device *dev) gen6_init_rps_frequencies(dev); /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ - if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) { + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) { intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); return; } @@ -4758,7 +4758,7 @@ static void gen9_enable_rc6(struct drm_device *dev) * 3b: Enable Coarse Power Gating only when RC6 is enabled. * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. */ - if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || + if ((IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) || ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0))) I915_WRITE(GEN9_PG_ENABLE, 0); else diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index c82c74caa73c..3753e7518d49 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -916,14 +916,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 || INTEL_REVID(dev) == SKL_REVID_B0)) || - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) { + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) { /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, GEN9_DG_MIRROR_FIX_ENABLE); } if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) { + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) { /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, GEN9_RHWO_OPTIMIZATION_DISABLE); @@ -952,7 +952,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) /* WaDisableMaskBasedCammingInRCC:skl,bxt */ if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) || - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, PIXEL_MASK_CAMMING_DISABLE); -- 2.1.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] drm/i915/bxt: add revision id for A1 stepping and use it 2015-10-06 11:41 ` [PATCH 2/3] drm/i915/bxt: add revision id for A1 stepping and use it Jani Nikula @ 2015-10-06 12:29 ` Ville Syrjälä 2015-10-06 13:43 ` Jani Nikula 0 siblings, 1 reply; 10+ messages in thread From: Ville Syrjälä @ 2015-10-06 12:29 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, Rodrigo Vivi On Tue, Oct 06, 2015 at 02:41:15PM +0300, Jani Nikula wrote: > Prefer inclusive ranges for revision checks rather than "below B0". Per > specs A2 is not used, so revid <= A1 matches revid < B0. The w/a db would say UNTIL_B0 etc., so might be easier to check against it if we keep to the same convention. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/i915_gem.c | 2 +- > drivers/gpu/drm/i915/i915_guc_submission.c | 2 +- > drivers/gpu/drm/i915/intel_ddi.c | 2 +- > drivers/gpu/drm/i915/intel_dp.c | 2 +- > drivers/gpu/drm/i915/intel_hdmi.c | 2 +- > drivers/gpu/drm/i915/intel_lrc.c | 8 ++++---- > drivers/gpu/drm/i915/intel_pm.c | 6 +++--- > drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++--- > 9 files changed, 16 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index a3b137715604..9833a2055930 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2509,6 +2509,7 @@ struct drm_i915_cmd_table { > #define SKL_REVID_F0 0x5 > > #define BXT_REVID_A0 0x0 > +#define BXT_REVID_A1 0x1 > #define BXT_REVID_B0 0x3 > #define BXT_REVID_C0 0x9 > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index f0cfbb9ee12c..fd2d880656b2 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -3757,7 +3757,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, > * cacheline, whereas normally such cachelines would get > * invalidated. > */ > - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) > + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) > return -ENODEV; > > level = I915_CACHE_LLC; > diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c > index 036b42bae827..863aa5c82466 100644 > --- a/drivers/gpu/drm/i915/i915_guc_submission.c > +++ b/drivers/gpu/drm/i915/i915_guc_submission.c > @@ -161,7 +161,7 @@ static int host2guc_sample_forcewake(struct intel_guc *guc, > data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE; > /* WaRsDisableCoarsePowerGating:skl,bxt */ > if (!intel_enable_rc6(dev_priv->dev) || > - (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || > + (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) || > (IS_SKL_GT3(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)) || > (IS_SKL_GT4(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0))) > data[1] = 0; > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index b25e99a432fb..b80e0f5ec5dc 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -3247,7 +3247,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port) > * On BXT A0/A1, sw needs to activate DDIA HPD logic and > * interrupts to check the external panel connection. > */ > - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0) > + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1) > && port == PORT_B) > dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port; > else > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 8d34ca7b287a..8baf6fe06313 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -6087,7 +6087,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, > break; > case PORT_B: > intel_encoder->hpd_pin = HPD_PORT_B; > - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) > + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1)) > intel_encoder->hpd_pin = HPD_PORT_A; > break; > case PORT_C: > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c > index 03d85909c6ab..32e9117ee8e3 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -2068,7 +2068,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, > * On BXT A0/A1, sw needs to activate DDIA HPD logic and > * interrupts to check the external panel connection. > */ > - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) > + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1)) > intel_encoder->hpd_pin = HPD_PORT_A; > else > intel_encoder->hpd_pin = HPD_PORT_B; > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 825fa7a8df86..acd4fa332a80 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1986,7 +1986,7 @@ static int logical_render_ring_init(struct drm_device *dev) > ring->init_hw = gen8_init_render_ring; > ring->init_context = gen8_init_rcs_context; > ring->cleanup = intel_fini_pipe_control; > - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { > + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { > ring->get_seqno = bxt_a_get_seqno; > ring->set_seqno = bxt_a_set_seqno; > } else { > @@ -2038,7 +2038,7 @@ static int logical_bsd_ring_init(struct drm_device *dev) > GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; > > ring->init_hw = gen8_init_common_ring; > - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { > + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { > ring->get_seqno = bxt_a_get_seqno; > ring->set_seqno = bxt_a_set_seqno; > } else { > @@ -2093,7 +2093,7 @@ static int logical_blt_ring_init(struct drm_device *dev) > GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; > > ring->init_hw = gen8_init_common_ring; > - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { > + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { > ring->get_seqno = bxt_a_get_seqno; > ring->set_seqno = bxt_a_set_seqno; > } else { > @@ -2123,7 +2123,7 @@ static int logical_vebox_ring_init(struct drm_device *dev) > GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; > > ring->init_hw = gen8_init_common_ring; > - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { > + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { > ring->get_seqno = bxt_a_get_seqno; > ring->set_seqno = bxt_a_set_seqno; > } else { > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 60d120c472ab..e25791e8748f 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4348,7 +4348,7 @@ static void gen6_set_rps(struct drm_device *dev, u8 val) > struct drm_i915_private *dev_priv = dev->dev_private; > > /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ > - if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) > + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) > return; > > WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); > @@ -4672,7 +4672,7 @@ static void gen9_enable_rps(struct drm_device *dev) > gen6_init_rps_frequencies(dev); > > /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ > - if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) { > + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) { > intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > return; > } > @@ -4758,7 +4758,7 @@ static void gen9_enable_rc6(struct drm_device *dev) > * 3b: Enable Coarse Power Gating only when RC6 is enabled. > * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. > */ > - if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || > + if ((IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) || > ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0))) > I915_WRITE(GEN9_PG_ENABLE, 0); > else > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index c82c74caa73c..3753e7518d49 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -916,14 +916,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) > > if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 || > INTEL_REVID(dev) == SKL_REVID_B0)) || > - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) { > + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) { > /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ > WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, > GEN9_DG_MIRROR_FIX_ENABLE); > } > > if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || > - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) { > + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) { > /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ > WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, > GEN9_RHWO_OPTIMIZATION_DISABLE); > @@ -952,7 +952,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) > > /* WaDisableMaskBasedCammingInRCC:skl,bxt */ > if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) || > - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) > + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) > WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, > PIXEL_MASK_CAMMING_DISABLE); > > -- > 2.1.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] drm/i915/bxt: add revision id for A1 stepping and use it 2015-10-06 12:29 ` Ville Syrjälä @ 2015-10-06 13:43 ` Jani Nikula 2015-10-06 17:50 ` Vivi, Rodrigo 2015-10-06 19:02 ` Ville Syrjälä 0 siblings, 2 replies; 10+ messages in thread From: Jani Nikula @ 2015-10-06 13:43 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx, Sarah Sharp, Rodrigo Vivi On Tue, 06 Oct 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > On Tue, Oct 06, 2015 at 02:41:15PM +0300, Jani Nikula wrote: >> Prefer inclusive ranges for revision checks rather than "below B0". Per >> specs A2 is not used, so revid <= A1 matches revid < B0. > > The w/a db would say UNTIL_B0 etc., so might be easier to check against > it if we keep to the same convention. So I wanted to double check what the convention is. I picked WaRsDisableCoarsePowerGating. KBL - SIWA_FOREVER BXT - SI_WA_BEFORE(BXT_REV_ID_B0) SKL - SIWA_UNTIL_SKL_E0 Description "Disable coarse power gating for GT4 until GT F0 stepping." *rolls eyes* So is that "until" there inclusive or non-inclusive? The db is contradicting itself... Cc: Sarah who has also looked at workarounds recently. Rodrigo, for one thing, I'll want workarounds for SKL and KBL in different conditions instead of conflated into SKL! But what about this non-inclusive end of range? It'll matter in patch 3/3. It's not so much a problem for ranges, but rather for specific revisions, where you'd have to include a revision not mentioned in the spec at all, e.g. for B0 only: IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_C0) instead of the current proposal: IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0) I'm not really fond of adding separate macros for checking specific vs. ranges. Thoughts? BR, Jani. > >> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> --- >> drivers/gpu/drm/i915/i915_drv.h | 1 + >> drivers/gpu/drm/i915/i915_gem.c | 2 +- >> drivers/gpu/drm/i915/i915_guc_submission.c | 2 +- >> drivers/gpu/drm/i915/intel_ddi.c | 2 +- >> drivers/gpu/drm/i915/intel_dp.c | 2 +- >> drivers/gpu/drm/i915/intel_hdmi.c | 2 +- >> drivers/gpu/drm/i915/intel_lrc.c | 8 ++++---- >> drivers/gpu/drm/i915/intel_pm.c | 6 +++--- >> drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++--- >> 9 files changed, 16 insertions(+), 15 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >> index a3b137715604..9833a2055930 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.h >> +++ b/drivers/gpu/drm/i915/i915_drv.h >> @@ -2509,6 +2509,7 @@ struct drm_i915_cmd_table { >> #define SKL_REVID_F0 0x5 >> >> #define BXT_REVID_A0 0x0 >> +#define BXT_REVID_A1 0x1 >> #define BXT_REVID_B0 0x3 >> #define BXT_REVID_C0 0x9 >> >> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c >> index f0cfbb9ee12c..fd2d880656b2 100644 >> --- a/drivers/gpu/drm/i915/i915_gem.c >> +++ b/drivers/gpu/drm/i915/i915_gem.c >> @@ -3757,7 +3757,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, >> * cacheline, whereas normally such cachelines would get >> * invalidated. >> */ >> - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) >> + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) >> return -ENODEV; >> >> level = I915_CACHE_LLC; >> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c >> index 036b42bae827..863aa5c82466 100644 >> --- a/drivers/gpu/drm/i915/i915_guc_submission.c >> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c >> @@ -161,7 +161,7 @@ static int host2guc_sample_forcewake(struct intel_guc *guc, >> data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE; >> /* WaRsDisableCoarsePowerGating:skl,bxt */ >> if (!intel_enable_rc6(dev_priv->dev) || >> - (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || >> + (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) || >> (IS_SKL_GT3(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)) || >> (IS_SKL_GT4(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0))) >> data[1] = 0; >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c >> index b25e99a432fb..b80e0f5ec5dc 100644 >> --- a/drivers/gpu/drm/i915/intel_ddi.c >> +++ b/drivers/gpu/drm/i915/intel_ddi.c >> @@ -3247,7 +3247,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port) >> * On BXT A0/A1, sw needs to activate DDIA HPD logic and >> * interrupts to check the external panel connection. >> */ >> - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0) >> + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1) >> && port == PORT_B) >> dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port; >> else >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >> index 8d34ca7b287a..8baf6fe06313 100644 >> --- a/drivers/gpu/drm/i915/intel_dp.c >> +++ b/drivers/gpu/drm/i915/intel_dp.c >> @@ -6087,7 +6087,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, >> break; >> case PORT_B: >> intel_encoder->hpd_pin = HPD_PORT_B; >> - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) >> + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1)) >> intel_encoder->hpd_pin = HPD_PORT_A; >> break; >> case PORT_C: >> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c >> index 03d85909c6ab..32e9117ee8e3 100644 >> --- a/drivers/gpu/drm/i915/intel_hdmi.c >> +++ b/drivers/gpu/drm/i915/intel_hdmi.c >> @@ -2068,7 +2068,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, >> * On BXT A0/A1, sw needs to activate DDIA HPD logic and >> * interrupts to check the external panel connection. >> */ >> - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) >> + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1)) >> intel_encoder->hpd_pin = HPD_PORT_A; >> else >> intel_encoder->hpd_pin = HPD_PORT_B; >> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c >> index 825fa7a8df86..acd4fa332a80 100644 >> --- a/drivers/gpu/drm/i915/intel_lrc.c >> +++ b/drivers/gpu/drm/i915/intel_lrc.c >> @@ -1986,7 +1986,7 @@ static int logical_render_ring_init(struct drm_device *dev) >> ring->init_hw = gen8_init_render_ring; >> ring->init_context = gen8_init_rcs_context; >> ring->cleanup = intel_fini_pipe_control; >> - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { >> + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { >> ring->get_seqno = bxt_a_get_seqno; >> ring->set_seqno = bxt_a_set_seqno; >> } else { >> @@ -2038,7 +2038,7 @@ static int logical_bsd_ring_init(struct drm_device *dev) >> GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; >> >> ring->init_hw = gen8_init_common_ring; >> - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { >> + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { >> ring->get_seqno = bxt_a_get_seqno; >> ring->set_seqno = bxt_a_set_seqno; >> } else { >> @@ -2093,7 +2093,7 @@ static int logical_blt_ring_init(struct drm_device *dev) >> GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; >> >> ring->init_hw = gen8_init_common_ring; >> - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { >> + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { >> ring->get_seqno = bxt_a_get_seqno; >> ring->set_seqno = bxt_a_set_seqno; >> } else { >> @@ -2123,7 +2123,7 @@ static int logical_vebox_ring_init(struct drm_device *dev) >> GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; >> >> ring->init_hw = gen8_init_common_ring; >> - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { >> + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { >> ring->get_seqno = bxt_a_get_seqno; >> ring->set_seqno = bxt_a_set_seqno; >> } else { >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c >> index 60d120c472ab..e25791e8748f 100644 >> --- a/drivers/gpu/drm/i915/intel_pm.c >> +++ b/drivers/gpu/drm/i915/intel_pm.c >> @@ -4348,7 +4348,7 @@ static void gen6_set_rps(struct drm_device *dev, u8 val) >> struct drm_i915_private *dev_priv = dev->dev_private; >> >> /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ >> - if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) >> + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) >> return; >> >> WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); >> @@ -4672,7 +4672,7 @@ static void gen9_enable_rps(struct drm_device *dev) >> gen6_init_rps_frequencies(dev); >> >> /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ >> - if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) { >> + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) { >> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); >> return; >> } >> @@ -4758,7 +4758,7 @@ static void gen9_enable_rc6(struct drm_device *dev) >> * 3b: Enable Coarse Power Gating only when RC6 is enabled. >> * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. >> */ >> - if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || >> + if ((IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) || >> ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0))) >> I915_WRITE(GEN9_PG_ENABLE, 0); >> else >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c >> index c82c74caa73c..3753e7518d49 100644 >> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c >> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c >> @@ -916,14 +916,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) >> >> if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 || >> INTEL_REVID(dev) == SKL_REVID_B0)) || >> - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) { >> + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) { >> /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ >> WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, >> GEN9_DG_MIRROR_FIX_ENABLE); >> } >> >> if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || >> - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) { >> + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) { >> /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ >> WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, >> GEN9_RHWO_OPTIMIZATION_DISABLE); >> @@ -952,7 +952,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) >> >> /* WaDisableMaskBasedCammingInRCC:skl,bxt */ >> if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) || >> - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) >> + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) >> WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, >> PIXEL_MASK_CAMMING_DISABLE); >> >> -- >> 2.1.4 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrjälä > Intel OTC -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] drm/i915/bxt: add revision id for A1 stepping and use it 2015-10-06 13:43 ` Jani Nikula @ 2015-10-06 17:50 ` Vivi, Rodrigo 2015-10-06 19:02 ` Ville Syrjälä 1 sibling, 0 replies; 10+ messages in thread From: Vivi, Rodrigo @ 2015-10-06 17:50 UTC (permalink / raw) To: ville.syrjala@linux.intel.com, Nikula, Jani Cc: intel-gfx@lists.freedesktop.org, Sharp, Sarah A On Tue, 2015-10-06 at 16:43 +0300, Jani Nikula wrote: > On Tue, 06 Oct 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> > wrote: > > On Tue, Oct 06, 2015 at 02:41:15PM +0300, Jani Nikula wrote: > > > Prefer inclusive ranges for revision checks rather than "below > > > B0". Per > > > specs A2 is not used, so revid <= A1 matches revid < B0. > > > > The w/a db would say UNTIL_B0 etc., so might be easier to check > > against > > it if we keep to the same convention. > > So I wanted to double check what the convention is. I picked > WaRsDisableCoarsePowerGating. > > KBL - SIWA_FOREVER > BXT - SI_WA_BEFORE(BXT_REV_ID_B0) > SKL - SIWA_UNTIL_SKL_E0 > > Description "Disable coarse power gating for GT4 until GT F0 > stepping." > > *rolls eyes* > > So is that "until" there inclusive or non-inclusive? The db is > contradicting itself... Cc: Sarah who has also looked at workarounds > recently. > > Rodrigo, for one thing, I'll want workarounds for SKL and KBL in > different conditions instead of conflated into SKL! I agree with Ville that <= REVID matches the spec in sense of "until" certain stepping and I like this. Also KBL W/A doesn't conflict with SKL W/as in they way they were derivated... > > But what about this non-inclusive end of range? It'll matter in patch > 3/3. It's not so much a problem for ranges, but rather for specific > revisions, where you'd have to include a revision not mentioned in > the > spec at all, e.g. for B0 only: > > IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_C0) > > instead of the current proposal: > > IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0) > > I'm not really fond of adding separate macros for checking specific > vs. ranges. > > Thoughts? > > BR, > Jani. > > > > > > > > > > > > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > > > --- > > > drivers/gpu/drm/i915/i915_drv.h | 1 + > > > drivers/gpu/drm/i915/i915_gem.c | 2 +- > > > drivers/gpu/drm/i915/i915_guc_submission.c | 2 +- > > > drivers/gpu/drm/i915/intel_ddi.c | 2 +- > > > drivers/gpu/drm/i915/intel_dp.c | 2 +- > > > drivers/gpu/drm/i915/intel_hdmi.c | 2 +- > > > drivers/gpu/drm/i915/intel_lrc.c | 8 ++++---- > > > drivers/gpu/drm/i915/intel_pm.c | 6 +++--- > > > drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++--- > > > 9 files changed, 16 insertions(+), 15 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h > > > b/drivers/gpu/drm/i915/i915_drv.h > > > index a3b137715604..9833a2055930 100644 > > > --- a/drivers/gpu/drm/i915/i915_drv.h > > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > > @@ -2509,6 +2509,7 @@ struct drm_i915_cmd_table { > > > #define SKL_REVID_F0 0x5 > > > > > > #define BXT_REVID_A0 0x0 > > > +#define BXT_REVID_A1 0x1 > > > #define BXT_REVID_B0 0x3 > > > #define BXT_REVID_C0 0x9 > > > > > > diff --git a/drivers/gpu/drm/i915/i915_gem.c > > > b/drivers/gpu/drm/i915/i915_gem.c > > > index f0cfbb9ee12c..fd2d880656b2 100644 > > > --- a/drivers/gpu/drm/i915/i915_gem.c > > > +++ b/drivers/gpu/drm/i915/i915_gem.c > > > @@ -3757,7 +3757,7 @@ int i915_gem_set_caching_ioctl(struct > > > drm_device *dev, void *data, > > > * cacheline, whereas normally such cachelines > > > would get > > > * invalidated. > > > */ > > > - if (IS_BROXTON(dev) && INTEL_REVID(dev) < > > > BXT_REVID_B0) > > > + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= > > > BXT_REVID_A1) > > > return -ENODEV; > > > > > > level = I915_CACHE_LLC; > > > diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c > > > b/drivers/gpu/drm/i915/i915_guc_submission.c > > > index 036b42bae827..863aa5c82466 100644 > > > --- a/drivers/gpu/drm/i915/i915_guc_submission.c > > > +++ b/drivers/gpu/drm/i915/i915_guc_submission.c > > > @@ -161,7 +161,7 @@ static int host2guc_sample_forcewake(struct > > > intel_guc *guc, > > > data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE; > > > /* WaRsDisableCoarsePowerGating:skl,bxt */ > > > if (!intel_enable_rc6(dev_priv->dev) || > > > - (IS_BROXTON(dev) && (INTEL_REVID(dev) < > > > BXT_REVID_B0)) || > > > + (IS_BROXTON(dev) && (INTEL_REVID(dev) <= > > > BXT_REVID_A1)) || > > > (IS_SKL_GT3(dev) && (INTEL_REVID(dev) <= > > > SKL_REVID_E0)) || > > > (IS_SKL_GT4(dev) && (INTEL_REVID(dev) <= > > > SKL_REVID_E0))) > > > data[1] = 0; > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > > > b/drivers/gpu/drm/i915/intel_ddi.c > > > index b25e99a432fb..b80e0f5ec5dc 100644 > > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > > @@ -3247,7 +3247,7 @@ void intel_ddi_init(struct drm_device *dev, > > > enum port port) > > > * On BXT A0/A1, sw needs to activate DDIA HPD > > > logic and > > > * interrupts to check the external panel > > > connection. > > > */ > > > - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < > > > BXT_REVID_B0) > > > + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= > > > BXT_REVID_A1) > > > && port == PORT_B) > > > dev_priv->hotplug.irq_port[PORT_A] = > > > intel_dig_port; > > > else > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c > > > b/drivers/gpu/drm/i915/intel_dp.c > > > index 8d34ca7b287a..8baf6fe06313 100644 > > > --- a/drivers/gpu/drm/i915/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > > @@ -6087,7 +6087,7 @@ intel_dp_init_connector(struct > > > intel_digital_port *intel_dig_port, > > > break; > > > case PORT_B: > > > intel_encoder->hpd_pin = HPD_PORT_B; > > > - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < > > > BXT_REVID_B0)) > > > + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= > > > BXT_REVID_A1)) > > > intel_encoder->hpd_pin = HPD_PORT_A; > > > break; > > > case PORT_C: > > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c > > > b/drivers/gpu/drm/i915/intel_hdmi.c > > > index 03d85909c6ab..32e9117ee8e3 100644 > > > --- a/drivers/gpu/drm/i915/intel_hdmi.c > > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > > > @@ -2068,7 +2068,7 @@ void intel_hdmi_init_connector(struct > > > intel_digital_port *intel_dig_port, > > > * On BXT A0/A1, sw needs to activate DDIA HPD > > > logic and > > > * interrupts to check the external panel > > > connection. > > > */ > > > - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < > > > BXT_REVID_B0)) > > > + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= > > > BXT_REVID_A1)) > > > intel_encoder->hpd_pin = HPD_PORT_A; > > > else > > > intel_encoder->hpd_pin = HPD_PORT_B; > > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c > > > b/drivers/gpu/drm/i915/intel_lrc.c > > > index 825fa7a8df86..acd4fa332a80 100644 > > > --- a/drivers/gpu/drm/i915/intel_lrc.c > > > +++ b/drivers/gpu/drm/i915/intel_lrc.c > > > @@ -1986,7 +1986,7 @@ static int logical_render_ring_init(struct > > > drm_device *dev) > > > ring->init_hw = gen8_init_render_ring; > > > ring->init_context = gen8_init_rcs_context; > > > ring->cleanup = intel_fini_pipe_control; > > > - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) > > > { > > > + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) > > > { > > > ring->get_seqno = bxt_a_get_seqno; > > > ring->set_seqno = bxt_a_set_seqno; > > > } else { > > > @@ -2038,7 +2038,7 @@ static int logical_bsd_ring_init(struct > > > drm_device *dev) > > > GT_CONTEXT_SWITCH_INTERRUPT << > > > GEN8_VCS1_IRQ_SHIFT; > > > > > > ring->init_hw = gen8_init_common_ring; > > > - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) > > > { > > > + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) > > > { > > > ring->get_seqno = bxt_a_get_seqno; > > > ring->set_seqno = bxt_a_set_seqno; > > > } else { > > > @@ -2093,7 +2093,7 @@ static int logical_blt_ring_init(struct > > > drm_device *dev) > > > GT_CONTEXT_SWITCH_INTERRUPT << > > > GEN8_BCS_IRQ_SHIFT; > > > > > > ring->init_hw = gen8_init_common_ring; > > > - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) > > > { > > > + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) > > > { > > > ring->get_seqno = bxt_a_get_seqno; > > > ring->set_seqno = bxt_a_set_seqno; > > > } else { > > > @@ -2123,7 +2123,7 @@ static int logical_vebox_ring_init(struct > > > drm_device *dev) > > > GT_CONTEXT_SWITCH_INTERRUPT << > > > GEN8_VECS_IRQ_SHIFT; > > > > > > ring->init_hw = gen8_init_common_ring; > > > - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) > > > { > > > + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) > > > { > > > ring->get_seqno = bxt_a_get_seqno; > > > ring->set_seqno = bxt_a_set_seqno; > > > } else { > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > > b/drivers/gpu/drm/i915/intel_pm.c > > > index 60d120c472ab..e25791e8748f 100644 > > > --- a/drivers/gpu/drm/i915/intel_pm.c > > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > > @@ -4348,7 +4348,7 @@ static void gen6_set_rps(struct drm_device > > > *dev, u8 val) > > > struct drm_i915_private *dev_priv = dev->dev_private; > > > > > > /* WaGsvDisableTurbo: Workaround to disable turbo on BXT > > > A* */ > > > - if (IS_BROXTON(dev) && (INTEL_REVID(dev) < > > > BXT_REVID_B0)) > > > + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= > > > BXT_REVID_A1)) > > > return; > > > > > > WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); > > > @@ -4672,7 +4672,7 @@ static void gen9_enable_rps(struct > > > drm_device *dev) > > > gen6_init_rps_frequencies(dev); > > > > > > /* WaGsvDisableTurbo: Workaround to disable turbo on BXT > > > A* */ > > > - if (IS_BROXTON(dev) && (INTEL_REVID(dev) < > > > BXT_REVID_B0)) { > > > + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= > > > BXT_REVID_A1)) { > > > intel_uncore_forcewake_put(dev_priv, > > > FORCEWAKE_ALL); > > > return; > > > } > > > @@ -4758,7 +4758,7 @@ static void gen9_enable_rc6(struct > > > drm_device *dev) > > > * 3b: Enable Coarse Power Gating only when RC6 is > > > enabled. > > > * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media > > > PG need to be disabled with RC6. > > > */ > > > - if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < > > > BXT_REVID_B0)) || > > > + if ((IS_BROXTON(dev) && (INTEL_REVID(dev) <= > > > BXT_REVID_A1)) || > > > ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && > > > (INTEL_REVID(dev) <= SKL_REVID_E0))) > > > I915_WRITE(GEN9_PG_ENABLE, 0); > > > else > > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > > > b/drivers/gpu/drm/i915/intel_ringbuffer.c > > > index c82c74caa73c..3753e7518d49 100644 > > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > > @@ -916,14 +916,14 @@ static int gen9_init_workarounds(struct > > > intel_engine_cs *ring) > > > > > > if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == > > > SKL_REVID_A0 || > > > INTEL_REVID(dev) == SKL_REVID_B0)) || > > > - (IS_BROXTON(dev) && INTEL_REVID(dev) < > > > BXT_REVID_B0)) { > > > + (IS_BROXTON(dev) && INTEL_REVID(dev) <= > > > BXT_REVID_A1)) { > > > /* > > > WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ > > > WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, > > > GEN9_DG_MIRROR_FIX_ENABLE); > > > } > > > > > > if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= > > > SKL_REVID_B0) || > > > - (IS_BROXTON(dev) && INTEL_REVID(dev) < > > > BXT_REVID_B0)) { > > > + (IS_BROXTON(dev) && INTEL_REVID(dev) <= > > > BXT_REVID_A1)) { > > > /* > > > WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ > > > WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, > > > > > > GEN9_RHWO_OPTIMIZATION_DISABLE); > > > @@ -952,7 +952,7 @@ static int gen9_init_workarounds(struct > > > intel_engine_cs *ring) > > > > > > /* WaDisableMaskBasedCammingInRCC:skl,bxt */ > > > if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == > > > SKL_REVID_C0) || > > > - (IS_BROXTON(dev) && INTEL_REVID(dev) < > > > BXT_REVID_B0)) > > > + (IS_BROXTON(dev) && INTEL_REVID(dev) <= > > > BXT_REVID_A1)) > > > WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, > > > PIXEL_MASK_CAMMING_DISABLE); > > > > > > -- > > > 2.1.4 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > > Ville Syrjälä > > Intel OTC > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] drm/i915/bxt: add revision id for A1 stepping and use it 2015-10-06 13:43 ` Jani Nikula 2015-10-06 17:50 ` Vivi, Rodrigo @ 2015-10-06 19:02 ` Ville Syrjälä 2015-10-07 8:32 ` Jani Nikula 1 sibling, 1 reply; 10+ messages in thread From: Ville Syrjälä @ 2015-10-06 19:02 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, Sarah Sharp, Rodrigo Vivi On Tue, Oct 06, 2015 at 04:43:11PM +0300, Jani Nikula wrote: > On Tue, 06 Oct 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > > On Tue, Oct 06, 2015 at 02:41:15PM +0300, Jani Nikula wrote: > >> Prefer inclusive ranges for revision checks rather than "below B0". Per > >> specs A2 is not used, so revid <= A1 matches revid < B0. > > > > The w/a db would say UNTIL_B0 etc., so might be easier to check against > > it if we keep to the same convention. > > So I wanted to double check what the convention is. I picked > WaRsDisableCoarsePowerGating. > > KBL - SIWA_FOREVER > BXT - SI_WA_BEFORE(BXT_REV_ID_B0) > SKL - SIWA_UNTIL_SKL_E0 > > Description "Disable coarse power gating for GT4 until GT F0 stepping." > > *rolls eyes* > > So is that "until" there inclusive or non-inclusive? The db is > contradicting itself... Hmm. My recollection was that it's exclusive, but now that I look at your findings and some other workarounds, it does look a bit more like inclusive. I would think the exclusive thing would be easier to maintain since the hsd specifies the stepping in which stuff got fixed, and the exclusive convention would then have the same stepping listed. Eg. if the hsd says fixed in E0, but the w/a db says UNTIL_D0, then one is left wondering about D1+ But perhaps such steppings didn't even exist. Well, in reality it's all over the place. Eg. looking at the BDW UNTIL_D0 stuff, some are fixed in E0, some are fixed in D0, and at least one was fixed in B0 according to hsd. So I'm starting to think that the meaning of the tag depends entirely on the person who pushed the change. > Cc: Sarah who has also looked at workarounds > recently. > > Rodrigo, for one thing, I'll want workarounds for SKL and KBL in > different conditions instead of conflated into SKL! > > But what about this non-inclusive end of range? It'll matter in patch > 3/3. It's not so much a problem for ranges, but rather for specific > revisions, where you'd have to include a revision not mentioned in the > spec at all, e.g. for B0 only: > > IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_C0) > > instead of the current proposal: > > IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0) > > I'm not really fond of adding separate macros for checking specific > vs. ranges. > > Thoughts? > > BR, > Jani. > > > > > > > > >> > >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> > >> --- > >> drivers/gpu/drm/i915/i915_drv.h | 1 + > >> drivers/gpu/drm/i915/i915_gem.c | 2 +- > >> drivers/gpu/drm/i915/i915_guc_submission.c | 2 +- > >> drivers/gpu/drm/i915/intel_ddi.c | 2 +- > >> drivers/gpu/drm/i915/intel_dp.c | 2 +- > >> drivers/gpu/drm/i915/intel_hdmi.c | 2 +- > >> drivers/gpu/drm/i915/intel_lrc.c | 8 ++++---- > >> drivers/gpu/drm/i915/intel_pm.c | 6 +++--- > >> drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++--- > >> 9 files changed, 16 insertions(+), 15 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > >> index a3b137715604..9833a2055930 100644 > >> --- a/drivers/gpu/drm/i915/i915_drv.h > >> +++ b/drivers/gpu/drm/i915/i915_drv.h > >> @@ -2509,6 +2509,7 @@ struct drm_i915_cmd_table { > >> #define SKL_REVID_F0 0x5 > >> > >> #define BXT_REVID_A0 0x0 > >> +#define BXT_REVID_A1 0x1 > >> #define BXT_REVID_B0 0x3 > >> #define BXT_REVID_C0 0x9 > >> > >> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > >> index f0cfbb9ee12c..fd2d880656b2 100644 > >> --- a/drivers/gpu/drm/i915/i915_gem.c > >> +++ b/drivers/gpu/drm/i915/i915_gem.c > >> @@ -3757,7 +3757,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, > >> * cacheline, whereas normally such cachelines would get > >> * invalidated. > >> */ > >> - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) > >> + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) > >> return -ENODEV; > >> > >> level = I915_CACHE_LLC; > >> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c > >> index 036b42bae827..863aa5c82466 100644 > >> --- a/drivers/gpu/drm/i915/i915_guc_submission.c > >> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c > >> @@ -161,7 +161,7 @@ static int host2guc_sample_forcewake(struct intel_guc *guc, > >> data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE; > >> /* WaRsDisableCoarsePowerGating:skl,bxt */ > >> if (!intel_enable_rc6(dev_priv->dev) || > >> - (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || > >> + (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) || > >> (IS_SKL_GT3(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)) || > >> (IS_SKL_GT4(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0))) > >> data[1] = 0; > >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > >> index b25e99a432fb..b80e0f5ec5dc 100644 > >> --- a/drivers/gpu/drm/i915/intel_ddi.c > >> +++ b/drivers/gpu/drm/i915/intel_ddi.c > >> @@ -3247,7 +3247,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port) > >> * On BXT A0/A1, sw needs to activate DDIA HPD logic and > >> * interrupts to check the external panel connection. > >> */ > >> - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0) > >> + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1) > >> && port == PORT_B) > >> dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port; > >> else > >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > >> index 8d34ca7b287a..8baf6fe06313 100644 > >> --- a/drivers/gpu/drm/i915/intel_dp.c > >> +++ b/drivers/gpu/drm/i915/intel_dp.c > >> @@ -6087,7 +6087,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, > >> break; > >> case PORT_B: > >> intel_encoder->hpd_pin = HPD_PORT_B; > >> - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) > >> + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1)) > >> intel_encoder->hpd_pin = HPD_PORT_A; > >> break; > >> case PORT_C: > >> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c > >> index 03d85909c6ab..32e9117ee8e3 100644 > >> --- a/drivers/gpu/drm/i915/intel_hdmi.c > >> +++ b/drivers/gpu/drm/i915/intel_hdmi.c > >> @@ -2068,7 +2068,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, > >> * On BXT A0/A1, sw needs to activate DDIA HPD logic and > >> * interrupts to check the external panel connection. > >> */ > >> - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) > >> + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1)) > >> intel_encoder->hpd_pin = HPD_PORT_A; > >> else > >> intel_encoder->hpd_pin = HPD_PORT_B; > >> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > >> index 825fa7a8df86..acd4fa332a80 100644 > >> --- a/drivers/gpu/drm/i915/intel_lrc.c > >> +++ b/drivers/gpu/drm/i915/intel_lrc.c > >> @@ -1986,7 +1986,7 @@ static int logical_render_ring_init(struct drm_device *dev) > >> ring->init_hw = gen8_init_render_ring; > >> ring->init_context = gen8_init_rcs_context; > >> ring->cleanup = intel_fini_pipe_control; > >> - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { > >> + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { > >> ring->get_seqno = bxt_a_get_seqno; > >> ring->set_seqno = bxt_a_set_seqno; > >> } else { > >> @@ -2038,7 +2038,7 @@ static int logical_bsd_ring_init(struct drm_device *dev) > >> GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; > >> > >> ring->init_hw = gen8_init_common_ring; > >> - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { > >> + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { > >> ring->get_seqno = bxt_a_get_seqno; > >> ring->set_seqno = bxt_a_set_seqno; > >> } else { > >> @@ -2093,7 +2093,7 @@ static int logical_blt_ring_init(struct drm_device *dev) > >> GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; > >> > >> ring->init_hw = gen8_init_common_ring; > >> - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { > >> + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { > >> ring->get_seqno = bxt_a_get_seqno; > >> ring->set_seqno = bxt_a_set_seqno; > >> } else { > >> @@ -2123,7 +2123,7 @@ static int logical_vebox_ring_init(struct drm_device *dev) > >> GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; > >> > >> ring->init_hw = gen8_init_common_ring; > >> - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { > >> + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { > >> ring->get_seqno = bxt_a_get_seqno; > >> ring->set_seqno = bxt_a_set_seqno; > >> } else { > >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > >> index 60d120c472ab..e25791e8748f 100644 > >> --- a/drivers/gpu/drm/i915/intel_pm.c > >> +++ b/drivers/gpu/drm/i915/intel_pm.c > >> @@ -4348,7 +4348,7 @@ static void gen6_set_rps(struct drm_device *dev, u8 val) > >> struct drm_i915_private *dev_priv = dev->dev_private; > >> > >> /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ > >> - if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) > >> + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) > >> return; > >> > >> WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); > >> @@ -4672,7 +4672,7 @@ static void gen9_enable_rps(struct drm_device *dev) > >> gen6_init_rps_frequencies(dev); > >> > >> /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ > >> - if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) { > >> + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) { > >> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > >> return; > >> } > >> @@ -4758,7 +4758,7 @@ static void gen9_enable_rc6(struct drm_device *dev) > >> * 3b: Enable Coarse Power Gating only when RC6 is enabled. > >> * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. > >> */ > >> - if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || > >> + if ((IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) || > >> ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0))) > >> I915_WRITE(GEN9_PG_ENABLE, 0); > >> else > >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > >> index c82c74caa73c..3753e7518d49 100644 > >> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > >> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > >> @@ -916,14 +916,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) > >> > >> if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 || > >> INTEL_REVID(dev) == SKL_REVID_B0)) || > >> - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) { > >> + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) { > >> /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ > >> WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, > >> GEN9_DG_MIRROR_FIX_ENABLE); > >> } > >> > >> if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || > >> - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) { > >> + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) { > >> /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ > >> WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, > >> GEN9_RHWO_OPTIMIZATION_DISABLE); > >> @@ -952,7 +952,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) > >> > >> /* WaDisableMaskBasedCammingInRCC:skl,bxt */ > >> if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) || > >> - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) > >> + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) > >> WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, > >> PIXEL_MASK_CAMMING_DISABLE); > >> > >> -- > >> 2.1.4 > >> > >> _______________________________________________ > >> Intel-gfx mailing list > >> Intel-gfx@lists.freedesktop.org > >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > > Ville Syrjälä > > Intel OTC > > -- > Jani Nikula, Intel Open Source Technology Center -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] drm/i915/bxt: add revision id for A1 stepping and use it 2015-10-06 19:02 ` Ville Syrjälä @ 2015-10-07 8:32 ` Jani Nikula 2015-10-13 13:16 ` Jani Nikula 0 siblings, 1 reply; 10+ messages in thread From: Jani Nikula @ 2015-10-07 8:32 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx, Sarah Sharp, Rodrigo Vivi On Tue, 06 Oct 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > On Tue, Oct 06, 2015 at 04:43:11PM +0300, Jani Nikula wrote: >> On Tue, 06 Oct 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: >> > On Tue, Oct 06, 2015 at 02:41:15PM +0300, Jani Nikula wrote: >> >> Prefer inclusive ranges for revision checks rather than "below B0". Per >> >> specs A2 is not used, so revid <= A1 matches revid < B0. >> > >> > The w/a db would say UNTIL_B0 etc., so might be easier to check against >> > it if we keep to the same convention. >> >> So I wanted to double check what the convention is. I picked >> WaRsDisableCoarsePowerGating. >> >> KBL - SIWA_FOREVER >> BXT - SI_WA_BEFORE(BXT_REV_ID_B0) >> SKL - SIWA_UNTIL_SKL_E0 >> >> Description "Disable coarse power gating for GT4 until GT F0 stepping." >> >> *rolls eyes* >> >> So is that "until" there inclusive or non-inclusive? The db is >> contradicting itself... > > Hmm. My recollection was that it's exclusive, but now that I look at > your findings and some other workarounds, it does look a bit more like > inclusive. > > I would think the exclusive thing would be easier to maintain since > the hsd specifies the stepping in which stuff got fixed, and the > exclusive convention would then have the same stepping listed. Eg. if > the hsd says fixed in E0, but the w/a db says UNTIL_D0, then one is > left wondering about D1+ But perhaps such steppings didn't even exist. > > Well, in reality it's all over the place. Eg. looking at the BDW UNTIL_D0 > stuff, some are fixed in E0, some are fixed in D0, and at least one was > fixed in B0 according to hsd. So I'm starting to think that the meaning > of the tag depends entirely on the person who pushed the change. With that, I stand by the patches I submitted as they are. BR, Jani. > >> Cc: Sarah who has also looked at workarounds >> recently. >> >> Rodrigo, for one thing, I'll want workarounds for SKL and KBL in >> different conditions instead of conflated into SKL! >> >> But what about this non-inclusive end of range? It'll matter in patch >> 3/3. It's not so much a problem for ranges, but rather for specific >> revisions, where you'd have to include a revision not mentioned in the >> spec at all, e.g. for B0 only: >> >> IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_C0) >> >> instead of the current proposal: >> >> IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0) >> >> I'm not really fond of adding separate macros for checking specific >> vs. ranges. >> >> Thoughts? >> >> BR, >> Jani. >> >> >> >> >> >> > >> >> >> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> >> --- >> >> drivers/gpu/drm/i915/i915_drv.h | 1 + >> >> drivers/gpu/drm/i915/i915_gem.c | 2 +- >> >> drivers/gpu/drm/i915/i915_guc_submission.c | 2 +- >> >> drivers/gpu/drm/i915/intel_ddi.c | 2 +- >> >> drivers/gpu/drm/i915/intel_dp.c | 2 +- >> >> drivers/gpu/drm/i915/intel_hdmi.c | 2 +- >> >> drivers/gpu/drm/i915/intel_lrc.c | 8 ++++---- >> >> drivers/gpu/drm/i915/intel_pm.c | 6 +++--- >> >> drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++--- >> >> 9 files changed, 16 insertions(+), 15 deletions(-) >> >> >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >> >> index a3b137715604..9833a2055930 100644 >> >> --- a/drivers/gpu/drm/i915/i915_drv.h >> >> +++ b/drivers/gpu/drm/i915/i915_drv.h >> >> @@ -2509,6 +2509,7 @@ struct drm_i915_cmd_table { >> >> #define SKL_REVID_F0 0x5 >> >> >> >> #define BXT_REVID_A0 0x0 >> >> +#define BXT_REVID_A1 0x1 >> >> #define BXT_REVID_B0 0x3 >> >> #define BXT_REVID_C0 0x9 >> >> >> >> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c >> >> index f0cfbb9ee12c..fd2d880656b2 100644 >> >> --- a/drivers/gpu/drm/i915/i915_gem.c >> >> +++ b/drivers/gpu/drm/i915/i915_gem.c >> >> @@ -3757,7 +3757,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, >> >> * cacheline, whereas normally such cachelines would get >> >> * invalidated. >> >> */ >> >> - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) >> >> + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) >> >> return -ENODEV; >> >> >> >> level = I915_CACHE_LLC; >> >> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c >> >> index 036b42bae827..863aa5c82466 100644 >> >> --- a/drivers/gpu/drm/i915/i915_guc_submission.c >> >> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c >> >> @@ -161,7 +161,7 @@ static int host2guc_sample_forcewake(struct intel_guc *guc, >> >> data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE; >> >> /* WaRsDisableCoarsePowerGating:skl,bxt */ >> >> if (!intel_enable_rc6(dev_priv->dev) || >> >> - (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || >> >> + (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) || >> >> (IS_SKL_GT3(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)) || >> >> (IS_SKL_GT4(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0))) >> >> data[1] = 0; >> >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c >> >> index b25e99a432fb..b80e0f5ec5dc 100644 >> >> --- a/drivers/gpu/drm/i915/intel_ddi.c >> >> +++ b/drivers/gpu/drm/i915/intel_ddi.c >> >> @@ -3247,7 +3247,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port) >> >> * On BXT A0/A1, sw needs to activate DDIA HPD logic and >> >> * interrupts to check the external panel connection. >> >> */ >> >> - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0) >> >> + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1) >> >> && port == PORT_B) >> >> dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port; >> >> else >> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >> >> index 8d34ca7b287a..8baf6fe06313 100644 >> >> --- a/drivers/gpu/drm/i915/intel_dp.c >> >> +++ b/drivers/gpu/drm/i915/intel_dp.c >> >> @@ -6087,7 +6087,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, >> >> break; >> >> case PORT_B: >> >> intel_encoder->hpd_pin = HPD_PORT_B; >> >> - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) >> >> + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1)) >> >> intel_encoder->hpd_pin = HPD_PORT_A; >> >> break; >> >> case PORT_C: >> >> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c >> >> index 03d85909c6ab..32e9117ee8e3 100644 >> >> --- a/drivers/gpu/drm/i915/intel_hdmi.c >> >> +++ b/drivers/gpu/drm/i915/intel_hdmi.c >> >> @@ -2068,7 +2068,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, >> >> * On BXT A0/A1, sw needs to activate DDIA HPD logic and >> >> * interrupts to check the external panel connection. >> >> */ >> >> - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) >> >> + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1)) >> >> intel_encoder->hpd_pin = HPD_PORT_A; >> >> else >> >> intel_encoder->hpd_pin = HPD_PORT_B; >> >> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c >> >> index 825fa7a8df86..acd4fa332a80 100644 >> >> --- a/drivers/gpu/drm/i915/intel_lrc.c >> >> +++ b/drivers/gpu/drm/i915/intel_lrc.c >> >> @@ -1986,7 +1986,7 @@ static int logical_render_ring_init(struct drm_device *dev) >> >> ring->init_hw = gen8_init_render_ring; >> >> ring->init_context = gen8_init_rcs_context; >> >> ring->cleanup = intel_fini_pipe_control; >> >> - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { >> >> + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { >> >> ring->get_seqno = bxt_a_get_seqno; >> >> ring->set_seqno = bxt_a_set_seqno; >> >> } else { >> >> @@ -2038,7 +2038,7 @@ static int logical_bsd_ring_init(struct drm_device *dev) >> >> GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; >> >> >> >> ring->init_hw = gen8_init_common_ring; >> >> - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { >> >> + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { >> >> ring->get_seqno = bxt_a_get_seqno; >> >> ring->set_seqno = bxt_a_set_seqno; >> >> } else { >> >> @@ -2093,7 +2093,7 @@ static int logical_blt_ring_init(struct drm_device *dev) >> >> GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; >> >> >> >> ring->init_hw = gen8_init_common_ring; >> >> - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { >> >> + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { >> >> ring->get_seqno = bxt_a_get_seqno; >> >> ring->set_seqno = bxt_a_set_seqno; >> >> } else { >> >> @@ -2123,7 +2123,7 @@ static int logical_vebox_ring_init(struct drm_device *dev) >> >> GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; >> >> >> >> ring->init_hw = gen8_init_common_ring; >> >> - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { >> >> + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { >> >> ring->get_seqno = bxt_a_get_seqno; >> >> ring->set_seqno = bxt_a_set_seqno; >> >> } else { >> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c >> >> index 60d120c472ab..e25791e8748f 100644 >> >> --- a/drivers/gpu/drm/i915/intel_pm.c >> >> +++ b/drivers/gpu/drm/i915/intel_pm.c >> >> @@ -4348,7 +4348,7 @@ static void gen6_set_rps(struct drm_device *dev, u8 val) >> >> struct drm_i915_private *dev_priv = dev->dev_private; >> >> >> >> /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ >> >> - if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) >> >> + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) >> >> return; >> >> >> >> WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); >> >> @@ -4672,7 +4672,7 @@ static void gen9_enable_rps(struct drm_device *dev) >> >> gen6_init_rps_frequencies(dev); >> >> >> >> /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ >> >> - if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) { >> >> + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) { >> >> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); >> >> return; >> >> } >> >> @@ -4758,7 +4758,7 @@ static void gen9_enable_rc6(struct drm_device *dev) >> >> * 3b: Enable Coarse Power Gating only when RC6 is enabled. >> >> * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. >> >> */ >> >> - if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || >> >> + if ((IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) || >> >> ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0))) >> >> I915_WRITE(GEN9_PG_ENABLE, 0); >> >> else >> >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c >> >> index c82c74caa73c..3753e7518d49 100644 >> >> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c >> >> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c >> >> @@ -916,14 +916,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) >> >> >> >> if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 || >> >> INTEL_REVID(dev) == SKL_REVID_B0)) || >> >> - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) { >> >> + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) { >> >> /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ >> >> WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, >> >> GEN9_DG_MIRROR_FIX_ENABLE); >> >> } >> >> >> >> if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || >> >> - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) { >> >> + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) { >> >> /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ >> >> WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, >> >> GEN9_RHWO_OPTIMIZATION_DISABLE); >> >> @@ -952,7 +952,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) >> >> >> >> /* WaDisableMaskBasedCammingInRCC:skl,bxt */ >> >> if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) || >> >> - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) >> >> + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) >> >> WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, >> >> PIXEL_MASK_CAMMING_DISABLE); >> >> >> >> -- >> >> 2.1.4 >> >> >> >> _______________________________________________ >> >> Intel-gfx mailing list >> >> Intel-gfx@lists.freedesktop.org >> >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx >> > >> > -- >> > Ville Syrjälä >> > Intel OTC >> >> -- >> Jani Nikula, Intel Open Source Technology Center > > -- > Ville Syrjälä > Intel OTC -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] drm/i915/bxt: add revision id for A1 stepping and use it 2015-10-07 8:32 ` Jani Nikula @ 2015-10-13 13:16 ` Jani Nikula 2015-10-13 13:17 ` Ville Syrjälä 0 siblings, 1 reply; 10+ messages in thread From: Jani Nikula @ 2015-10-13 13:16 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx, Sarah Sharp, Rodrigo Vivi On Wed, 07 Oct 2015, Jani Nikula <jani.nikula@intel.com> wrote: > On Tue, 06 Oct 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: >> On Tue, Oct 06, 2015 at 04:43:11PM +0300, Jani Nikula wrote: >>> On Tue, 06 Oct 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: >>> > On Tue, Oct 06, 2015 at 02:41:15PM +0300, Jani Nikula wrote: >>> >> Prefer inclusive ranges for revision checks rather than "below B0". Per >>> >> specs A2 is not used, so revid <= A1 matches revid < B0. >>> > >>> > The w/a db would say UNTIL_B0 etc., so might be easier to check against >>> > it if we keep to the same convention. >>> >>> So I wanted to double check what the convention is. I picked >>> WaRsDisableCoarsePowerGating. >>> >>> KBL - SIWA_FOREVER >>> BXT - SI_WA_BEFORE(BXT_REV_ID_B0) >>> SKL - SIWA_UNTIL_SKL_E0 >>> >>> Description "Disable coarse power gating for GT4 until GT F0 stepping." >>> >>> *rolls eyes* >>> >>> So is that "until" there inclusive or non-inclusive? The db is >>> contradicting itself... >> >> Hmm. My recollection was that it's exclusive, but now that I look at >> your findings and some other workarounds, it does look a bit more like >> inclusive. >> >> I would think the exclusive thing would be easier to maintain since >> the hsd specifies the stepping in which stuff got fixed, and the >> exclusive convention would then have the same stepping listed. Eg. if >> the hsd says fixed in E0, but the w/a db says UNTIL_D0, then one is >> left wondering about D1+ But perhaps such steppings didn't even exist. >> >> Well, in reality it's all over the place. Eg. looking at the BDW UNTIL_D0 >> stuff, some are fixed in E0, some are fixed in D0, and at least one was >> fixed in B0 according to hsd. So I'm starting to think that the meaning >> of the tag depends entirely on the person who pushed the change. > > With that, I stand by the patches I submitted as they are. Ville, opinions, r-b, nak, ack, crap, what? ;) BR, Jani. -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] drm/i915/bxt: add revision id for A1 stepping and use it 2015-10-13 13:16 ` Jani Nikula @ 2015-10-13 13:17 ` Ville Syrjälä 0 siblings, 0 replies; 10+ messages in thread From: Ville Syrjälä @ 2015-10-13 13:17 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, Sarah Sharp, Rodrigo Vivi On Tue, Oct 13, 2015 at 04:16:47PM +0300, Jani Nikula wrote: > On Wed, 07 Oct 2015, Jani Nikula <jani.nikula@intel.com> wrote: > > On Tue, 06 Oct 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > >> On Tue, Oct 06, 2015 at 04:43:11PM +0300, Jani Nikula wrote: > >>> On Tue, 06 Oct 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > >>> > On Tue, Oct 06, 2015 at 02:41:15PM +0300, Jani Nikula wrote: > >>> >> Prefer inclusive ranges for revision checks rather than "below B0". Per > >>> >> specs A2 is not used, so revid <= A1 matches revid < B0. > >>> > > >>> > The w/a db would say UNTIL_B0 etc., so might be easier to check against > >>> > it if we keep to the same convention. > >>> > >>> So I wanted to double check what the convention is. I picked > >>> WaRsDisableCoarsePowerGating. > >>> > >>> KBL - SIWA_FOREVER > >>> BXT - SI_WA_BEFORE(BXT_REV_ID_B0) > >>> SKL - SIWA_UNTIL_SKL_E0 > >>> > >>> Description "Disable coarse power gating for GT4 until GT F0 stepping." > >>> > >>> *rolls eyes* > >>> > >>> So is that "until" there inclusive or non-inclusive? The db is > >>> contradicting itself... > >> > >> Hmm. My recollection was that it's exclusive, but now that I look at > >> your findings and some other workarounds, it does look a bit more like > >> inclusive. > >> > >> I would think the exclusive thing would be easier to maintain since > >> the hsd specifies the stepping in which stuff got fixed, and the > >> exclusive convention would then have the same stepping listed. Eg. if > >> the hsd says fixed in E0, but the w/a db says UNTIL_D0, then one is > >> left wondering about D1+ But perhaps such steppings didn't even exist. > >> > >> Well, in reality it's all over the place. Eg. looking at the BDW UNTIL_D0 > >> stuff, some are fixed in E0, some are fixed in D0, and at least one was > >> fixed in B0 according to hsd. So I'm starting to think that the meaning > >> of the tag depends entirely on the person who pushed the change. > > > > With that, I stand by the patches I submitted as they are. > > Ville, opinions, r-b, nak, ack, crap, what? ;) Yeah, I guess it's all good. Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/3] drm/i915: add helpers for platform specific revision id range checks 2015-10-06 11:41 [PATCH 1/3] drm/i915: remove parens around revision ids Jani Nikula 2015-10-06 11:41 ` [PATCH 2/3] drm/i915/bxt: add revision id for A1 stepping and use it Jani Nikula @ 2015-10-06 11:41 ` Jani Nikula 1 sibling, 0 replies; 10+ messages in thread From: Jani Nikula @ 2015-10-06 11:41 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, Rodrigo Vivi Revision checks are almost always accompanied by a platform check. (The exceptions are platform specific code.) Add helpers to check for a platform and a revision range: IS_SKL_REVID() and IS_BXT_REVID(). In most places this simplifies and clarifies the code. It will be obvious that revid macros are used for the correct platform. This should make it easier to find all the revision checks for workarounds for each platform, and make it easier to remove them once we drop support for early hardware revisions. This should also make it easier to differentiate between Skylake and Kabylake revision checks when Kabylake support is added. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 13 +++++++++ drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/i915_guc_submission.c | 6 ++-- drivers/gpu/drm/i915/intel_ddi.c | 3 +- drivers/gpu/drm/i915/intel_dp.c | 4 +-- drivers/gpu/drm/i915/intel_guc_loader.c | 4 +-- drivers/gpu/drm/i915/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/intel_lrc.c | 26 ++++++++--------- drivers/gpu/drm/i915/intel_pm.c | 29 +++++++++---------- drivers/gpu/drm/i915/intel_ringbuffer.c | 46 ++++++++++++------------------ 10 files changed, 69 insertions(+), 66 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9833a2055930..578563ca0d5c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2440,6 +2440,15 @@ struct drm_i915_cmd_table { #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision) +#define REVID_FOREVER 0xff +/* + * Return true if revision is in range [since,until] inclusive. + * + * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. + */ +#define IS_REVID(p, since, until) \ + (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) + #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) @@ -2508,11 +2517,15 @@ struct drm_i915_cmd_table { #define SKL_REVID_E0 0x4 #define SKL_REVID_F0 0x5 +#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) + #define BXT_REVID_A0 0x0 #define BXT_REVID_A1 0x1 #define BXT_REVID_B0 0x3 #define BXT_REVID_C0 0x9 +#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until)) + /* * The genX designation typically refers to the render engine, so render * capability related checks should use IS_GEN, while display and other checks diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index fd2d880656b2..8af33a48204f 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3757,7 +3757,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, * cacheline, whereas normally such cachelines would get * invalidated. */ - if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) + if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) return -ENODEV; level = I915_CACHE_LLC; diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index 863aa5c82466..4bf9aa54c75e 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -161,9 +161,9 @@ static int host2guc_sample_forcewake(struct intel_guc *guc, data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE; /* WaRsDisableCoarsePowerGating:skl,bxt */ if (!intel_enable_rc6(dev_priv->dev) || - (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) || - (IS_SKL_GT3(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)) || - (IS_SKL_GT4(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0))) + IS_BXT_REVID(dev, 0, BXT_REVID_A1) || + (IS_SKL_GT3(dev) && IS_SKL_REVID(dev, 0, SKL_REVID_E0)) || + (IS_SKL_GT4(dev) && IS_SKL_REVID(dev, 0, SKL_REVID_E0))) data[1] = 0; else /* bit 0 and 1 are for Render and Media domain separately */ diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index b80e0f5ec5dc..7bcca708393d 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -3247,8 +3247,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port) * On BXT A0/A1, sw needs to activate DDIA HPD logic and * interrupts to check the external panel connection. */ - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1) - && port == PORT_B) + if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B) dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port; else dev_priv->hotplug.irq_port[port] = intel_dig_port; diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 8baf6fe06313..407fd1b12902 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1192,7 +1192,7 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) static bool intel_dp_source_supports_hbr2(struct drm_device *dev) { /* WaDisableHBR2:skl */ - if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) + if (IS_SKL_REVID(dev, 0, SKL_REVID_B0)) return false; if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || @@ -6087,7 +6087,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, break; case PORT_B: intel_encoder->hpd_pin = HPD_PORT_B; - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1)) + if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) intel_encoder->hpd_pin = HPD_PORT_A; break; case PORT_C: diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index a17b6a56be83..ac31696012df 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -322,8 +322,8 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv) I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE); /* WaDisableMinuteIaClockGating:skl,bxt */ - if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || - (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) { + if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || + IS_BXT_REVID(dev, 0, BXT_REVID_A0)) { I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) & ~GUC_ENABLE_MIA_CLOCK_GATING)); } diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 32e9117ee8e3..f619de5f50a7 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -2068,7 +2068,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, * On BXT A0/A1, sw needs to activate DDIA HPD logic and * interrupts to check the external panel connection. */ - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1)) + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) intel_encoder->hpd_pin = HPD_PORT_A; else intel_encoder->hpd_pin = HPD_PORT_B; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index acd4fa332a80..a0d45b806af0 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -284,8 +284,8 @@ static bool disable_lite_restore_wa(struct intel_engine_cs *ring) { struct drm_device *dev = ring->dev; - return ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || - (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) && + return (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || + IS_BXT_REVID(dev, 0, BXT_REVID_A0)) && (ring->id == VCS || ring->id == VCS2); } @@ -1164,7 +1164,7 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring, * this batch updates GEN8_L3SQCREG4 with default value we need to * set this bit here to retain the WA during flush. */ - if (IS_SKYLAKE(ring->dev) && INTEL_REVID(ring->dev) <= SKL_REVID_E0) + if (IS_SKL_REVID(ring->dev, 0, SKL_REVID_E0)) l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS; wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 | @@ -1329,8 +1329,8 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring, uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); /* WaDisableCtxRestoreArbitration:skl,bxt */ - if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) || - (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) + if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || + IS_BXT_REVID(dev, 0, BXT_REVID_A0)) wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ @@ -1355,8 +1355,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring, uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ - if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) || - (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) { + if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || + IS_BXT_REVID(dev, 0, BXT_REVID_A0)) { wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0); wa_ctx_emit(batch, index, @@ -1365,8 +1365,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring, } /* WaDisableCtxRestoreArbitration:skl,bxt */ - if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) || - (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) + if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || + IS_BXT_REVID(dev, 0, BXT_REVID_A0)) wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); @@ -1986,7 +1986,7 @@ static int logical_render_ring_init(struct drm_device *dev) ring->init_hw = gen8_init_render_ring; ring->init_context = gen8_init_rcs_context; ring->cleanup = intel_fini_pipe_control; - if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { + if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { ring->get_seqno = bxt_a_get_seqno; ring->set_seqno = bxt_a_set_seqno; } else { @@ -2038,7 +2038,7 @@ static int logical_bsd_ring_init(struct drm_device *dev) GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; ring->init_hw = gen8_init_common_ring; - if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { + if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { ring->get_seqno = bxt_a_get_seqno; ring->set_seqno = bxt_a_set_seqno; } else { @@ -2093,7 +2093,7 @@ static int logical_blt_ring_init(struct drm_device *dev) GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; ring->init_hw = gen8_init_common_ring; - if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { + if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { ring->get_seqno = bxt_a_get_seqno; ring->set_seqno = bxt_a_set_seqno; } else { @@ -2123,7 +2123,7 @@ static int logical_vebox_ring_init(struct drm_device *dev) GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; ring->init_hw = gen8_init_common_ring; - if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { + if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { ring->get_seqno = bxt_a_get_seqno; ring->set_seqno = bxt_a_set_seqno; } else { diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e25791e8748f..579dcb117f72 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -71,7 +71,7 @@ static void skl_init_clock_gating(struct drm_device *dev) gen9_init_clock_gating(dev); - if (INTEL_REVID(dev) <= SKL_REVID_D0) { + if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) { /* WaDisableHDCInvalidation:skl */ I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | BDW_DISABLE_HDC_INVALIDATION); @@ -84,16 +84,15 @@ static void skl_init_clock_gating(struct drm_device *dev) /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes * involving this register should also be added to WA batch as required. */ - if (INTEL_REVID(dev) <= SKL_REVID_E0) - /* WaDisableLSQCROPERFforOCL:skl */ + /* WaDisableLSQCROPERFforOCL:skl */ + if (IS_SKL_REVID(dev, 0, SKL_REVID_E0)) I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | GEN8_LQSC_RO_PERF_DIS); /* WaEnableGapsTsvCreditFix:skl */ - if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) { + if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | GEN9_GAPS_TSV_CREDIT_DISABLE)); - } } static void bxt_init_clock_gating(struct drm_device *dev) @@ -115,14 +114,13 @@ static void bxt_init_clock_gating(struct drm_device *dev) /* WaStoreMultiplePTEenable:bxt */ /* This is a requirement according to Hardware specification */ - if (INTEL_REVID(dev) == BXT_REVID_A0) + if (IS_BXT_REVID(dev, 0, BXT_REVID_A0)) I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); /* WaSetClckGatingDisableMedia:bxt */ - if (INTEL_REVID(dev) == BXT_REVID_A0) { + if (IS_BXT_REVID(dev, 0, BXT_REVID_A0)) I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); - } } static void i915_pineview_get_mem_freq(struct drm_device *dev) @@ -4348,7 +4346,7 @@ static void gen6_set_rps(struct drm_device *dev, u8 val) struct drm_i915_private *dev_priv = dev->dev_private; /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ - if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) + if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) return; WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); @@ -4672,7 +4670,7 @@ static void gen9_enable_rps(struct drm_device *dev) gen6_init_rps_frequencies(dev); /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ - if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) { + if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); return; } @@ -4717,7 +4715,7 @@ static void gen9_enable_rc6(struct drm_device *dev) /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */ if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && - (INTEL_REVID(dev) <= SKL_REVID_E0))) + IS_SKL_REVID(dev, 0, SKL_REVID_E0))) I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); else I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); @@ -4741,8 +4739,8 @@ static void gen9_enable_rc6(struct drm_device *dev) DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); /* WaRsUseTimeoutMode */ - if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) || - (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) { + if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || + IS_BXT_REVID(dev, 0, BXT_REVID_A0)) { I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */ I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | GEN7_RC_CTL_TO_MODE | @@ -4758,8 +4756,9 @@ static void gen9_enable_rc6(struct drm_device *dev) * 3b: Enable Coarse Power Gating only when RC6 is enabled. * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. */ - if ((IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) || - ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0))) + if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || + ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && + IS_SKL_REVID(dev, 0, SKL_REVID_E0))) I915_WRITE(GEN9_PG_ENABLE, 0); else I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 3753e7518d49..f7de5f661240 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -914,17 +914,15 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); - if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 || - INTEL_REVID(dev) == SKL_REVID_B0)) || - (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) { - /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ + /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ + if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || + IS_BXT_REVID(dev, 0, BXT_REVID_A1)) WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, GEN9_DG_MIRROR_FIX_ENABLE); - } - if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || - (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) { - /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ + /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ + if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || + IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, GEN9_RHWO_OPTIMIZATION_DISABLE); /* @@ -934,12 +932,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) */ } - if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) || - IS_BROXTON(dev)) { - /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */ + /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */ + if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) || IS_BROXTON(dev)) WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, GEN9_ENABLE_YV12_BUGFIX); - } /* Wa4x4STCOptimizationDisable:skl,bxt */ /* WaDisablePartialResolveInVc:skl,bxt */ @@ -951,24 +947,22 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) GEN9_CCS_TLB_PREFETCH_ENABLE); /* WaDisableMaskBasedCammingInRCC:skl,bxt */ - if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) || - (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) + if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) || + IS_BXT_REVID(dev, 0, BXT_REVID_A1)) WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, PIXEL_MASK_CAMMING_DISABLE); /* WaForceContextSaveRestoreNonCoherent:skl,bxt */ tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT; - if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) || - (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0)) + if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) || + IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER)) tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE; WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp); /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */ - if (IS_SKYLAKE(dev) || - (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) { + if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0)) WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, GEN8_SAMPLER_POWER_BYPASS_DIS); - } /* WaDisableSTUnitPowerOptimization:skl,bxt */ WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); @@ -1030,11 +1024,11 @@ static int skl_init_workarounds(struct intel_engine_cs *ring) return ret; /* WaDisablePowerCompilerClockGating:skl */ - if (INTEL_REVID(dev) == SKL_REVID_B0) + if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0)) WA_SET_BIT_MASKED(HIZ_CHICKEN, BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); - if (INTEL_REVID(dev) <= SKL_REVID_D0) { + if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) { /* *Use Force Non-Coherent whenever executing a 3D context. This * is a workaround for a possible hang in the unlikely event @@ -1045,19 +1039,17 @@ static int skl_init_workarounds(struct intel_engine_cs *ring) HDC_FORCE_NON_COHERENT); } - if (INTEL_REVID(dev) == SKL_REVID_C0 || - INTEL_REVID(dev) == SKL_REVID_D0) - /* WaBarrierPerformanceFixDisable:skl */ + /* WaBarrierPerformanceFixDisable:skl */ + if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0)) WA_SET_BIT_MASKED(HDC_CHICKEN0, HDC_FENCE_DEST_SLM_DISABLE | HDC_BARRIER_PERFORMANCE_DISABLE); /* WaDisableSbeCacheDispatchPortSharing:skl */ - if (INTEL_REVID(dev) <= SKL_REVID_F0) { + if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) WA_SET_BIT_MASKED( GEN7_HALF_SLICE_CHICKEN1, GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); - } return skl_tune_iz_hashing(ring); } @@ -1077,7 +1069,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) STALL_DOP_GATING_DISABLE); /* WaDisableSbeCacheDispatchPortSharing:bxt */ - if (INTEL_REVID(dev) <= BXT_REVID_B0) { + if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) { WA_SET_BIT_MASKED( GEN7_HALF_SLICE_CHICKEN1, GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); -- 2.1.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2015-10-13 13:17 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-10-06 11:41 [PATCH 1/3] drm/i915: remove parens around revision ids Jani Nikula 2015-10-06 11:41 ` [PATCH 2/3] drm/i915/bxt: add revision id for A1 stepping and use it Jani Nikula 2015-10-06 12:29 ` Ville Syrjälä 2015-10-06 13:43 ` Jani Nikula 2015-10-06 17:50 ` Vivi, Rodrigo 2015-10-06 19:02 ` Ville Syrjälä 2015-10-07 8:32 ` Jani Nikula 2015-10-13 13:16 ` Jani Nikula 2015-10-13 13:17 ` Ville Syrjälä 2015-10-06 11:41 ` [PATCH 3/3] drm/i915: add helpers for platform specific revision id range checks Jani Nikula
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